MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by PZTA92T1/D
High Voltage Transistor
PNP Silicon |
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COLLECTOR 2,4 |
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BASE |
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1 |
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EMITTER 3 |
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MAXIMUM RATINGS |
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Rating |
Symbol |
Value |
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Unit |
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Collector±Emitter Voltage |
VCEO |
± 300 |
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Vdc |
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Collector±Base Voltage |
VCBO |
±300 |
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Vdc |
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Emitter±Base Voltage |
VEBO |
± 5.0 |
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Vdc |
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Collector Current |
IC |
± 500 |
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mAdc |
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Total Power Dissipation up to T = 25°C(1) |
P |
1.5 |
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Watts |
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A |
D |
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Storage Temperature Range |
Tstg |
± 65 to +150 |
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°C |
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Junction Temperature |
TJ |
150 |
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°C |
DEVICE MARKING |
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P2D |
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THERMAL CHARACTERISTICS |
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Characteristic |
Symbol |
Max |
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Unit |
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Thermal Resistance from Junction to Ambient(1) |
RθJA |
83.3 |
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°C/W |
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ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
PZTA92T1
Motorola Preferred Device
SOT±223 PACKAGE
PNP SILICON
HIGH VOLTAGE TRANSISTOR
SURFACE MOUNT
4
1
2
3
CASE 318E±04, STYLE 1
TO±261AA
Characteristic |
Symbol |
Min |
Max |
Unit |
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OFF CHARACTERISTICS
Collector±Emitter Breakdown Voltage (IC = ±1.0 mAdc, IB = 0) |
V(BR)CEO |
± 300 |
Ð |
Vdc |
Collector±Base Breakdown Voltage (IC = ±100 μAdc, IE = 0) |
V(BR)CBO |
± 300 |
Ð |
Vdc |
Emitter±Base Breakdown Voltage (IE = ±100 μAdc, IC = 0) |
V(BR)EBO |
± 5.0 |
Ð |
Vdc |
Collector±Base Cutoff Current (VCB = ± 200 Vdc, IE = 0) |
ICBO |
Ð |
± 0.25 |
μAdc |
Emitter±Base Cutoff Current (VBE = ± 3.0 Vdc, IC = 0) |
IEBO |
Ð |
± 0.1 |
μAdc |
ON CHARACTERISTICS |
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DC Current Gain(2) |
h |
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Ð |
(IC = ± 1.0 mAdc, VCE = ± 10 Vdc) |
FE |
25 |
Ð |
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(IC = ±10 mAdc, VCE = ± 10 Vdc) |
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40 |
Ð |
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(IC = ± 30 mAdc, VCE = ± 10 Vdc) |
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25 |
Ð |
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Saturation Voltages |
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Vdc |
(IC = ±20 mAdc, IB = ±2.0 mAdc) |
VCE(sat) |
Ð |
± 0.5 |
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(IC = ±20 mAdc, IB = ±2.0 mAdc) |
VBE(sat) |
Ð |
± 0.9 |
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DYNAMIC CHARACTERISTICS |
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Collector±Base Capacitance @ f = 1.0 MHz (VCB = ±20 Vdc, IE = 0) |
Ccb |
Ð |
6.0 |
pF |
Current±Gain Ð Bandwidth Product |
fT |
50 |
Ð |
MHz |
(IC = ±10 mAdc, VCE = ± 20 Vdc, f = 100 MHz) |
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1.Device mounted on a glass epoxy printed circuit board 1.575 in. x 1.575 in. x 0.059 in.; mounting pad for the collector lead min. 0.93 in2.
2.Pulse Test: Pulse Width ≤ 300 μs; Duty Cycle = 2.0%.
Thermal Clad is a trademark of the Bergquist Company
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
Motorola Small±Signal Transistors, FETs and Diodes Device Data |
1 |
Motorola, Inc. 1997 |
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PZTA92T1
INFORMATION FOR USING THE SOT±223 SURFACE MOUNT PACKAGE
POWER DISSIPATION
The power dissipation of the SOT±223 is a function of the pad size. These can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SOT±223 package, PD can be calculated as follows.
TJ(max) ± TA
PD = RθJA
The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 1.5 watts.
PD = 150°C ± 25°C = 1.5 watts 83.3°C/W
The 83.3°C/W for the SOT±223 package assumes the recommended collector pad area of 965 sq. mils on a glass epoxy printed circuit board to achieve a power dissipation of 1.5 watts. If space is at a premium, a more realistic approach is to use the device at a PD of 833 mW using the footprint shown. Using a board material such as Thermal Clad, a power dissipation of 1.6 watts can be achieved using the same footprint.
MOUNTING PRECAUTIONS
The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected.
•Always preheat the device.
•The delta temperature between the preheat and soldering should be 100°C or less.*
•When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method, the difference should be a maximum of 10°C.
•The soldering temperature and time should not exceed 260°C for more than 10 seconds.
•When shifting from preheating to soldering, the maximum temperature gradient should be 5°C or less.
•After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress.
•Mechanical stress or shock should not be applied during cooling
* Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection
interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process.
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0.15 |
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3.8 |
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0.079 |
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2.0 |
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0.248 |
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0.091 |
0.091 |
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6.3 |
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2.3 |
2.3 |
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0.079 |
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2.0 |
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0.059 |
0.059 |
0.059 |
inches |
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mm |
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1.5 |
1.5 |
1.5 |
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SOT±223 |
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2 |
Motorola Small±Signal Transistors, FETs and Diodes Device Data |
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