Motorola MVME5500 Programmer's Reference Manual

MVME5500

Single-Board Computer

Programmer’s Reference

Guide

V5500A/PG1

August 2003 Edition

© Copyright 2003 Motorola Inc.

All rights reserved.

Printed in the United States of America.

Motorola and the stylized M logo are trademarks of Motorola, Inc., registered in th e U.S.
Patent and Trademark Office.

All other product or service names mentioned in this document are the property of their
respective owners.

Safety Summary

The following general safety precautions must be observed during all phases of operation, service, and repair of
this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual
could result in personal injury or damage to the equipment.

The safety preca utio ns liste d bel ow re pres ent wa rn ings of ce rt ain dange r s of wh ic h Mo toro la i s aw are. You, as
the user of the product, should follow these warnings and all other safety precautions necessary for the safe
operation of the equipment in your operating environment.

Ground the Instrument.

To minimize shock hazard, th e equipment chassis a nd enclosure must be conne cted to an e lectrical ground. If the
equipment is supplied with a three-conductor AC power cable, the power cable must be plugged into an approved
three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground
(safety ground) at the power outlet. The power jack and mating plug of the power cable meet International
Electrotechnical C om mission (IEC) safety st andards and local electrical regulatory codes.

Do Not Operate in an Explosive Atmosphere.

Do not opera te th e eq u ip ment in an y ex pl os ive at mosp her e such a s i n th e pr esen c e of fl amma ble g ase s or fu mes .
Operation of any el ectrica l equip ment in s uch an environ ment cou ld resul t in an e xplosion and ca use injur y or
damage.

Keep Away From Live Circuits Inside the Equipment.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other
qualified service personnel may remove equipment covers for internal subassembly or component replacement
or any internal adjustment. Service personnel should not replace components with power cable connected. Under
certain condit ions, dangero us voltages may exist e ven with the power cable removed. To avoid inj uries, such
personnel should always disconnect powe r and discharge circuits before touching components.

Use Caution When Exposing or Handling a CRT.

Breakage of a Ca thode-Ray Tube (CRT) causes a hig h-velocity sc attering of glas s fragments (imp losion). To
prevent CRT implosion, do not handle the CRT and avoid rough handling or jarring of the equipment. Handling
of a CRT should be done only by qualified s ervice personnel using approved safety mask and gloves .

Do Not Substitute Parts or Modify Equipment.

Do not install substitut e parts or perfor m any un authoriz ed modi fication of the e quipmen t. Conta ct your loc al
Motorola representative for service and repair to ensure that all safety features are maintained.

Observe Warnings in Manual.

Warnings, such as the example below, precede potentially dangerous procedures throughout this manual.
Instructions containe d in the warni ngs must be fol lowed. You should also employ a ll othe r safe ty preca utions
which you deem necessary for the opera ti on of the equipment in your operating environment.

Warnin g

To prevent serious injury or death from dangerous voltages, use extreme
caution when handling, testing, and adjusting this equipment and its

Warning

components.

Flammability

All Motorola PWBs (printed wiring boards) ar e manufactured with a flammability rating
of 94V-0 by UL-recognized manufacturers.

EMI Caution

Caution

!

Caution

This equipment generate s, uses a nd can ra diate elect romagnet ic ene r gy. It
may cause or be susceptible to electromagnetic interference (EMI) if not
installed and used with adequate EMI protection.

Lithium Battery Caution

This product contains a lithium battery to power the clock and calendar circuitry.

Caution

!

Caution

Caution

!

Attention

Caution

!

Vorsicht

Danger of explos ion if batt ery is repla ced incorrect ly . Replace battery o nly
with the same or equivalent type recommended by the equipment
manufacturer. Dispose of used batteries according to the manufacturer’s
instructions.

Il y a danger d’explosion s’il y a remplacement incorrect de la batterie.
Remplacer uniquement avec une batterie du même type ou d’un type
équivalent recommandé par le constructeur. Mettre au rebut les batteries
usagées conformément aux instructions du fabricant.

Explosionsgefahr b ei uns achg emäßem Austausch der Batt er ie . Ers atz nur
durch denselben ode r einen v om Herstell er empfohlene n Typ. En tsor gung
gebrauchter Batterien nach Angaben des Herstellers.

CE Notice (European Community)

Warnin g

!

Warning

Motorola Computer Gr oup product s with the CE marking co mply with the EMC Dir ective
(89/336/EEC). Compliance with this directive implies conformity to the following
European Norms:

EN55022 “Limits and Methods of Measur ement of Ra dio Int erferen ce Chara cteri stic s
of Information Technology Equipment”; this product tested to Equipment Class A

EN55024 “Information te chnology equipment—Immunity c haracteristics—Limits an d
methods of measurement”

Board products are tested in a representative system to show compliance with the above
mentioned requirements. A proper installation in a CE-marked system will maintain the
required EMC performance.

In accordance with European Community directives, a “Declaration of Conformity” has
been made and is available on request. Please contact your sales representative.

This is a Class A product. In a domestic environment, this product may
cause radio interference, in which case the user may be required to take
adequate measures.

Notice

While reasonable efforts have been made to assure the accuracy of this document,
Motorola, Inc. a ssumes n o liabil ity res ulting f rom any omissions in thi s document, or fr om
the use of the information obtained therein. Motorola reserves the right to revis e this
document and to make c hanges from time to ti me in t he cont ent hereof without o bli gation
of Motorola to notify any person of such revision or changes.

Electronic versions of this material may be read online, downloaded for personal use, or
referenced in another document as a URL to the Motorola Computer Group Web site. The
text itself may n ot be published co mmercially in p rint or electroni c form, edited, tr anslated,
or otherwise altered without the permission of Motorola, Inc.

It is possible that t h i s pub li cat ion may contain reference to or information abou t Motorola
products (machines and pr ograms), progra mming, or servi ces that are not av ailable in yo ur
country. Such references or information must not be construed to mean that Motorola
intends to announce such Motorola products, programming, or services in your country.

Limited and Restricted Rights Legend

If the documentation contained herein is supplied, directly or indirectly, to the U.S.
Government, the following notice shall apply unless otherwise agreed to in writing by
Motorola, Inc.

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in
subparagraph (b)(3) of the Rig hts i n Tech nical Data clause at DFARS 252.227-7013 (Nov.

1995) and of the Rights in Noncommerc ial Computer Software and Doc umentation c lause
at DFARS 252.227-7014 (Jun. 1995).

Motorola, Inc.
Computer Group
2900 South Diablo Way
Tempe, Arizona 85282

About This Guide

Overview of Contents .............................................................................................. xiii

Comments and Suggestions ......................................................................................xiv

Conventions Used in This Manual ............................................................................xiv

CHAPTER 1 Board Description and Memory Maps

Introduction .............................................................................................................. 1-1

Overview .................................................................................................................. 1-1

Memory Maps ....... .................................. ..... .................................. ...... ...... .............. 1-5

Default Processor Memory Map ....................................................................... 1-5

MOTLoad’s Processor Memory Map ............................................................... 1-6

Default PCI Memory Map ................................ .................................. ..... ...... ...1-7

MOTLoad’ s PCI Memory Maps ......................................................... ..... ......... 1-9

PCI I/O Space Maps .......................................................................................... 1-9

System I/O Memory Map ............................................................................... 1-10

System Status Register 1 ..................................................................................1-11

System Status Register 2 ................................................................................. 1-13

System Status Register 3 ................................................................................. 1-15

Presence Detect Register ................................................................................. 1-16

Configuration Header/Switch Register (S1) ................................................... 1-17

Time Base Enable Register ............................................................................. 1-18

Geographical Address Register (S2) ............................................................... 1-18

COM1 & COM2 Universal Asynchronous Receiver/Transmitter (UART) ... 1-20

Real-Time Clock and NVRAM ...................................................................... 1-20

ISA Local Resource Bus ........................................................................................ 1-20

Contents

CHAPTER 2 Programming Details

Introduction .............................................................................................................. 2-1

PCI Configuration Space and IDSEL Mapping ....................................................... 2-1

Interrupt Controller .................................................................................................. 2-3

T wo- Wire Serial Interface ....................... ..... .................................. ...... ...... .............. 2-5

GT-64260B Initialization .......................................................................................... 2-7

GT-64260B GPP Configuration ............................................................................... 2-7

GT-64260B Reset Configuration .............................................................................. 2-9

vii

GT-64260B Device Controller Bank Assignments .................................................2-11

System Clock Generators .......................................................................................2-13

VPD and User Configuration EEPROMs ...............................................................2-14

Temperature Sensor ................................................................................................2-14

Flash Memory .........................................................................................................2-14

PCI Arbitration Assignments ..................................................................................2-14

Other Software Considerations ...............................................................................2-15

CPU Bus Mode ................................................................................................2-15

Processor Ty pe Identification .................. ...... ..... .................................. ...... .....2-16

Processor PLL Configuration ............................. ...... .......................................2-16

L1, L2, L3 Cache .............................................................................................2-16

APPENDIX A Vital Product Data

Flash Memory Configuration Data ..........................................................................A-1

L3 Cache Configuration Data ..................................................................................A-3

APPENDIX B Related Documentation

Motorola Computer Group Documents ................................................................... B-1

Manufacturers’ Documents ..................................................................................... B-2

Related Specifications ............................................................................................. B-5

viii

List of Figures

Figure 1-1. MVME5500 Block Diagram ................................................................ 1-4

ix

List of Tables

T ab le 1-1. MVME5500 Features Summary ................................................... ...... ...1-2

Table 1-2. Default Processor Memory Map ............................................................ 1-5

Table 1-3. MOTLoad’s Processor Memory Map .................................................... 1-6

Table 1-4. Default PCI Memory Map ..................................................................... 1-7

Table 1-5. MOTLoad’s PCI 0 Domain Memory Map ............................................. 1-9

Table 1-6. MOTLoad’s PCI 1 Domain Memory Map ............................................. 1-9

Table 1-7. PCI 0 Domain I/O Map .......................................................................... 1-9

Table 1-8. PCI 1 Domain I/O Map ........................................................................ 1-10

Table 1-9. Device Bank 1 I/O Memory Map ........................................................ 1-10

Table 1-10. System Status Register 1 .....................................................................1-11

T ab le 1-11. System Status Register 2 .................................................................... 1-13

Table 1-12. System Status Register 3 .................................................................... 1-15

Table 1-13. Presence Detect Register .................................................................... 1-16

T ab le 1-14. Configuration Header/Switch Register ................. ..... ........................ 1-17

T ab le 1-15. TBEN Register ...................................................... ..... ...... .................. 1-18

Table 1-16. Geographical Address Register .......................................................... 1-19

Table 2-1. IDSEL Mapping for PCI Devices .......................................................... 2-2

Table 2-2. GT-64260B External GPP Interrupt Assignments ................................. 2-4

Table 2-3. I2C Bus Device Addressing ................................................................... 2-6

T ab le 2-4. GT-64260B GPP Pin Function Assignments ........................... ..... ...... ...2-7

T ab le 2-5. GT-64260B Power -Up Con figu ration Settings ................................... . 2-10

Table 2-6. Device Bank Assignments ................................................................... 2-12

Table 2-7. Device Bank Timing Parameters .........................................................2-12

T ab le 2-8. PCI Arbiter Assignments ................. ...... .................................. ..... ...... .2-15

Table 2-9. Processor L3CR Register Assignments ............................................... 2-16

Table A-1. Flash 0 Memory Configuration Data ....................................................A-1

Table A-2. Flash 1 Memory Configuration Data ....................................................A-2

Table A-3. L3 Cache Configuration Data ...............................................................A-3

Table B-1. Motorola Computer Group Documents ................................................. B-1

T ab le B-2. Manufacturers’ Documents ...................................................................B-2

T ab le B-3. Related Specifications ............................................................. ..... .........B-5

xi

About This Guide

The MVME5500 Single-Bo ard Computer Programmer’s Reference Guide
provides general programming information, including memory maps,
interrupts, and register data for the MVME5500 family of boards. This
document should be used by anyone who wants general, as well as
technical information about the MVME5500 products.

As of the printing date of this manual, the MVME5500 supports the
models listed below.

Model Number Description

MVME5500-0161 1 GHz MPC7455 processor, 512MB SDRAM,

MVME5500-0163 1 GHz MPC7455 processor, 512MB SDRAM,

Overview of Contents

This manual is divided into the following chapters and appendices:

Scanbe handles

IEEE handles

Chapter 1, Board Desc ription and Memory Maps, provid es a brief product

description and a block diagram. The remainder of the chapter provides
information on memory maps and system and configuration registers.

Chapter 2, Programming Details, provides additional programming

information including IDSEL mapping, interrupt assignments for the
GT-64260B system processor, two-wire serial interface addressing, and
other device and system considerations.

Appendix A, Vital Product Data, provides a listing of vital product data

(VPD) related to this product.

Appendix B, Related Documentation, provides a listing of related

Motorola manuals, vendor documentation, and industry specifications.

xiii

Comments and Suggestions

Motorola welcomes and appreciates yo ur comments on its doc umentation.
W e want to know wh at you think about our manuals and how we can make
them better. Mail comments to:

Motorola Computer Group
Reader Comments DW164
2900 S. Diablo Way
Tempe, Arizona 85282

You can also submit comments to the following e-mail address:

[e-mail]

In all your correspondenc e, pleas e list your name, pos itio n, and comp any.
Be sure to include the title and part number of the manual and tel l how you
used it. Then tell us your feelings about its strengths and weaknesses and
any recommendations for improvements.

Conventions Used in Th is Manual

The following typographical conventions are used in this document:

bold

xiv

is used for user inpu t that you t ype just as i t appears ; it is also us ed for
commands, options and arguments to commands, and names of
programs, directories and files.

italic

is used for names of variable s to which you assign value s, for funct ion
parameters, and for structure names and fields. Italic is also used for
comments in screen displays and examples, and to introduce new
terms.

courier

is used for system output (for example, screen displays, reports),
examples, and system prompts.

<Enter>, <Return> or <CR>

represents the carriage return or Enter key.

Ctrl

represents the Con trol key. Execute control c harac ters by pr ess ing t he
Ctrl key and the letter simultaneously, for example, Ctrl-d.

xv

1Board Description and Memory

Introduction

This chapter briefly describes the board level hardware features of the
MVME5500 single-board computer, including a table of features and a
block diagram. The remainder of the chapter provides memory map
information including a default memory map, MOTLoad’s processor
memory map, a default PCI memory map, MOTLoad’ s PCI memory map,
a PCI I/O memory map, and system I/O memory maps.

Programmable registers in the GT-64260B system controller are
documented in publication MV-S100414-00 Rev A, which is obtainable
from Marvell Technologies, Ltd. Refer to Appendix B, Related

Documentation for more information.

Overview

The MVME5500 is a single-board computer based on the PowerPC
MPC7455 processor and the Marvell GT-64260B host bridge with a dual
PCI interface and memory controller. On-board payload includes two
PMC slots, two SDRAM banks, an expans ion connector for two addi tional
banks of SDRAM, 8MB boot Fla sh ROM, one 10/100/ 1000 Ethernet po rt,
one 10/100 Ethernet port, 32MB expansion Flash ROM, two serial ports,
and an NVRAM and real-time clock.

Maps

1

1-1

Board Description and Memory Maps

1

The following table lists the features of the MVME5500.

Tab le 1-1. MVME5500 Feat ures Su mmar y

Feature Description

Processor – Single 1 GHz MPC7455 processor

– Bus clock frequency at 133 MHz

L3 Cache – 2MB using DDR SRAM

– Bus clock frequency at 200 MHz

Flash – 8MB Flash soldered on board

– 32MB expansion Flash soldered on board

System Memory – Two banks on-board for 512MB using 256Mb devices

– Expansion connector for a mezzanine board with two banks for
512MB using 256Mb devices
– Double-bit-error detect, single-bit-error correct across 72 bits
– Bus clock frequency at 133 MHz

Memory Controller – Provided by GT-64260B

– Supports one to four banks of SDRAM at up to 1GB per bank

Processor Host Bridge – Provided by GT-64260B

– Supports MPX mode or 60x mode

PCI Interfaces – Provided by GT-64260B

– T wo independent 64-bit interfaces, one compliant to PCI spec rev

2.1 (Bus 0.0) and the other compl iant to PCI spec rev 2.2 (Bus 1. 0)
– Bus clock frequency at 66 MHz

– Provided by the HiNT PCI 6154 secondary interface
– One 64-bit interface, compliant to PCI spec rev 2.1 (Bus 0.1)
– Bus clock frequency at 33 MHz

Interrupt Controller – Provided by GT-64260B

– Interrupt sources internal to GT-64260B
– Up to 32 external interrupt inputs
– Up to seven interrupt outputs

Counters/Timers – Eight 32-bit counters/timers in GT-64260B

1-2 Computer Group Literature Center Web Site

Table 1-1. MVME5500 Features Summary (continued)

Feature Description

I2C – Provided by GT-64260B

– Master or slave capable
– On-board serial EEPROMs for V PD, SP D, GT-64260B init, and

user data storage
NVRAM – 32KB provided by MK48T37
Real Time Clock – Provided by MK48T37
Watchdog Timers – One in GT-64260B

– One in MK48T37

– Each watchdog timer can generate interrupt or reset, software

selectable

Overview

1

On-board Peripheral
Support

PCI Mezzanine Cards – Two PMC sites (one shared with the expansion memory and has

PCI Expansion – One expansion connector for interface to PMCspan
Miscellaneous – Reset/Abort switch

Form Factor – Standard VME

– One 10/100/1000BaseT Ethernet interface, one 10/100BaseT

Ethernet interface

– Dual 16C550 compatible UARTs

IPMC capability)

– Front panel status indicators, Run and Board Fail

http://www.motorola.com/computer/literature 1-3

Board Description and Memory Maps

1

Figure 1-1. MVME5500 Block Diagram

1-4 Computer Group Literature Center Web Site

Memory Maps

Default Processor Memory Map

When power is first applied or a hard reset has occurred, the GT-64260B
has a default addre ss map. Table 1-2 shows the default proc ess or memory
map.

Table 1-2. Default Processor Memory Map

Processor Address

Size Definition NotesStart End

0000 0000 007F FFFF 8MB SDRAM Bank 0
0080 0000 00FF FFFF 8MB SDRAM Bank 1
0100 0000 017F FFFF 8MB SDRAM Bank 2
0180 0000 01FF FFFF 8MB SDRAM Bank 3
0200 0000 0FFF FFFF 224MB U nas sign e d

Memory Maps

1

1000 0000 11FF FFFF 32MB PCI Bus 0 I/O Space
1200 0000 13FF FFFF 32MB PCI Bus 0 Memory Space 0
1400 0000 1BFF FFFF 128MB U nas signed
1C00 0000 1C7F FFFF 8MB Device Port CS0
1C80 0000 1CFF FFFF 8MB Device Port CS1
1D00 0000 1DFF FFFF 16MB Device Port CS2
1E00 0000 1FFF FFFF 32MB Unassigned
2000 0000 21FF FFFF 32MB PCI Bus 1 I/O
2200 0000 23FF FFFF 32MB PCI Bus 1 Memory Space 0
2400 0000 25FF FFFF 32MB PCI Bus 1 Memory Space 1
2600 0000 27FF FFFF 32MB PCI Bus 1 Memory Space 2
2800 0000 29FF FFFF 32MB PCI Bus 1 Memory Space 3
2A00 0000 F0FF FFFF 3184MB Unassigned

http://www.motorola.com/computer/literature 1-5

Board Description and Memory Maps

1

Table 1-2. Default Processor Memory Map (continued)

Processor Address

Size Definition NotesStart End

F100 0000 F100 FFFF 64KB Internal Registers 1
F101 0000 F1FF FFFF 16MB -

64KB
F200 0000 F3FF FFFF 32MB PCI Bus 0 Memory Space 1
F400 0000 F5FF FFFF 32MB PCI Bus 0 Memory Space 2
F600 0000 F7FF FFFF 32MB PCI Bus 0 Memory Space 3
F800 0000 FEFF FFFF 112MB Unassigned
FF00 0000 FF7F FFFF 8MB Device Port CS3
FF80 0000 FFFF FFFF 8MB Boot Flash Bank 2

Unassigned

Notes 1. Set by configuration resistors.

2. Sele cts Flash 0 or Flash 1 dep ending on the state of th e Flash
boot bank select jumper.

MOTLoad’s Processor Memory Map

MOTLoad’s processor memory map is given in the following table.

Table 1-3. MOTLoad’s Processor Memory Map

Processor Address

Size Definition NotesStart End

0000 0000 7FFF FFFF 2GB On-Board SDRAM 1
8000 0000 DFFF FFFF 768MB PCI 0 Domain Memory Space
E000 0000 EFFF FFFF 1GB PCI 1 Domain Memory Space
F000 0000 F07F FFFF 8MB PCI 0 Domain I/O Space 2
F080 0000 F0FF FFFF 8MB PCI 1 Domain I/O Space 2

1-6 Computer Group Literature Center Web Site

Default PCI Memory Map

Table 1- 3. MOTLoad’s Processor Memory Map (continued)

Processor Address

Size Definition NotesStart End

F100 0000 F10F FFFF 1MB GT-64260B Internal Registers
F110 0000 F11F FFFF 1MB GT-64260B Device Bus Registers 3
F120 0000 F1FF FFFF 14MB Reserved
F200 0000 FE00 0000 32MB Flash Bank 0 4
FF80 0000 FFFF FFFF 8MB Flash Bank 1 4

Notes 1. Maximum size is 2GB. Actual size depends on the amount

of memory installed.

2. Zero-based I/O space.

3. Device chip select 1.

4. Flash 0/Flash 1 can be mapped to device chip select 0 or
BOOT chip select depending on the state of the Flash boot
bank select header.

1

Default PCI Memory Map

T able 1-4 is th e default PCI mem ory map for eac h PCI bus foll owing reset.

Table 1-4. Default PCI Memory Map

PCI Address

Size DefinitionStart End

0000 0000 007F FFFF 8MB SDRAM Bank 0
0080 0000 00FF FFFF 8MB SDRAM Bank 1
0100 0000 017F FFFF 8MB SDRAM Bank 2
0180 0000 01FF FFFF 8MB SDRAM Bank 3
0200 0000 0FFF FFFF 224MB Unassigned

http://www.motorola.com/computer/literature 1-7

Board Description and Memory Maps

1

Table 1- 4. Default PCI Memory Map (continued)

PCI Address

Size DefinitionStart End

1000 0000 11FF FFFF 32MB PCI Bus 1 P2P I/O Space
1200 0000 13FF FFFF 32MB PCI Bus 1 P2P Memory Space 0
1400 0000 1400 FFFF 64KB Internal Registers
1401 0000 1BFF FFFF 128MB -

64KB
1C00 0000 1C7F FFFF 8MB Device Port CS0
1C80 0000 1CFF FFFF 8MB Device Port CS1
1D00 0000 1DFF FFFF 16MB Device Port CS2
1E00 0000 1FFF FFFF 32MB Unassigned
2000 0000 21FF FFFF 32MB PCI Bus 0 P2P I/O Space
2200 0000 23FF FFFF 32MB PCI Bus 0 P2P Memory Space 0
2400 0000 25FF FFFF 32MB PCI Bus 0 P2P Memory Space 1
2600 0000 F1FF FFFF 3264MB Unassigned
F200 0000 F3FF FFFF 32MB PCI Bus 1 P2P Memory Space 1
F400 0000 FEFF FFFF 176MB Unassigned
FF00 0000 FF7F FFFF 8MB Device Port CS3
FF80 0000 FFFF FFFF 8MB Boot Flash Bank

Unassigned

1-8 Computer Group Literature Center Web Site

MOTLoad’s PCI Memory Maps

MOTLoad’s PCI Memory Maps

MOTLoad’s PCI memory map for each PCI domain is shown in the
following tables.

Table 1-5. MOTLoad’s PCI 0 Domain Memory Map

PCI 0 Memory Address

Size DefinitionStart End

0000 0000 7FFF FFFF 2GB On-Board SDRAM
8000 0000 DFFF FFFF 768MB Local PCI 0 Domain Memory Space
F000 0000 FFFF FFFF 256MB Reserved

Table 1-6. MOTLoad’s PCI 1 Domain Memory Map

PCI 1 Memory Address

Size DefinitionStart End

1

0000 0000 7FFF FFFF 2GB On-Board SDRAM
E000 0000 EFFF FFFF 1GB Local PCI 1 Domain Memory Space
F000 0000 FFFF FFFF 256MB Reserved

PCI I/O Space Maps

The PCI I/O space map for each PCI domain is shown in the following
tables.

Table 1-7. PCI 0 Domain I/O Map

PCI 0 I/O Address

Size DefinitionStart End

0000 0000 007F FFFF 8MB Local PCI Domain I/O Space

http://www.motorola.com/computer/literature 1-9

Board Description and Memory Maps

1

Table 1-8. PCI 1 Domain I/O Map

PCI 1 I/O Address

Size DefinitionStart End

0000 0000 007F FFFF 8MB Local PCI Domain I/O Space

System I/O Memory Map

System resources f or the MVME55 00 board i ncluding sy stem control and
status registers, NVRAM/RTC, and the 16550 UARTs are mapped into a
1MB address range assigned to device bank 1. The region defined by
device bank 1 resides within the GT-64260B device bus register’s space
listed in Table 1-3 on page 1-6. The memory map is defined in the
following table:

Table 1-9. Device Bank 1 I/O Memory Map

Device Bank1
Address Offset Definition

0 0000 System Status Register 1
0 0001 System Status Register 2
0 0002 System Status Register 3
0 0003 Reserved
0 0004 Presence Detect Register
0 0005 Software Readable Header/Switch
0 0006 Timebase Enable Register
0 0007 Geographical Address Register (VME board)
0 0008 - 0 FFFF Reserved for future on-board registers
1 0000 - 1 7FFF M48T37V NVRAM/RTC
2 0000 - 2 0FFF COM1 16550 UART
2 1000 - 2 1FFF COM2 16550 UART
2 4000 - F FFFF Reserved (undefined)

1-10 Computer Group Literature Center Web Site

System Status Register 1

The MVME5500 board system status register 1 is used to provide board
status information and software control of Abort.

Tabl e 1-10. System Status Register 1

REG System Status Register 1 - Offset 0x0 0000
BIT 76543210
FIELD

System Status Register 1

1

REF_CLK

OPER RRRR/WRRRR
RESET XXX1 XX00

BANK_SEL

SAFE_START

ABORT_

FLASH_BSY_

FUSE_STAT

RSVD

RSVD

REF_CLK

Reference clock. This bit reflects the current state of the 28.8 KHz
reference clock derived from the 1.8432 MHz UART oscillator
divided by 64. This clock may be used as a fixed timing reference.

BANK_SEL

Boot Flash bank select. This bit reflects the current state of the boot
Flash bank select jumpe r. A cleared condition ind icate s that Flas h 0 i s
the boot bank. A set condition indicates that Flash 1 is the boot bank.

SAFE_START

ENV safe start. This bit refl ects the cu rrent sta te of the ENV safe st art
select jumper. A cleared condition indicates that the ENV settings
programmed in NVRAM, VPD, and SPD should be used by the
firmware. A set condition indicates that firmware should use the safe
ENV settings.

http://www.motorola.com/computer/literature 1-11

Board Description and Memory Maps

1

ABORT_

This bit reflects the current state of the on-board abort signal. Writing
a 0 at this bit position asserts the abort interrupt output signal, while
writing a 1 at this bit position clears the abort interrupt output signal.
Reading a 1 at this bit position indicates that the abort switch is
deasserted, whil e reading a 0 at this bit position indi cates that t he abort
switch is asserted.

FLASH_BSY_

Flash busy. This bit provides the current state of the Flash 0
StrataFlash device status pins. These two open drain output pins are
wire ORed. Refer to the appr opria te Intel StrataFlash data sheet for a
description on the function of the status pin.

FUSE_STAT

Fuse status. This bit indicates t he status of the soldered, on-board fuses
(R199 and R188). A cleared condition indicates that one of the fuses
is open. A se t condition indicates that all fuses are function al.

1-12 Computer Group Literature Center Web Site

System Status Register 2

The MVME5500 board system status register 2 provides board con trol and
status bits.

Ta bl e 1-11. System Status Register 2

REG System Status Register 2 - Offset 0x0 0001
BIT 76543210
FIELD

System Status Register 2

1

BD_FAIL

OPER R/WR/WR/WR/WRRRR
RESET 111100XX

EEPROM_WP

FLASH_WP

TSTAT_MASK

RSVD

PCI 0.1_M66EN

PCI 1.0_M66EN

PCI 0.0_M66EN

BD_FAIL

Board fail. T his bit is used to c ontrol the board fail LED. A set
condition illuminates the front-panel LED and a cleared condition
extinguishes the front-panel LED.

EEPROM_WP

EEPROM write protect. This bit is to provide protection against
inadvertent writes to the on -board EEPROM device s. Clea ring t he bit
enables writes to the EEPROM devices. Setting this bit write protects
the devices. The devices are write protected following a reset.

FLASH_WP

Flash write protect. This bit is used to provide protection against
inadvertent writes to both Flash 0 and Flash 1 memory devices.
Clearing this bit enables writes to the Flash devices. Setting this bit
write protects the devices. This bit is set during reset and must be
cleared by the system software to enable writing of the Flash devices.

http://www.motorola.com/computer/literature 1-13

Board Description and Memory Maps

1

TSTAT_MASK

Thermostat mask. This bit is used to mask the DS1621 tempe rature
sensor thermostat out put. If thi s bit is c leared, th e thermo stat outp ut is
enabled to generate an interrupt on GPP 3. If the bit is set, the
thermostat output is disabled from generating an interrupt.

PCI0.1_M66EN

PCI Bus 0.1 M66EN. This bit reflects the state of the PCI Bus 0.1
M66EN pin. A cleared condition indicates that PCI Bus 0.0 is
operating at 33 MHz. A set cond ition indicates that the bus is operating
at 66 MHz. This bit is always cleared on the MVME5500.

PCI1.0_M66EN

PCI Bus 1.0 M66EN. This bit reflects the state of the PCI Bus 1.0
M66EN pin. A cleared condition indicates that PCI Bus 1.0 is
operating at 33 MHz. A set cond ition indicates that the bus is operating
at 66 MHz.

PCI0.0_M66EN

PCI Bus 0.0 M66EN. This bit reflects the state of the PCI Bus 0.0
M66EN pin. A cleared conditi on ind icates that PCI Bus 0 is operati ng
at 33 MHz. A set condition indicates that the bus is operating at
66 MHz.

1-14 Computer Group Literature Center Web Site

System Status Register 3

The MVME5500 board system status register 3 provides the board
software-controlled reset functions.

Tabl e 1-12. System Status Register 3

REG System Status Register 3 - Offset 0x0 0002
BIT 76543210
FIELD

System Status Register 3

1

BRD_RST

OPER WRRRR/WRRR
RESET 00001000

RSVD

RSVD

RSVD

ABT_INT_MASK

RSVD

RSVD

RSVD

BRD_RST

Board reset. Setting this bit forces a hard reset of the MVME5500
board. This bit clears automatically when the board reset is complete.

ABT_INT_MASK

Abort interrupt mask. This bit is used to mask the abort interrupt. If
this bit is set, the abort interrupt is masked so the abort interrupt is not
generated. If the bit is cleared, the abort interrupt may be generated.

http://www.motorola.com/computer/literature 1-15

Board Description and Memory Maps

1

Presence Detect Register

The MVME5500 board contains a presence detect register that may be
read by the sys tem sof tware to de term ine t he pr esence of op ti onal device s.

Tabl e 1-13. Presence Det ec t Regi st er

REG Presence Detect Register - Offset 0x0 0004h
BIT 76543210
FIELD

RSVD

OPER RRRRRRRR
RESET 11 1 1 1 X X X

PMC_SPANP_

RSVD

RSVD

RSVD

RSVD

PMC_SPANP_

PMC2P_

PMC1P_

PMC expansion module present. If set, there is no PMC expansion
module installed. If cleared, the PMC expansion module is installed.

PMC2P_

PMC module 2 present. If set, there is no PMC module installed in
position 2. If cleared, the PMC module is installed.

PMC1P_

PMC module 1 present. If set, there is no PMC module installed in
position 1. If cleared, the PMC module is installed.

1-16 Computer Group Literature Center Web Site

Configuration Header/Switch Register (S1)

Configuration Header/Switch Register (S1)

The MVME5500 board has an 8-bit he ade r or swit ch that may be read by
the software.

Table 1-14. Configuration Header/Switch Register

REG Configuration Header/Switch Register - Offset 0x0 0005h
BIT 76543210
FIELD

1

OPER RRRRRRRR
RESET XXXXXXXX

CFG[7-0]

Configuration bits 7-0. These bits reflect the position of the switch
installed in the soft ware readable hea der location . A cleared condition
indicates that t he swi tch i s ON for the h eader posit io n asso ciate d with
that bit and a set condition indicates that the switch is OFF.

1

12345678

ON ON

16 16

CFG_7

CFG_0 = 0
CFG_1 = 0
CFG_2 = 0
CFG_3 = 0
CFG_4 = 0
CFG_5 = 0

CFG_6

CFG_5

CFG_4

1

CFG_3

12345678

CFG_2

CFG_1

CFG_0

CFG_0 = 1
CFG_1 = 1
CFG_2 = 1
CFG_3 = 1
CFG_4 = 1

CFG_5 = 1
CFG_6 = 0
CFG_7 = 0

http://www.motorola.com/computer/literature 1-17

CFG_6 = 1

CFG_7 = 1

Board Description and Memory Maps

1

Time Base Enable Register

The time base enable (TBEN) register provides the means to control the
processor’s TBEN input.

Ta ble 1-15. TBEN Register

REG TBEN Register- Offset 0x0 0006
BIT 76543210
FIELD

RSVD

OPER RRRRRRRR/W
RESET 00000001

RSVD

RSVD

TBEN0

Processor time base enabl e. When this bi t is cleare d, the TBEN pin of
the processor is dr iven low . When this bit is set, the TBEN pin is driven
high.

Geographical Address Register (S2)

This register ref lects the inverted s tates of t he geographi cal address pins at
the 5-row, 160-pin P1 connector. Applications not using the 5-row
backplane can use a planar switch (same type as the Configuration

Header/Switch Register (S1) on page 1-17) to assign a geographical

address according to the following diagram.

RSVD

RSVD

RSVD

RSVD

TBEN0

1-18 Computer Group Literature Center Web Site

Geographical Address Register (S2)

Note The switch positions must all be turned off whe n the

MVME5500 is used in a 5-row backplane.

Table 1-16. Geographical Address Register

REG Geographical Address Register - 0xFF100007
BIT 7 6543210
FIELD

1

OPER R RRRRRRR
RESET X XXXXXXX

1

12345678

ON ON

16 16

VMEGA0_

GAP* = 0
Not used
Not used
GA4* = 0
GA3* = 0
GA2* = 0
GA1* = 0
GA0* = 0

VMEGA1_

VMEGA2_

VMEGA3_

1

VMEGA4_

12345678

RSVD

RSVD

GAP* = 1
Not used
Not used
GA4* = 1
GA3* = 1
GA2* = 1
GA1* = 1
GA0* = 1

VMEGAP_

http://www.motorola.com/computer/literature 1-19

Board Description and Memory Maps

1

COM1 & COM2 Universal Asynchronous Receiver/Tr ansmitter (UART)

COM1 and COM2 are PC16550 Universal Asynchronous
Receiver/T ransmit ter (UART) to provide an asynchronous seri al inter face
for test/debug purposes. To facilitate proper baud rate generation, the
frequency of the input clock for the PC16550 UART is fixed at

1.8432 MHz. For additional programming details, refer to the PC16550
Data Sheet.

Real-Time Clock and NVRAM

The SGS-Thomson M48T37 is used by the MVME5500 bo ard to provi de
32KB of non-volatile static RAM, real-time clock, and watchdog timer
functions. The device is accessed as linear memory . Refer to the MK48T37
Data Sheet for programming information.

ISA Local Resource Bus

The ISA local resources exist only if an IPMC712/761 module is mounted
on the MVME5500. Refer to the IPMC712/761 I/O Module Installation
and Use, listed in Appendix B, Related Documentation.

1-20 Computer Group Literature Center Web Site

Introduction

This chapter includes additional programming information for the
MVME5500 single-board computer. Items discussed include:

❏ PCI Configuration Space and IDSEL Mapping on page 2-1
❏ Interrupt Controller on page 2-3
❏ Two-Wire Serial Interface on page 2-5
❏ GT-64260B Initialization on page 2-7
❏ GT-64260B GPP Configuration on page 2-7
❏ GT-64260B Reset Configuration on page 2-9
❏ GT-64260B Device Controller Bank Assignmen ts on page 2-11
❏ System Clock Generators on page 2-13

2Programming Details

2

❏ VPD and User Configuration EEPROMs on page 2-14
❏ Temperature Sensor on page 2-14
❏ Flash Memory on page 2-14
❏ PCI Arbitration Assignments on page 2-14
❏ Other Software Considerations on page 2-15

PCI Configuration Sp ace and IDSEL Mappin g

Each PCI device has an ass ociat ed addr ess li ne conne cted vi a a resi stor to
its IDSEL pin for configuration space accesses. Table 2-1 shows the
IDSEL assignments for the PCI devices on each of the PCI buses on the
MVME5500 board along with the corresponding interrupt assignment to
the general-purpose port (GPP) pins. Refer to the GT-64260B System

Controller for PowerPC Processors Data Sheet and the PCI 6154 (HB2)
PCI-to-PC I Bridge Data Book, both listed in Appendix B, Related

2-1

Programming Details

2

Documentation, for details on generating configuration cycles on each of

the PCI buses.

Table 2-1. IDSEL Mapping for PCI Devices

PCI
PCI
Bus

0.0 0b0_0001 AD11 IPMC 11

0.1 0b0_0000 AD16 CA91C142D VME

Device
Number Field

0b0_0110 AD16 PMC 1

0b0_0111 AD17 PMC 1 IDSEL B
0b0_1010 AD20 HiNT PCI 6154

0b1_0101 AD31 GT-64260B PCI

AD

Line

Physical PCI
Device

(J11,12,13,14)

Bridge

Bridge

VLINT0
CA91C142D VME

VLINT1
CA91C142D VME

VLINT2
CA91C142D VME

VLINT3

Device INT# to GPP Interrupt
Input

INTA# INTB# INTC# INTD#

891011

12

13

14

15

0b0_0100 AD20 PMC Expansion 12 13 14 15

Note Device-specific interrupt
routing is established on the PMCspan
board. Refer to the PMCspan PMC

Adapter Carrier Board Installation
and Use manual, listed in Appendix

B, Related Documentation.

2-2 Computer Group Literature Center Web Site

Interrupt Controller

Table 2-1. IDSEL Mapping for PCI Devices (continued)

PCI
PCI
Bus

1.0 0 b0_0110 AD16 PMC 2

Device
Number Field

0b0_0111 AD17 PMC 2 IDSEL B
0b0_1010 AD20 82C544 Ethernet 1 20
0b1_0101 AD31 GT-64260B PCI

AD

Line

Physical PCI
Device

(J21,22,23,24)

Bridge

Interrupt Controller

The MVME5500 uses the GT-64260B interrupt controller to handle
interrupts internal to the GT-64260B, as well as the external interrupt
sources. The GT-64260B has a limited number of directly triggerable
interrupt inputs. Each of the GPP pins can be configured for an interrupt
input, but the inpu ts are combine d internall y in groups of eight inputs (one
for each byte lane) for one interrupt source. Therefore, interrupt inputs in
each byte lane are essentially shared. Currently defined external
interrupting devices and GPP interrupt assignments are shown in Table

2-2.

2

Device INT# to GPP Interrupt
Input

INTA# INTB# INTC# INTD#

16 17 18 19

The GT-64260B has one dedicated processor interrupt output, CPUINT_,
which is connected to the prima ry proce ssor CPU0 INT_L in put. Refe r to

http://www.motorola.com/computer/literature 2-3

Programming Details

2

the GT-64260B System Controller for PowerPC Processors Data Sheet,
listed in Appendix B, Rela ted Documenta tion, for details.

Table 2-2. GT-64260B External GPP Interrupt Ass ignments

GPP
Group GPP #

0 0 Level High COM1 || COM2

1 Level Low Not Used. Pulled High.
2 Level Low Abort Switch
3 Level Low RTC || Thermostat Output
4 Level Low Not Used. Pulled high, tied to GPP27.
5 Level Low Not Used. Pulled high, tied to GPP28.
6 Level Low GT-64260B WDMNI Interrupt. Tied to GPP24.
7 Level Low LXT971A Interrupt (10/100Mbit PHY)

1 8 Level Low PMC 1 Interrupt INT A

9 Level Low PMC 1 Interrupt INT B
10 Level Low PMC 1 Interrupt INT C
11 Level Low PMC 1 Interrupt INT D || IPMC INT
12 Level Low VME Interrupt VLINT0
13 Level Low VME Interrupt VLINT1
14 Level Low VME Interrupt VLINT2

Edge/
Level Polarity Interrupt Source

15 Level Low VME Interrupt VLINT3

2-4 Computer Group Literature Center Web Site

Two-Wire Serial Interface

Table 2-2. G T-64260B External GPP Interrupt Assi gnment s (continued)

GPP
Group GPP #

2 16 Level Low PMC 2 Interrupt INT A

17 Level Low PMC 2 Interrupt INT B
18 Level Low PMC 2 Interrupt INT C
19 Level Low PMC 2 Interrupt INT D
20 Level Low 82544 Interrupt
21 Level Low Not Used. Pulled High.
22 Level Low Not Used. Pulled High.
23 Level Low Not Used. Pulled High.

3 24 Watchdog Timer NMI Output WDNMI# to

25 Watchdog Timer Expired Output WDE#
26 GT-64260B SROM Initialization Active InitAct
27 Level Low Not Used. Pulled high, tied to GPP4.
28 Not Used. Pulled high, tied to GPP5.

Edge/
Level Polarity Interrupt Source

GPP6

2

29 Optional External PPC Bus Arbiter BG1 Enable
30 Unused. Pulled High.
31 Unused. Pulled High.

Two-Wire Serial Interface

A two-wire serial interface for the MVME5500 board is provided by an
I2C compatible serial controller integrated into the GT-64260B system
controller . The I2C ser ial controller p rovides two basic functions. The fi rst
function is to provide GT-64260B register initialization following a reset.
The GT-64260B can be configured (by jumper setting) to automatically
read data out of a serial EEPR OM following a reset and initialize any
number of internal registers. In the second function, the controller is used
by the system software to read the contents of the VPD EEPROM

http://www.motorola.com/computer/literature 2-5

Programming Details

2

contained on the MVME5500 board, along with the SPD EEPROMs, to
further initializ e the memory controller and othe r interfaces. For addition al
details regardi ng the G T -64260B two- wire serial controller op eration, refer
to the GT -64260B Sys tem Contr oller f or PowerPC Pr oces sors Data She et,
listed in Appendix B, Rela ted Documenta tion.

T able 2-3 shows the I2C devices used for the MVME5500 and the assigned

device IDs.

Table 2-3. I2C Bus Device Addressing

Device
Address

Device Function Size

Memory SPD (On-board. Banks A and B.) 256 x 8 000b $A0 1, 2
Memory SPD (On mezzanine. Banks C and D.) 256 x 8 001b $A2 1
IPMC VPD 256 x 8 010b $A4
GT-64260B Fixed Initialization 256 x 8 011b $A6 2

(A2A1A0)

I2C BUS
Address Notes

Configuration VPD 8K x 8 100b $A8 2, 3
User VPD 8K x 8 101b $AA 2, 3
Not Used NA 110b $AC
Not Used NA 111b $AE
DS1621 Temperature Sensor NA 000b $90

Notes 1. Each SPD defines the physical attributes of each bank or

group of banks, that is, if both banks of a group are
populated, they will be the same speed and memory size.

2. This device can be write-protected by either setting the
EEPROM_WP bit of SSR2 or by placing a jumper on the
EEPROM wr ite protect header. The hardware jumper
mechanism always takes precedence over the software
setting. For 8KB sized parts, only the upper 2KB are write­protectable.

3. This is a 2-byte address serial EEPROM (AT24C64).

2-6 Computer Group Literature Center Web Site

GT-64260B Initialization

GT-64260B Initialization

Serial EEPROM devices a re provided to support opt io nal initialization of
the GT-64260B (enabled by an on-board jumper). Using the SROM
initialization method, any of the GT-64260B internal registers or other
system components (that is, devices on the PCI bus) can be initialized.
Initialization takes place by s equentia lly read ing 8-byt e addre ss/data pairs
from the SROM and writing the 32-bit dat a to the decoded 32-bit addre ss
until the da ta pattern matching the last serial data item register is read for
the SROM (default value = 0xffffffff). The on-board reset logic keeps the
processor reset asserted until this initialization process is completed.

GT-64260B GPP Configuration

The G T-64260B contains a 32-bi t GPP. The GPP pins can be configured as
general-purpose I/O pins, as external interrupt inputs, or as specific
control/status pins for one of t he GT-64260B internal devices. After reset,
all GPP pins default to gene ral-purpose inputs. Software must then
configure each of the pins for the desired function. The following table
defines the function assigned to each GPP pin on the MVME5500 board.

Table 2-4. GT-64260B GPP Pin Function Assignments

2

GPP Number Input/Output Function

0 I COM1/COM2 interrupts (ORed)
1 I Not Used. Pulled High.
2 I Abort Interrupt
3 I RTC and Thermostat Interrupts (ORed)
4 O Not Used. Pulled high, tied to GPP27.
5 I Not Used. Pulled high, tied to GPP28.
6 I GT-64260B WDMNI Interrupt. Tied to GPP24.
7 I LXT971A Interrupt (10/100Mbit PHY)
8 I PMC 1 Interrupt INT A

http://www.motorola.com/computer/literature 2-7

Programming Details

2

Table 2-4. GT-64260B GPP Pin Function Assignments (continued)

GPP Number Input/Output Function

9 I PMC 1 Interrupt INT B
10 I PMC 1 Interrupt INT C
11 I PMC 1 Interrupt INT D/IPMC INT
12 I VME Interrupt 0
13 I VME Interrupt 1
14 I VME Interrupt 2
15 I VME Interrupt 3
16 I PMC 2 Interrupt INT A
17 I PMC 2 Interrupt INT B
18 I PMC 2 Interrupt INT C
19 I PMC 2 Interrupt INT D
20 I 82544 Interrupt
21 I Not Used. Pulled High.
22 I Not Used. Pulled High.
23 I Not Used. Pulled High.
24 O Watchdog Timer NMI Output WDNMI# to GPP6
25 O Watchdog Timer Expired Output WDE#
26 O GT-64260B SROM Initialization Active InitAct
27 I Not Used. Pulled high, tied to GPP4.
28 O Not Used. Pulled high, tied to GPP5.
29 O Optional external PPC Bus Arbiter BG1 Enable.
30 I Not Used. Pulled High.
31 I Not Used. Pulled High.

2-8 Computer Group Literature Center Web Site

GT-64260B Reset Configuration

GT-64260B Reset Configuration

The GT-64260B supports two methods of device initialization following
reset:

❏ Pins sampl ed on the deas ser ti on of reset
❏ Partial pin sample on deassertion of reset plus serial ROM

initialization via the I2C bus

The MVME5500 board supports both options listed above. An on-board
jumper setting is used to select the option. If the pin-sample-only method
is selected, then states of the various pins on the device AD bus are
sampled when reset is deasserted to determine the desired operating
modes. Table 2-5 on page 2-10 describes the configuration options.
Combinations of pullups, pulldowns, and jumpers are used to set the
options. Some options are fixed and some are selectable at build time by
installing the proper pullup/pulldown resistor. Finally, some options may
be selected using on-board jumpers.

Using the SROM initialization method, any of the GT-64260B internal
registers or other syste m compon ents ( that is, devi ces on th e PCI bus) can
be initialized. Initialization takes place by sequentially reading 8-byte
address/data pairs from the SROM and writing the 32-bit data to the
decoded 32-bit address until the last serial data item of 0xffffffff is read. If
the SROM initialization option is selected, the following pins are still
sampled to determine certain operating parameters:

2

❏ AD(1) – SROM byte offset width
❏ AD(3:2) – SROM address
❏ AD(4) – CPU endianess

http://www.motorola.com/computer/literature 2-9

Programming Details

2

❏ AD(30:28) – PLL settings
❏ AD(31) – CPU interface voltage

Table 2-5. GT-64260B Power-Up Configuration Settings

Default
Device AD
Bus Signal

AD[0] Jumper x SROM Initialization 0 No SROM

Select
Option

Power-Up

Setting Description State of Bit vs. Function

Initialization

1 SROM Initialization

Enabled

AD[1] Resistor 0 SROM Byte Offset

Width

AD[3:2] Resistors 11 SROM Device

Address
AD[4] Fixed 0 CPU Data Endianess 0 Must be Pulled Down
AD[5] Fixed 1 C PU Interface Clock 1 CPU Interface

AD[6] Jumper x CPU Bus

Configuration

AD[8] Resistor 1 Internal 60x Bus

Arbiter
AD[9] Fixed 0 Multiple GT-64260B

Support
AD[11:10] Fixed 11 Multiple GT-64260B

Address ID
AD[12] Fixed 0 SDRAM UMA 0 Not Suppo r t ed
AD[13] Fixed 0 UMA Device Type 0 UMA Master
AD[15:14] Fixed 10 BootCS* Device

Width

0 Up to 8 Bits

11 1010011 ($A6)

Synchronous with

TClk
0 60x Bus Mode
1 MPX Bus Mode
1 Internal Arbiter

Enabled
0 Not Supported

11 GT Responds to CPU

Address A[5:6] = 11

10 32 Bits

AD[16] Resistor 1 PCI Retry 1 Enable

2-10 Computer Group Literature Center Web Site

GT-64260B Device Controller Bank Assignments

Table 2-5. GT-64260B Power-Up Configuration Settings (continued)

Default
Device AD
Bus Signal

AD[17] Fixed 0 PCI_0 Expansion

AD[18] Fixed 0 PCI_1 Expansion

AD[22:19] Fixed 0000 Reserved 0000 Must be Pulled Down
AD[23] Fixed 1 SDClkIn/

AD[24] Resistor 1 Internal Space Default

AD[27:25] Fixed 000 Reserved 000 Must be Pulled Down
AD[28] Resistor 0 PLL Tune 0 Tuning Option 0
AD[29] Resistor 0 PL L Divider 0 Divider Option 0
AD[30] Resistor 0 PLL Bypass 0 PLL Enabled
AD[31] Fixed 0 CPU Interface Voltage 0 2.5V

Select
Option

Power-Up

Setting Description State of Bit vs. Function

0 Not Supported

ROM

0 Not Supported

ROM

1SDClkIn

SDClkOut Select

1 0xf100.0000

Address

2

GT-64260B Device Controller Bank
Assignments

The MVME5500 board uses three of the GT-64260B device controller
banks for interfacing to various devices. The following tables define the
device bank assignments and the programmable device bank timing
parameters required for each of the banks used. Note that all device bank

http://www.motorola.com/computer/literature 2-11

Programming Details

2

timing parameters, except BAdrSkew, have an exte nsion bit th at forms the
most significant bit of the timing parameter.

Device Bank Data Width Function Note

Table 2-6. Device Bank Assignments

Device
Bank

Flash 0
(150 ns)

0 32 bit Flash 0 Soldered Flash or Flash

1 Soldered Flash
1 8 bit I/O Devices
2NANot used
3NANot used
Boot 32 bit Flash 1 Soldered Flash or Flash

0 Soldered Flash

1

1

Note 1. Determined by Flash boot bank select jumper.

Table 2-7. Device Bank Timing Parameters

Device Bank Timing Parameter Min. Value

GT-64260B
Tclk Clock
Freq.

100 MHz1 - 10 - 30 - 60 - 30 - 70 - 40
133 MHz1 - 60 - 40 - 80 - 31 - 20 - 50

Acc2FirstExt - Acc2First

Acc2NextExt - Acc2Next

TurnOff Ext - TurnOff

ALE2WrExt - ALE2Wr

WrLowExt - WrLow

WrHighExt - WrHigh

BAdrSkew

Flash 0
(120 ns)

2-12 Computer Group Literature Center Web Site

100 MHz0 - e0 - 30 - 60 - 30 - 70 - 40
133 MHz 1 - 2 0 - 4 0 - 8 0 - 3 1 - 2 0 - 5 0

System Clock Generators

Device
Bank

Flash 0
(100 ns)

Device
Bank1
I/O

Flash 1
(90 ns)

Table 2-7. Device Bank Timing Parameters (continued)

Device Bank Timing Parameter Min. Value

GT-64260B
Tclk Clock
Freq.

100 MHz0 - c0 - 30 - 60 - 30 - 70 - 40
133 MHz 1 - 0 0 - 4 0 - 8 0 - 3 1 - 2 0 - 5 0
100 MHz 0 - c 0 - a 0 - 5 0 - 3 1 - 0 0 - 4 0
133 MHz 1 - 0 0 - e 0 - 7 0 - 3 1 - 3 0 - 6 0

100 MHz0 - b0 - 90 - 30 - 30 - 40 - 30
133 MHz 0 - e 0 - c 0 - 4 0 - 3 0 - 5 0 - 4 0

Note Flash 0 contains 100 ns, 120 ns, or 150 ns StrataFlash devices.

Acc2FirstExt - Acc2First

Acc2NextExt - Acc2Next

TurnOff Ext - TurnOff

ALE2WrExt - ALE2Wr

Device speed can be determined from VPD.

WrLowExt - WrLow

WrHighExt - WrHigh

2

BAdrSkew

System Clock Generators

The system clock generator functions generate and distribute all of the
clocks required for system operation. The clocks for the processor,
memory, and PCI devices consist of a clock tree derived from a 66 MHz
oscillator and a se ries o f PLL clock g enerat ors. The clock tree i s desi gned
in such a manner as to maintain the strict edge-to-edge jitter and low clock­to-clock skew required by these devices. Additional clocks required by
individual devices are generated near the devices using individual
oscillators.

http://www.motorola.com/computer/literature 2-13

Programming Details

2

VPD and User Configuration EEPROMs

The MVME5500 board contains an Atmel AT24C64 vital product data
(VPD) EEPROM containing configuration information specific to the
board. Typical information that may be present in the VPD is:
manufacturer, board revision, build version, date of assembly, memory
present, options present, L3 cache information, etc. A second AT24C64
device is available for user data storage.

Temperature Sen so r

The MVME5500 board contains a Maxim DS1621 digital temperature
sensor with an I2C s erial bus int erface. This devi ce may be used t o provide
a measure of the ambient temperature of the board.

Flash Memory

The MVME5500 contains two banks of Flash memory accessed via the
device controller contained wit hin the GT - 64260B. Flash 1 co nsists of t wo
soldered 32Mb devices (E28F320J3A) to give a minimum of 8MB Flash
memory. Flash 0 consists of two Intel StrataFlash 3.3 volt devices,
configured to operate in 16-b it mode, to form a 32-bit Flash port . This bank
contains 64Mb devices (E28F128J3A) for 32MB of Flash.

There is a Flash boot bank select jumper on board, which selects either
Flash 0 or Flash 1 as the boot bank. No jumper or a jumper installed
between pins 1 and 2 selects Flash 0 as the boot bank. A jumper installed
between pins 2 and 3 selects Flash 1 as the boot bank.

PCI Arbitration Assignments

PCI arbitration for PCI Bus 0.0 and PCI Bus 1.0 is handled using logic
implemente d in PLDs. These arbiters use a rotating priority scheme for
fairness and bus parking will always be on the GT-64260B. There are no
software programmable modes to these arbiters.

2-14 Computer Group Literature Center Web Site

Other Software Considerations

PCI arbitration for PCI Bus 0.1 is provided by the HiNT PCI 6154
secondary side arbiter.

Table 2-8. PCI Arbiter Assignments

PCI Bus
Number

0.0 0 G T-64260B Host

0.1 0 PCI/PMC Expansion

1.0 0 G T-64260B Host

REQ/GNT
Pair PCI Device

1PMC Req 1
2PMC Req 2
3 PCI-to-PCI Bridge

(HiNT PCI 6154)

4Not Used

1 VME Controller

1PMC Req 1
2PMC Req 2
3 82544

2

4Not Used

Other Software Considerations

The following subsections discuss software aspects of the CPU bus,
processor, and cache that can have an influence on the MVME5500.

CPU Bus Mode

The CPU bus operating mode (60x or MPX) is deter mined by rea din g the
BMODE bits (bits 16-17) in the processor’s Memory Subsystem Control
Register (MSSCR0). The power-up state of the BMODE(0:1) pins is
captured in these register bits. Refer to the MPC7450 RISC

http://www.motorola.com/computer/literature 2-15

Programming Details

2

Microprocessor User’s Manual, listed in Appendix B, Related

Documentation, for details.

Processor Type Identification

Software can det ermine the p rocessor vers ion throu gh the vers ion regist er .
The most significant 16 bits (0:15) of the MPC7455 processor version
register reads as 0x8001.

Processor PLL Configuration

The processor internal clock frequency (core frequency) is a multiple of
the system bus frequency. The processor has five configuration pins,
PLL_EXT and PLL_CFG[0:3], for hardware strapping of the processor
core frequency (between 2x and 16x of the system bus frequency).

L1, L2, L3 Cache

The processors support on-chip L1 and L2 caches and external L3 cache.
L3 cache supports 1 or 2MB in a variety of SRAM device types. Each
processor L3 interface on the MVME5500 consists of two 8Mb devices
(K7D803671B-HC30) providing a total of 2MB of L3 cache. Data parity
checking should be enabled. The follow ing processo r L3CR register
settings assume a processor speed of 933 MHz and L3 clock speed of
233 MHz.

Table 2-9. Processor L3CR Register Assignments

Apollo L3CR
Register Description Value

L3SIZ L3 Size, 2 MB 1
L3RT L3 SRAM Type, DDR SRAM 00

2-16 Computer Group Literature Center Web Site

L1, L2, L3 Cache

Table 2-9. Processor L3CR Register Assignments

Apollo L3CR
Register Description Value

L3PE L3 Data Parity Checking Enable, ON 1
L3CLK L3 Clock Speed; 233 MHz, Divide b y 4 110
L3CKSP L3 Clock Sample Point, 2 Clocks TBD
L3PSP L3 P-Clock Sample Point, 3 Clocks TBD

2

http://www.motorola.com/computer/literature 2-17

AVital Product Data

This appendix gives a n ov ervie w of the vita l product data (VPD) re quire d
for the MVME5500.

Flash Memory Configuration Data

The Flash memory configuration data packet consists of byte fields that
indicate the size/organization/type of the Flash memory array. Table A-1
and Table A-2 further describe the Flash memor y configura tion VPD data
packet.

Tabl e A-1. Flash 0 Memory Configuration Data

A

Byte
Offset

00 2 FMC_MID Manufacturer ’s Identifier
02 2 FMC_DID Manufacturer’s Device Identifier
04 1 FMC_DDW Device Data Width (16 bits on MVME5500)
05 1 FMC_NOD Number of Devices Present

06 1 FMC_NOC Number of Columns (Interleaves)

07 1 FMC_CW Colu mn Width in Bits (16 on MVME5500)

Field Size
(Bytes) F ield Mnemonic Field Description

(two on MVME5500)

(two on MVME5500)

This will always be a multiple of the device’s
data width.

A-1

A

Vital Product Data

Table A-1. Flash 0 Memory Configuration Data (continued)

Byte
Offset

08 1 FMC_WEDW Write/Erase Data Width (16 on MVME5500)

09 1 FMC_BANK Bank Number of Flash Memory Array: 0 for

0A 1 FMC_SPEED ROM Access Speed in Nanoseconds
0B 1 FMC_SIZE Total Bank Size (Should agree with the

Field Size
(Bytes) F ield Mnemonic Field Description

The Flash memory devices must be
programmed in parallel when the write/erase
data width exceeds the device’s data width.

this bank

physical organization above):
07 = 32M

Table A-2. Flash 1 Memory Configuration Data

Byte
Offset

00 2 FMC_MID Manufacturer’s Identifier

02 2 FMC_DID Manufacturer’s Device Identifier

Field Size
(Bytes) Field Mnemonic Field Description

(FFFF = Undefined/Not-Applicable)

(FFFF = Undefined/Not-Applicable)
04 1 FMC_DDW Device Data Width (16 bits on MVME5500)
05 1 FMC_NOD Number of Devices Present

(two on MVME5500)
06 1 FMC_NOC Number of Columns (Interleaves)

(two on MVME5500)
07 1 FMC_CW Col umn Width in Bits (16 on MVME5500)

This will always be a multiple of the device’s

data width.

A-2 Computer Group Literature Center Web Site

L3 Cache Configuration Data

Table A-2. Flash 1 Memory Configuration Data (continued)

A

Byte
Offset

08 1 FMC_WEDW Write/Erase Data Width (16 on MVME5500)

09 1 FMC_BANK Bank Number of Memory Array: 1 for this

0A 1 FMC_SPEED ROM Access Speed in Nanoseconds
0B 1 FMC_SIZE Total Bank Size (Should agree with the

Field Size
(Bytes) Field Mnemonic Field Description

The two memory devices must be
programmed in parallel when the write/erase
data width exceeds the device’s data width.

bank

physical organization above):
03 = 2M for this bank

L3 Cache Configuration Data

The L3 cache configurati on data packet consists of byt e fields that indica te
the size/or ganization/type of the L3 cache memory array . Table A-3 further
describes the L3 cache memory configuration VPD data packet.

Table A-3. L3 Cache Configuration Data

Byte Offset Field Size (Bytes) Field Description

00 1 Which processor is cache connected to:

01 - 1st Processor

01 1 Cache size:

01 - 2MB

02 1 L3 cache core to cache ratio:

(Backside Configurations - setting depends on pr ocessor core
speed and SRAM capability)
06 - 4:1 (4)

03 1 Cache clock sample point:

02 - 4 clocks

http://www.motorola.com/computer/literature A-3

A

Vital Product Data

Table A-3. L3 Cache Configuration Data (continued)

Byte Offset Field Size (Bytes) Field Description

04 1 Processor clock sample point:

03 - 3 clocks

05 1 Sample point override:

00 - sample point override disabled

06 1 SRAM clock control:

00 - SRAM clock control disabled

07 1 SRAM type:

00 - MSUG2 DDR SRAM

08 1 Data bus error detection type:

01 - parity

09 1 Address bus error detection type:

00 - None

A-4 Computer Group Literature Center Web Site

BRelated Documentation

Motorola Computer Group Documents

The Motorola pub lications listed bel ow are refe renced in t his manual . You
can obtain electr onic copies of Motorola Computer Group p ublications by:

❏ Contacting your local Motorola sales office
❏ Visiting Motorola Computer Group’s World Wide Web literature

site, http://www.motorola.com/computer/literature

Table B-1. Motorola Computer Group Documents

B

Document Title

MVME5500 Single-Board Computer Installation
and Use

MVME761 Transition Module Installation and Use VME761A/IH
MVME712M Transition Module Installation and

Use
MOTLoad Firmware Package User’s Manual MOTLODA/UM
IPMC712/761 I/O Module Installation and Use VIPMCA/IH
PMCspan PMC Adapter Carrier Board Installation

and Use

To obtain the most up-to-date product information in PDF or HTML
format, visit http://www.motorola.com/computer/literature

Motorola Publication
Number

V5500A/IH

VME712MA/IH

PMCSPANA/IH

B-1

Related Documentation

B

Manufacturers’ Documents

For additional information, refer to the following table for manufacturers’
data sheets or user’ s manuals. As an ad ditional help, a sour ce for the list ed
document is provided. Please note that, while these sources have been
verified, the information is subject to change without notice.

Table B-2. Manufacturers’ Documents

Document Title and Source Publication Number

MPC7450 RISC Microprocessor User’s Manual

Literature Distribution Center for Motorola
T e le p hon e: 1-8 00- 441-24 47
FAX: [phone] or [phone]

Web Site: http://e­www.motorola.com/webapp/sps/library/prod_lib.jsp
E-mail: [e-mail]

MPC7450 RISC Microprocessor Hardware Specification

Literature Distribution Center for Motorola
T e le p hon e: 1-8 00- 441-24 47
FAX: [phone] or [phone]

Web Site: http://e­www.motorola.com/webapp/sps/library/prod_lib.jsp
E-mail: [e-mail]

MPC7450UM/D Rev 2

MPC7450EC/D Rev 3

GT-64260B System Controller for PowerPC Processors Data Sheet
Marvell Technologies, Ltd.
Web Site: http://www.marvell.com

Intel 82544EI Gigabit Ethernet Controller with Integrated PHY Data
Sheet

Intel Corporation
Literature Center
19521 E. 32nd Parkway
Aurora CO 80011-8141
Web Site: http://www.intel.com/design/litcentr/index.htm

B-2 Computer Group Literature Center Web Site

MV-S100414-00B

82544.pdf

Manufacturers’ Documents

Table B-2. Manufacturers’ Documents (continued)

Document Title and Source Publication Number

LXT971A 10/100Mbit PHY Datasheet
Intel Corporation

Literature Center
19521 E. 32nd Parkway
Aurora CO 80011-8141
Web Site: http://www.intel.com/design/litcentr/index.htm

3 Volt Synchronous Intel StrataFlash Memory 28F640K3,
28F640K18, 28F128K3, 28F128K18, 28F256K3,

28F256K18 (x16)
Intel Corporation

Literature Center
19521 E. 32nd Parkway
Aurora CO 80011-8141
Web Site: http://www.intel.com/design/litcentr/index.htm

3 Volt Intel StrataFlash Memory
28F128J3A, 28F640J3A, 28F320J3A

Intel Corporation
Literature Center
19521 E. 32nd Parkway
Aurora CO 80011-8141
Web Site: http://www.intel.com/design/litcentr/index.htm

24941402.pdf

290737-003

290667-005

B

PCI 6154 (HB2) PCI-to-PCI Bridge Data Book
PLX Technology, Inc.

870 Maude Avenue
Sunnyvale, California 94085
Web Site: http://www.hintcorp.com/products/hint/default.asp

http://www.motorola.com/computer/literature B-3

6154_DataBook_v2.0.p
df

Related Documentation

B

Table B-2. Manufacturers’ Documents (continued)

Document Title and Source Publication Number

TL16C550C Universal Asynchronous Receiver/Transmitter
T e x a s Ins truments

P. O. Box 655303
Dallas, Texas 75265
Web Site: http://www.ti.com

3.3V-5V 256Kbit (32Kx8) Timekeeper SRAM
ST Microelectronics

1000 East Bell Road
Phoenix, AZ 85022
Web Site: http://eu.st.com/stonline/index.shtml

2-Wire Serial CMOS EEPROM
Atmel Corporation

San Jose, CA
Web Site: http://www.atmel.com/atmel/support/

Universe II User Manual
Tundra Semiconductor Corporation

Web Site:

http://www.tundra.com/page.cfm?tree_id=100008#Universe II
(CA91C042)

SLLS177E

M48T37V

AT24C02
AT24C04
AT24C64
AT24C256
AT24C512

8091142_MD300_01.p
df

B-4 Computer Group Literature Center Web Site

Related Specifications

Related Specifications

For additional information, refer to the following table for related
specifications. For your convenience, a source for the listed document is
also provided. It is important to not e that in many case s, the infor mation is
preliminary and the revis ion levels of the document s are subject to cha nge
without notice.

Table B-3. Related Specifications

Document Title and Source Publication Number
VITA http://www.vita.com/

VME64 Specification ANSI/VITA 1-1994
VME64 Extensions ANSI/VITA 1.1-1997
2eSST Source Synchronous Transfer VITA 1.5-199x

PCI Special Interest Group (PCI SIG) http://www.pcisig.com/

Peripheral Component Interconnect (PCI) Local Bus Specification,
Revision 2.0, 2.1, 2.2

PCI Local Bus
Specification

B

http://www.motorola.com/computer/literature B-5

Index

B

block diagram 1-4

C

cache 2-16
comments, sending xiv
config switch register 1-17
conventions used in the manual xiv
core frequency 2-16
CPU bus mode 2-15

D

default PCI memory map 1-7
default processor memory map 1-5
documentation, related B-1

F

features 1-2
Flash memory 2-14

config data A-1

G

geographical address register 1-18
GT-64260B system controller 2-1

device bank timing 2-12
device controller banks 2-11
GPP config 2-7
GPP interrupts 2-4
I2C 2-5
initialization 2-7
interrupt controller 2-3
power-up c onfig 2-10
reset config 2-9

I

I2C 2-5
IDSEL mapping 2-2

interrupt controller 2-3

L

L1, L2, L3 cache 2-16
L3 cache config data A-3

M

manual conventions xiv
manufactur ers’ documents B-2
memory maps

default PCI 1-7
default processor 1-5
MOTLoad’s PCI 1-9
MOTLoad’s processor 1-6

system I/O 1-10
MOTLoad’s PCI memory map 1-9
MOTLoad’s processor memory map 1-6

N

NVRAM 1-20

P

PCI arbiter 2-15
PLL clock generators 2-13
presence detect register 1-16
processor bus mode 2-15
processor version register 2-16

R

real-time clock 1-20
registers

config switch register 1-17

geographical address register 1-18

presence detect register 1-16

system status register 1 1-11

system status register 2 1-13

system status register 3 1-15

IN-1

time base enable register 1-18

related documentation B-1

S

suggestions, submitting xiv
system clock gene rators 2-13
system I/O memory ma p 1-10
system status register 1 1-11
system status register 2 1-13
system status register 3 1-15

T

temp sensor 2-14

time base enable register 1-18
two-wire serial interface 2-5
typeface, meaning of xiv

U

UART 1-20

V

vital product data (VPD) 2-14, A-1

Flash memory A-1
L3 cache A-3

N
D
E
X

I

IN-2 Computer Group Literature Center Web Site