Motorola MVME3600, MVME4600 Programmer's Reference Manual

MVME3600/4600 Series

VME Processor Modules

Programmer’s Reference

Guide

V36V46A/PG3

August 2001 Edition

© Copyright 1998, 2001 Motorola, Inc.

All rights reserved.

Printed in the United States of America.

®

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PowerPC

and the Motorola symbol are registered trademarks of Motorola, Inc.

™

, VMEmodule™, and VMEsystem™ are tradem arks of Motoro la, Inc.

®

is a registered trademark and PowerPC 604™ is a trademark of International
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is a registered trademark of International Business Machines Corporation.

AIX

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All other products ment io ned i n this document are tradema rks or registered tradema rk s of

their respective holders.

Safety Summary

The following general safety precautions must be observed during all phases of operation, service, and repair of this
equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result
in personal injury or damage to the equipment.

The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user
of the product, shoul d foll ow these warni ngs and al l other sa fety pr ecauti ons nece ssary fo r the safe ope ration of the
equipment in your operating environment.

Ground the Instrument.

To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. If the
equipment is su pplied wi th a three-c onductor A C power ca ble, the po wer cable m ust be plug ged into an a pproved
three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground
(safety ground) at the power outlet. The power jack and mating plug of the power cable meet International
Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes.

Do Not Operate in an Explosive Atmosphere.

Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes.
Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage.

Keep Away From Live Circuits Inside the Equipment.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other
qualified service personnel may remove equipment covers for internal subassembly or component replacement or any
internal adjust ment. Service pe rsonnel should n ot replace compon ents with power c able connected. Under certain
conditions, dangero us voltages may exist even with the power cable remo ved. T o avoid inju ries, such pers onnel should
always disconnect power and discharge circuits before touching components.

Use Caution When Exposing or Handling a CRT.

Breakage of a Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent
CRT implosion, do not handl e the CRT and avoid rough handling o r jarring of t he equipment . Handling o f a CRT
should be done only by qualified service personnel using approved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.

Do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local
Motorola representative for service and repair to ensure that all safety features are maintained.

Observe Warnings in Manual.

W arn ings , such as th e exa mple be low, prece de pote nt ially danger ous p rocedu res th rough out th is manu al. In str uction s
contained in the warnings m ust be follow ed. You should also employ all ot her safety precautions w hich you dee m
necessary for the operation of the equi pment in your operating environment.

To prevent serious injury or death from dangerous voltages, use extreme
caution when handling, testing, and adjusting this equipment and its

Warning

components.

Flammability

All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating
of 94V-0 by UL-recognized manufacturers.

EMI Caution

This equipment ge ner ates, uses a nd can radi ate el ectro magne tic energy . It

!

Caution

This product contains a lithium battery to power the clock and calendar circuitry.

!

Caution

may cause or be susceptible to electromagnetic interference (EMI) if not
installed and used with adequate EMI protection.

Lithium Battery Caution

Danger of explosion if battery is re placed incorrect ly. Replace battery only
with the same or equivalent type recommended by the equipment
manufacturer. Dispose of used batteries according to the manufacturer’s
instructions.

!

Attention

!

Vorsicht

Il y a danger d’explosion s’il y a remplacement incorrect de la batterie.
Remplacer uniquement avec une batterie du même type ou d’un type
équivalent recommandé par le constructeur. Mettre au rebut les batteries
usagées conformément aux instructions du fabricant.

Explosionsgefahr bei unsachgemäßem Austausch de r Ba tt er ie . Ersatz nur
durch denselben ode r einen vom Herstel ler empfohle nen Typ. Entsorgu ng
gebrauchter Batterien nach Angaben des Herstellers.

CE Notice (European Community)

Motorola Compute r Group pro ducts wi th the CE mar king co mply with the EMC Dir ective
(89/336/EEC). Compliance with this directive implies conformity to the following
European Norms:

EN55022 “Limits and Methods of Meas urement of Radio Int erferen ce Chara cteri stic s
of Information Technology Equipment”; this product tested to Equipment Class B

EN55024 “Information te chnology equipment—Immunity char acteristics—Limits and
methods of measurement”

Board products are tested in a representative system to show compliance with the above
mentioned requirements. A proper installation in a CE-marked system will maintain the
required EMC performance.

In accordance with European Community directives, a “Declaration of Conformity” has
been made and is available on request. Please contact your sales representative.

Notice

While reasonable efforts have been made to assure the accuracy of this document,
Motorola, Inc. a ssumes n o lia bility r esulti ng from any omissio ns in this docu ment, or from
the use of the information obtained therein. Motorola reserves the right to revise this
document and to ma ke c hanges from time to ti me in the content he re of wi thout obligation
of Motorola to notify any person of such revision or changes.

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Limited and Restricted Rights Legend

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Government, the following notice shall apply unless otherwise agreed to in writing by
Motorola, Inc.

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in
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1995) and of the Rights in Noncommerc ial Computer Software and Docume ntation c lause
at DFARS 252.227-7014 (Jun. 1995).

Motorola, Inc.
Computer Group
2900 South Diablo Way
Tempe, Arizona 85282

Contents

About This Manual

Summary of Changes..................................................................................................xx

Overview of Contents.................................................................................................xx

Comments and Suggestions.......................................................................................xxi

Conventions Used in This Manual.............................................................................xxi

CHAPTER 1 Board Description and Memory Maps

Introduction ................................................................................................................1-1

Overview.............................................................................................................1-1

Summary of Features..........................................................................................1-2

Block Diagrams..................................................................................................1-3

Functional Description ...............................................................................................1-7

Overview.............................................................................................................1-7

Programming Model..................................................................................................1-8

Memory Maps.....................................................................................................1-8

Processor Memory Maps................................................. ...... ..... .................1-8

PCI Memory Maps....................................................................................1-14

VMEbus Mapping ................................................ ..... ................................1-20

Falcon-Controlled System Registers ................................................................1-25

System Configuration Register (SYSCR).................................................1-26

Memory Configuration Register (MEMCR).............................................1-27

System External Cache Control Register (SXCCR)..................................1-29

CPU Control Register................................................................................1-31

ISA Local Resource Bus..........................................................................................1-31

W83C553 PIB Registers...................................................................................1-31

PC87308VUL Super I/O (ISASIO) Strapping..................................................1-32

NVRAM/RTC & Watchdog Timer Registers...................................................1-32

Module Configuration and Status Registers.....................................................1-33

CPU Configuration Register......................................................................1-34

Base Module Feature Register...................................................................1-34

Base Module Status Register (BMSR)......................................................1-35

Seven-Segment Display Register .......................................... ....................1-36

VME Registers..................................................................................................1-37

LM/SIG Control Register..........................................................................1-38

LM/SIG Status Register.............................................................................1-39

vii

Location Monitor Upper Base Address Register ......................................1-40

Location Monitor Lower Base Address Register......................................1-40

Semaphore Register 1 ............................. ..... ...... .................................. .....1-41

Semaphore Register 2 ............................. ..... ...... .................................. .....1-41

VME Geographical Address Register (VGAR) ........................................1-42

Z85230 ESCC and Z8536 CIO Registers and Port Pins..................................1-43

Z8536/Z85230 Registers........................................................... ..... ...... .....1-43

Z8536 CIO Port Pins.................................................................................1-44

ISA DMA Channels .........................................................................................1-46

CHAPTER 2 Raven PCI Host Bridge & Multi-Processor

Interrupt Controller Chip

Introduction ...............................................................................................................2-1

Summary of Features..........................................................................................2-1

Block Diagram ...................................................................................................2-2

Functional Description ..............................................................................................2-4

MPC Bus Interface.............................................................................................2 -4

MPC Address Mapping...............................................................................2-4

MPC Slave ..................................................................................................2-6

MPC Write Posting .....................................................................................2-8

MPC Master ................................................................................................2-8

MPC Arbiter..............................................................................................2-10

MPC Bus Timer ........................................................................................2-10

PCI Interface.....................................................................................................2-10

PCI Address Mapping...............................................................................2-11

PCI Slave...................................................................................................2-14

PCI Write Posting .....................................................................................2-17

PCI Master ................................................................................................2-17

Generating PCI Cycles..............................................................................2-20

Endian Conversion...........................................................................................2-25

When MPC Devices are Big-Endian.........................................................2-25

When MPC Devices are Little-Endian......................................................2-26

Raven Registers.................................................. ...... .................................2-27

Error Handling................................................ ..... ...... .................................. .....2-28

Transaction Ordering........................................................................................2-29

Registers ..................................................................................................................2-30

MPC Registers..................................................................................................2-30

Vendor ID/Device ID Registers................................................................2-32

Revision ID Register.................................................................................2-33

General Control-Status/Feature Registers.................................................2-33

MPC Arbiter Control Register..................................................................2-35

viii

Prescaler Adjust Register...........................................................................2-36

MPC Error Enable Register.......................................................................2-36

MPC Error Status Register........................................................................2-39

MPC Error Address Register.....................................................................2-41

MPC Error Attribute Register - MERAT..................................................2-41

PCI Interrupt Acknowledge Register ........................................................2-43

MPC Slave Address (0,1 and 2) Registers................................................2-43

MPC Slave Address (3) Register...............................................................2-44

MPC Slave Offset/Attribute (0,1 and 2) Registers....................................2-45

MPC Slave Offset/Attribute (3) Registers.................................................2-46

General Purpose Registers.........................................................................2-47

PCI Registers....................................................................................................2-47

Vendor ID/ Device ID Registers ...............................................................2-49

PCI Command/ Status Registers................................................................2-50

Revision ID/ Class Code Registers............................................................2-52

I/O Base Register.......................................................................................2-52

Memory Base Register ......................................... ..... ................................2-53

PCI Slave Address (0,1,2 and 3) Registers................................................2-54

PCI Slave Attribute/ Offset (0,1,2 and 3) Registers..................................2-55

CONFIG_ADDRESS Register..................................................................2-56

CONFIG_DATA Register.........................................................................2-58

Raven Interrupt Controller Implementation.............................................................2-59

Introduction.......................................................................................................2-59

The Raven Interrupt Controller (RavenMPIC) Features...........................2-59

Architecture...............................................................................................2-59

CSR’s Readability .....................................................................................2-60

Interrupt Source Priority............................................................................2-60

Processor’s Current Task Priority..............................................................2-60

Nesting of Interrupt Events........................................................................2-60

Spurious Vector Generation ......................................................................2-61

Interprocessor Interrupts (IPI)...................................................................2-61

8259 Compatibility....................................................................................2-61

Raven-Detected Errors ..............................................................................2-62

Timers........................................................................................................2-62

Interrupt Delivery Modes ..........................................................................2-62

Block Diagram Description..............................................................................2-64

Program Visible Registers......................................... ...... ...... ....................2-65

Interrupt Pending Register (IPR)...............................................................2-65

Interrupt Selector (IS)................................................................................2-65

Interrupt Request Register (IRR)...............................................................2-66

In-Service Register (ISR)..........................................................................2-66

Interrupt Router.........................................................................................2-66

ix

MPIC Registers ................................................................................................2-68

RavenMPIC Registers...............................................................................2-68

Feature Reporting Register ................................ .................................. .....2-72

Global Configuration Register..................................................................2-73

Vendor Identification Register................................. ..... ...... ......................2-74

Processor Init Register ........................................................ ......................2-74

IPI Vector/Priority Registers........................ .............................................2-75

Spurious Vector Register..........................................................................2-76

Timer Frequency Register.........................................................................2-76

Timer Current Count Registers.................................................................2-77

Timer Basecount Registers .......................................................................2-77

Timer Vector/Priority Registers................................................................2-78

Timer Destination Registers......................................................................2-79

External Source Vector/Priority Registers................................................2-79

External Source Destination Registers......................................................2-81

Raven-Detected Errors Vector/Priority Register ......................................2-81

Raven-Detected Errors Destination Register............................................2-82

Interprocessor Interrupt Dispatch Registers..............................................2-83

Interrupt Task Priority Registers...............................................................2-83

Interrupt Acknowledge Registers..............................................................2-84

End-of-Interrupt Registers ........................................................................2-85

Programming Notes..........................................................................................2-85

External Interrupt Service.........................................................................2-85

Reset State.................................................................................................2-86

Operation..........................................................................................................2-87

Interprocessor Interrupts...........................................................................2-87

Dynamically Changing I/O Interrupt Configuration................................. 2-87

EOI Register............................................................. ..... ...... ......................2-88

Interrupt Acknowledge Register...............................................................2-88

8259 Mode ................................................................................................2-88

Current Task Priority Level ......................................................................2-88

Architectural Notes...........................................................................................2-89

CHAPTER 3 Falcon ECC Memory Controller Chipset

Introduction ...............................................................................................................3-1

Summary of Features..........................................................................................3-1

Block Diagrams..................................................................................................3-2

Functional Description ..............................................................................................3-6

Performance........................................................................................................3-6

Four-beat Reads/Writes............................................ ..... ...... ........................3-6

Single-beat Reads/Writes............................................................................3-7

x

DRAM Speeds.......................................... .................................. ...... ...... .....3-7

ROM/Flash Speeds....................................................................................3-11

PowerPC 60x Bus Interface..............................................................................3-12

Responding to Address Transfers..............................................................3-12

Completing Data Transfers........................................................................3-12

Cache Coherency.......................................................................................3-12

Cache Coherency Restrictions...................................................................3-13

L2 Cache Support......................................................................................3-13

ECC...................................................................................................................3-13

Cycle Types...............................................................................................3-13

Error Reporting................................................................................. ...... ...3-13

Error Logging................................ .................................. ...... ..... ...............3-15

DRAM Test er....................... ...... ..... .................................. ...... ...... ....................3-15

ROM/Flash Interface ........................................................................................3-15

Refresh/Scrub....................................................................................................3-19

Blocks A and/or B Present, Blocks C and D Not Present .........................3-19

Blocks A and/or B Present, Blocks C and/or D Present............................3-20

DRAM Arbitration................................................. ...... ..... ................................3-21

Chip Defaults....................................................................................................3-21

External Register Set ........................................................................................3-21

CSR Accesses...................................................................................................3-22

Programming Model................................................................................................3-22

CSR Architecture..............................................................................................3-22

Register Summary.............................................................................................3-28

Detailed Register Bit Descriptions ...................................................................3-31

Vendor/Device Register ............................................................................3-32

Revision ID/ General Control Register .....................................................3-32

DRAM Attributes Register................................... ..... ...... ..........................3-34

DRAM Base Register.......................... ..... .................................. ...... ...... ...3-36

CLK Frequency Register...........................................................................3-37

ECC Control Register ................................................................................3-38

Error Logger Register............................... ...... ...... .................................. ...3-42

Error_Address Register.............................................................................3-44

Scrub/Refresh Register..............................................................................3-45

Refresh/Scrub Address Register................................................................3-46

ROM A Base/Size Register.......................................................................3-47

ROM B Base/Size Register .......................................................................3-50

DRAM Tester Control Registers and Test SRAM....................................3-52

32-Bit Counter...........................................................................................3-52

Test SRAM................................................................................................3-52

Power-Up Reset Status Register 1.............................................................3-53

Power-Up Reset Status Register 2.............................................................3-53

xi

External Register Set.................................................................................3-54

Software Considerations..........................................................................................3-55

Parity Checking on the PowerPC Bus..............................................................3-55

Programming ROM/Flash Devices..................................................................3-55

Writing to the Control Registers.......................................................................3-55

Sizing DRAM...................................................................................................3-56

ECC Codes ..............................................................................................................3-59

Data Paths................................................................................................................3-62

CHAPTER 4 Universe (VMEbus to PCI) Chip

General Information ..................................................................................................4-1

Introduction........................................................................................................4-1

Product Overview – Features.............................................................................4-1

Functional Description ..............................................................................................4-2

Architectural Overview......................................................................................4-2

VMEbus Interface....................... .................................. ...... ...... ..................4-4

PCI Bus Interface........................................................................................4-5

Interrupter and Interrupt Handler................................................................4-6

DMA Controller..........................................................................................4-7

Registers – Universe Control and Status Registers (UCSR).....................................4-7

Universe Register Map.......................................................................................4-8

Universe Chip Problems after a PCI Reset..............................................................4-13

Problem Description.........................................................................................4-13

Examples.......................................................................................................... 4-15

Example 1: MVME2600 Series Board Exhibits Problem.........................4-15

Example 2: MVME3600 Series Board Acts Differently ..........................4-17

Example 3: Universe Chip is Checked at Tundra.....................................4-19

CHAPTER 5 Programming Details

Introduction ...............................................................................................................5-1

PCI Arbitration..........................................................................................................5-1

Interrupt Handling .....................................................................................................5-2

RavenMPIC........................................................................................................5-3

8259 Interrupts ...................................................................................................5-4

ISA DMA Channels...................................................................................................5-7

Exceptions .................................................................................................................5-8

Sources of Reset.................................................................................................5-8

Soft Reset ................................ ...... .................................................................... .5-9

Universe Chip Problems after a PCI Reset ........................................................5-9

xii

Error Notification and Handling.......................................................................5-10

Endian Issues ...........................................................................................................5-11

Processor/Memory Domain.................................................... ...... ..... ...... ...... ...5-14

Raven’s Involvement........................................................................................5-14

PCI Domain ......................................................................................................5-14

PCI-SCSI...................................................................................................5-14

PCI-Ethernet..............................................................................................5-15

PCI-Graphics.............................................................................................5-15

Universe’s Involvement....................................................................................5-15

VMEbus Domain.............................................................. ...... ...... ..... ...... .........5-15

ROM/Flash Initialization .........................................................................................5-16

APPENDIX A Related Documentation

Motorola Computer Group Documents....................................................................A-1

Manufacturers’ Documents.......................................................................................A-2

Related Specifications...............................................................................................A-4

xiii

List of Figures

Figure 1-1. MVME3600 Series System Block Diagram ...........................................1-5

Figure 1-2. MVME4600 Series System Block Diagram ...........................................1-6

Figure 1-3. VMEbus Master Mapping.....................................................................1-21

Figure 1-4. VMEbus Slave Mapping.......................................................................1-23

Figure 2-1. Raven Block Diagram.............................................................................2-3

Figure 2-2. MPC to PCI Address Decoding..............................................................2-5

Figure 2-3. MPC to PCI Address Translation............................................................2-6

Figure 2-4. PCI to MPC Address Decoding............................................................2-12

Figure 2-5. PCI to MPC Address Translation..........................................................2-13

Figure 2-6. PCI Spread I/O Address Translation.....................................................2-22

Figure 2-7. Big to Little-Endian Data Swap............................................................2-26

Figure 2-8. RavenMPIC Block Diagram.................................................................2-64

Figure 3-1. Falcon Pair Used with DRAM in a System ............................................3-3

Figure 3-2. Falcon Internal Data Paths (Simplified)..................................................3-4

Figure 3-3. Overall DRAM Connections...................................................................3-5

Figure 3-4. Data Path for Reads from the Falcon Internal CSRs.............................3-23

Figure 3-5. Data Path for Writes to the Falcon Internal CSRs.................................3-24

Figure 3-6. Memory Map for Byte Reads to the CSR.............................................3-25

Figure 3-7. Memory Map for Byte Writes to the Internal Register Set

and Test SRAM........................................................................................................3-26

Figure 3-8. Memory Map for 4-Byte Reads to the CSR..........................................3-27

Figure 3-9. Memory Map for 4-Byte Writes to the Internal Register Set

and Test SRAM........................................................................................................3-27

Figure 3-10. PowerPC Data to DRAM Data Correspondence.................................3-63

Figure 4-1. Architectural Diagram for the Universe..................................................4-3

Figure 4-2. UCSR Access Mechanisms.....................................................................4-8

Figure 5-1. MVME3600/4600 Series Interrupt Architecture.....................................5-2

Figure 5-2. PIB Interrupt Handler Block Diagram....................................................5-5

Figure 5-3. Big-Endian Mode..................................................................................5-12

Figure 5-4. Little-Endian Mode...............................................................................5-13

xv

List of T ables

Table 1-1. MVME3600/4600 Series Features Summary...........................................1-2

T ab le 1-2. Default Processor Memory Map...............................................................1-9

T ab le 1-3. CHRP Memory Map Example................................ ...... ...... ....................1-10

Table 1-4. Raven MPC Register Values for CHRP Memory Map...........................1-11

Table 1-5. PREP Memory Map Example.................................................................1-12

Table 1-6. Raven MPC Register Values for PREP Memory Map ...........................1-13

Table 1-7. PCI CHRP Memory Map........................................................................1-14

Table 1-8. Raven PCI Register Values for CHRP Memory Map.............................1-16

Table 1-9. Universe PCI Register Values for CHRP Memory Map.........................1-16

Table 1-10. PCI PREP Memory Map.......................................................................1-17

Table 1-11. Raven PCI Register Values for PREP Memory Map............................1-19

Table 1-12. Universe PCI Register Values for PREP Memory Map........................1-19

Table 1-13. Universe PCI Register Values for VMEbus Slave Map Example ........1-24

Table 1-14. VMEbus Slave Map Example...............................................................1-25

Table 1-15. System Register Summary....................................................................1-25

Table 1-16. Strap Pins Configuration for the PC87308VUL...................................1-32

Table 1-17. MK48T59/559 Access Registers ..........................................................1-33

Table 1-18. Module Configuration and Status Registers.........................................1-33

Table 1-19. VME Registers......................................................................................1-37

Table 1-20. Z8536/Z85230 Access Registers..........................................................1-43

Table 1-21. Z8536 CIO Port Pins Assignment ........................................................1-44

Table 1-22. Interpretation of MID3-MID0..............................................................1-45

Table 1-23. PIB DMA Channel Assignments..........................................................1-47

Table 2-1. MPC Slave Response Command Types....................................................2-7

Table 2-2. MPC Transfer Types.................................................................................2-9

T ab le 2-3. PCI Slave Response Command Types................................................. ...2-15

Table 2-4. PCI Master Command Codes .................................................................2-18

Table 2-5. Address Modification for Little-Endian Transfers .................................2-27

T ab le 2-6. Raven MPC Register Map......................................................................2-30

Table 2-7. Raven PCI Configuration Register Map.................................................2-48

Table 2-8. Raven PCI I/O Register Map ..................................................................2-49

T ab le 2-9. RavenMPIC Register Map...................................... ...... ..........................2-68

Table 3-1. PowerPC 60x Bus to DRAM Access Timing when Configured

for 70ns Page Devices................................................................................................3-8

xvii

Table 3-2. PowerPC 60x Bus to DRAM Access Timing when Configured

for 60ns Page Devices...............................................................................................3-9

Table 3-3. PowerPC 60x Bus to DRAM Access Timing when Configured

for 50ns Hyper Devices...........................................................................................3-10

Table 3-4. PowerPC 60x Bus to ROM/Flash Access Timing when Configured

for 64 bits (32 Bits per Falcon)................................................................................3-11

Table 3-5. PowerPC 60x Bus to ROM/Flash Access Timing when Configured

for 16 Bits (8 Bits per Falcon).................................................................................3-11

T ab le 3-6. Error Reporting.................................................................................. .....3-14

Table 3-7. PowerPC 60x to ROM/ Flash Address Mapping when ROM/Flas h

is 16 Bits Wide (8 Bits per Falcon) .........................................................................3-17

Table 3-8. PowerPC 60x to ROM/ Flash Address Mapping when ROM/Flas h

is 64 Bits Wide (32 Bits per Falcon) .......................................................................3-18

T ab le 3-9. Register Summary............................................................................. .....3-29

Table 3-10. ram spd1,ram spd0 and DRAM Type ...................................................3-33

Table 3-11. Block_A/B/C/D Configurations...........................................................3-35

Table 3-12. rtest encodings......................................................................................3-45

Table 3-13. ROM/Flash Block A Size Encoding ....................................................3-48

Table 3-14. rom_a_rv and rom_b_rv encoding.......................................................3-48

Table 3-15. Read/Write to ROM/Flash....................................................................3-49

Table 3-16. ROM/Flash Block B Size Encoding.....................................................3-51

T ab le 3-17. Sizing Addresses.................................................................. ..... ...... .....3-58

Table 3-18. PowerPC 60x Address to DRAM Address Mappings..........................3-59

Table 3-19. Syndrome Codes Ordered by Bit in Error............................................3-60

Table 3-20. Single-Bit Errors Ordered by Syndrome Code.....................................3-61

Table 3-21. PowerPC Data to DRAM Data Mapping.............................................3-64

Table 4-1. Universe Register Map.............................................................................4-9

T ab le 5-1. PCI Arbitration Assignments................................ ..... ..............................5-1

T ab le 5-2. RavenMPIC Interrupt Assignmen ts........................... ...... ...... ..................5-3

Table 5-3. PIB PCI/ISA Interrupt Assignments........................................................5-6

Table 5-4. Reset Sources and Devices Affected........................................................5-8

Table 5-5. Error Notification and Handling.............................................................5-10

Table 5-6. ROM/Flash Bank Default......................................................................5-16

Table A-1. Motorola Computer Group Documents .................................................A-1

Table A-2. Manufacturers’ Documents ...................................................................A-2

Table A-3. Related Specifications ...........................................................................A-4

xviii

About This Manual

This manual provides programming information for the MVME3604 and
MVME4604 VME Processor Modules (VMEmodules), that are based on
the MVME3604-xxxx base board, the PM604-xxxx mezzanine modules,
and the RAM201-xxx mezzanine modules. Extensive programming
information is pr ovided for several Appl ication-Specific I ntegrated Circuit
(ASIC) devices used on the boards. Reference information is included in

Appendix A, Related Documentation for the Large Sc ale Int egr ati on ( LSI)

devices used on the board s a nd sour ces fo r addi tional i nformati on are list ed.
As of the publication date , the information presented in t his manual applies

to the following MVME3600/4600 series models:

Model Number Description

MVME3604-5342A to
MVME3604-5372

MVME3604-6342 to
MVME3604-6372

MVME3604-5442,
5462, 5472

MVME3604-6442,
6462, 6472

MVME4604-5342A to
MVME4604-5372

MVME4604-6342 to
MVME4604-6372A

MVME4604-5442,
5462, 5472

300 MHz MPC604, 64-512MB ECC DRAM, 9MB Flash, 512KB L2
cache, and IEEE 1101 front panel for use with MVME761

300 MHz MPC604, 64-512MB ECC DRAM, 9MB Flash, 512KB L2
cache, and Scanbe front panel for use with MVME712M

400 MHz MPC604, 64-512MB ECC DRAM, 9MB Flash, 512KB L2
cache, and IEEE 1101 front panel for use with MVME761

400 MHz MPC604, 64-512MB ECC DRAM, 9MB Flash, 512KB L2
cache, and Scanbe front panel for use with MVME712M

Dual 300 MHz MPC604, 64-512MB ECC DRAM, 9MB Flash,
512KB L2 cache, and IEEE 1101 front panel for use with MVME761

Dual 300 MHz MPC604, 64-512MB ECC DRAM, 9MB Flash,
512KB L2 cache, and Scanbe front panel for use with MVME712M

Dual 400 MHz MPC604, 64-512MB ECC DRAM, 9MB Flash,
512KB L2 cache, and IEEE 1101 front panel for use with MVME761

xix

Summary of Changes

This is the third edition of the Programmer’s Reference Guide. It
supersedes the January 2001 edition and incorporates the following
updates.

Date Description of Change

August 2001 All data referring to the VME CSR Bit Set Register

(VCSR_SET) and VM E CSR Bit Clear Registe r
(VCSR_CLR) has been deleted. These registers of the
Universe II are unavailable for implementation as intended by
the MVME materials and the Universe II User Manual.

January 2001 A warning about DRAM component requirements has been

added to the
sections of Chapter 3.

DRAM Attributes Register and Sizing DRAM

Overview of Contents

Chapter 1, Board Description and Memory Maps, describes the board-

level hardware features of MVME3600/4600 series VME processor
modules. It includes memory maps and a discussion of some general
software considerations such as cache coherency, interrupts, and bus
errors.

xx

Chapter 2, Raven PCI Host Bridge & Multi-Processor Interrupt

Controller Chip

PowerPC to PCI Local Bus Bridge ASIC.

Chapter 3, Falcon ECC Memory Controll er Chipset, pr ovides a functiona l

description and programming model for the Falcon DRAM controller
ASIC.

Chapter 4, Universe ( VMEbus to PCI) Chip, gi ves a genera l descripti on of

the Universe VMEbus interface chip.

Chapter 5, Programming Details , provides programming func tions for the

different ASIC chips applicable to the MVME3600/4600 series.

, provides the architecture and usage of the Raven, a

Appendix A, Related Documentat ion, lists all documentation rel ated to the

MVME3600/4600 series.

Comments and Suggestions

Motorola welcomes and appreciates your comments on its doc umentation.
We want to know what y ou think about our manuals and how we can make
them better. Mail comments to:

Motorola Computer Group
Reader Comments DW164
2900 S. Diablo Way
Tempe, Arizona 85282

You can also submit comments to the following e-mail address:

[e-mail]

In all your corres pondence , plea se li st your name, po siti on, and c ompan y.
Be sure to include the title and par t number of the manual and tell how you
used it. Then tell us your feelings about its strengths and weaknesses and
any recommendations for improvements.

Conventions Used in This Manual

The following typographical conventions are used in this document:
Unless otherwise s pecified, all address references are i n h exadecimal. An

asterisk (*) following the signal name for signals which are level
significant denotes that the signal is true or valid when the signal is low.
An asterisk (*) following the signal name for signals which are edge
significant deno tes that the a ctions init iated by th at signal occu r on high to
low transitio n.

$ dollar specifies a hexadecimal number
& ampersand specifies a decimal number
% percent specifies a binary number

xxi

bold

is used for user inpu t that you t ype just as i t appears ; it is al so used for
commands, options and arguments to commands, and names of
programs, directories and files.

italic

is used for names of variables to which you assign values. Italic is also
used for comments in screen dis plays and examples, and to intr odu ce
new terms.

courier

is used for system output (for example, screen displays, reports),
examples, and system prompts.

<Enter>, <Return> or <CR>

<CR> represents the carriage return or Enter key.

CTRL

represents the Control key. Execute control characters by pr essing the
Ctrl key and the letter simultaneously, for example, Ctrl-d.

In this manual, assertion and negation are used to specify forcing a signal
to a particular stat e. In parti cular, a ssertion and asser t refe r to a signal tha t
is active or true; negation and negate indicate a signal that is inactive or
false. These terms ar e used independently of the vo ltage level (high or l ow)
that they represent.

xxii

Data and address sizes are defined as follows:

❏ A byte i s eight bits, numb ered 0 through 7, wit h bit 0 being the leas t

significant.

❏ A word is 16 bits, numbered 0 th rough 15, wit h bit 0 bei ng the le ast

significant.

❏ A longword is 32 bi ts, numbered 0 throug h 31 , wit h bit 0 being the

least significant.

The terms control bit, status bit, true, and false are used extensively in this
document. The term control bit is used to describe a bit in a register that
can be set and cleared under software control. The term true is used to
indicate that a bit is in the state that enables the function it controls. The
term false is used to indicate that the bit is in the state that disables the
function it controls. In all tables, the terms 0 and 1 are used to describe the
actual value that sh ould be written to the bit, or the value that it yields when
read. The term status bit is used to describe a bit in a register that reflects
a specific condition. The status bit can be read by software to determine
operational or exception conditions.

xxiii

1Board Description and Memory

Introduction

This manual provides programming in formatio n for Motorola MVME3604
and MVME4604 VME Processor Modules (VMEmodules) , that are based
on the MVME3604-xxxx base boa rd, the PM604-xxxx me zzanine modules,
and the RAM201-xxx mezzanine modules. Extensive programming
information is pr ovided for several Appl ication-Specific I ntegrated Circuit
(ASIC) devices used on the boards. Reference information is included in
Appendix A for the Large Scale Integr ation (LSI) devices used on the boards
and sources for additional inf ormat ion are listed.

This chapter briefly describes the board level hardware features of the
MVME3600 series and MVME4600 series VME P rocessor Modules. Th e
chapter begins with a board level overview and features li st. Memory maps
are next, and are the major feature of this chapter.

Programmable registers in the MVME3600 serie s and MVME4600 series
that reside in ASICs are covered in the chapters on those ASICs.

2, Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

covers the Raven (processor-to-PCI bridge),

Memory Controller Chipset

controller),
Universe chip (VMEbus to PC I bus), and
covers certain programming features, such as interrupts and exceptions.

Appendix A, Related Documentation lists all related documentation.

Maps

Chapter 3, Falcon ECC

covers the Falcon chipset (ECC memory

Chapter 4, Universe (VMEbus to PCI) Chip covers the

Chapter 5, Progr amming Details

1

Chapter

Overview

The MVME3600 series and MVME4600 series VME Processor Module
families, hereafter sometimes referred to simply as the MVME3600 and
MVME4600, or the V3600 series and V4600 series, provide many
standard features required by a compute r system: SCSI, Ethernet interface,
graphics, keyboard in terface, mouse interface , sync and asyn c serial ports ,
parallel port, boot Flash, and up to 1GB of ECC DRAM.

1-1

1

Board Description and Memory Maps

Mixing of MVME3600/4600 base and processor/memory modules with

!

Caution

MVME160x processor/memory and base modules is NOT supported.
Motorola cannot predict or guarantee the performance of any such mixture of
modules.

Summary of Features

There are many models based on the MVME3600/46 00 series architecture.
The following table summarizes the major features of the
MVME3600/4600 series:

Table 1-1. MVME3600/4600 Series Features Summary

Feature Description

Processors Single(MVME3600) or dual (twin) (MVME4600 only)

Supports MPC604 BGA processors only
Bus Clock Frequencies up to 66 MHz

L2 Cache 512KB Look-aside L2 Cache

Flash 8MB (64-bit wide), with socketed 1MB (16-bit wide)

DRAM 64 to 1GB;

ECC Protected (Single-bit Correction, Double-bit Detection)
Two-way Interleaved

NVRAM 8KB

RTC MK48T59/559 Device

1-2 Computer Group Literature Center Web Site

Table 1-1. MVME3600/4600 Series Features Summary (Continued)

Feature Description

Peripheral
Support

VME Interface 32-bit Address/64-bit Data PCI

PMC Slots One 32/64-bit Slot

Miscellaneous RESET/ABORT Switches

Two async serial ports
Two sync/async serial ports
One (IEEE1284, or printer) Parallel Port
8-bit or 16-bit single-ended primary fast SCSI-2 interface
16-bit differential or single-ended secondary fast SCSI-2 interface

(MVME3600)
16-bit differential or single-ended secondary Ultra SCSI interface

(MVME4600)
AUI or 10BaseT/100BaseTX primary Ethernet interface
AUI secondary Ethernet interface (MVME3600);

10BaseT/100BaseT secondary Ethernet interface (MVME4600)
1280 x 1024 Graphics Interface
One PS/2 Keyboard and one PS/2 Mouse
One PS/2 Floppy Port

A32/A24/A16, D64 (MBLT)/D32/D16/D08 Master and Slave
Programmable Interrupter & Interrupt Handler
Full System Controller Functions
Programmable DMA Controller with link list support
Location Monitor

Status LEDs

Introduction

1

Block Diagrams

The MVME3600 and MVME4600 series provide 512KB look-aside
external cache. The Falcon chipset controls the boot Flash and the ECC
DRAM. The Raven ASIC functions as the 64-bit PCI host bridge and the
MPIC interrupt controller. PCI devices include: SCSI, VME, graphics,
Ethernet, and one PMC slot. Standard I/O functions are provided by the
Super I/O device which r esides on the ISA bus . The NVRAM/RTC and the

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1

Board Description and Memory Maps

optional synchronous serial ports also reside on the ISA bus. The general
system block diagrams for the MVME3600 series and the MVME4600
series are shown below:

1-4 Computer Group Literature Center Web Site

GENERATOR

SECONDARY

ETHERNET

AND SCSI

CLOCK

L2 CACHE

256K

PROCESSOR

MPC604

PHB & MPIC

RAVEN ASIC

PROCESSOR/MEMORY MEZZANINE

DEBUG CONNECTOR

66MHz MPC604 PROCESSOR BUS

33MHz 32/64-BIT PCI LOCAL B US

PCI CONNECTOR

33MHz 32/64-BIT PCI LOCAL B US

VIDEO
DRAM

MEMORY EXPANSION CONNECTORS

(64MB-1GB DRAM O N M EZZ A N INE )

32MB-64MB

MEMORY CONTROLLER

FALCON CHIPSET

DRAM

Flash

1MB

Flash

4MB or 8MB

SYSTEM

REGISTERS

PCI EXPANSION

Introduction

1

GRAPHICS

CL-GD54XX

GRAPHICS

ISA

REGISTERS

FLOPPY & LED

MOUSE KBD

64-BIT PMC SLOT

PMC FRONT I/O SLOT

FRONT PANEL

PIB

W83C553

ISA BUS

SUPER I/O

PC87308

SERIAL

PARALLEL

712/761 P2 I/O OPTIONS

VME P2 VME P1

ETHERNET

DEC21140

AUI/10BT/100BTX

RTC/NVRAM/WD

MK48T559

ESCC
85230

CIO

Z8536

SCSI

53C825A

VME BRIDGE

UNIVERSE

BUFFERS

BASE BOARD

Figure 1-1. MVME3600 Series System Block Diagram

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1

Board Description and Memory Maps

PROCESSOR/MEMORY MEZZANINE

MEMORY EXPANSION CONNECTORS

(64MB-1GB DRAM ON MEZZANINE)

4MB or 8MB

DRAM

64MB

MEMORY CONTROLLER

FALCON CHIPSET

REGISTERS

PCI EXPANSION

Flash

1MB

Flash

SYSTEM

GENERATOR

SECONDARY

ETHERNET

AND SCSI

CLOCK

L2 CACHE

256K

PROCESSOR 0

MPC604

PROCESSOR 1

MPC604

PHB & MPIC
RAVEN ASIC

DEBUG CONNECTOR

66MHz MPC604 PROCESSOR BUS

33MHz 32/64-BIT PCI LOCAL BUS

PCI CONNECTOR

33MHz 32/64-BIT PCI LOCAL BUS

VIDEO
DRAM

GRAPHICS

CL-GD54XX

GRAPHICS

ISA

REGISTERS

FLOPPY & LED

MOUSE KBD

64-BIT PMC SLOT

PMC FRONT I/O SLOT

FRONT PANEL

PIB

W83C553

ISA BUS

SUPER I/O

PC87308

SERIAL

PARALLEL

712/761 P2 I/O OPTIONS

VME P2 VME P1

ETHERNET

DEC21140

AUI/10BT/100BTX

RTC/NVRAM/WD

MK48T559

ESCC
85230

CIO

Z8536

SCSI

53C825A

VME BRIDGE

UNIVERSE

BUFFERS

BASE BOARD

Figure 1-2. MVME4600 Series System Block Diagram

1-6 Computer Group Literature Center Web Site

Functional Description

Overview

The MVME3600 series is a family of two-slot VME Processor Modules.
It consists of the MPC604 processor, the Raven PCI Bridge & Interrupt
Controller, the ECC Memory Controller Falcon chipset, 9MB of Flash
memory, 64MB to 1GB of ECC-protected DRAM, and a rich set of
features for support of I/O peripherals.

The MVME4600 series is a very si milar series of two-s lot VME Processor
Modules. It contains two MPC604 proc essors, and 64MB to 1GB of ECC­protected DRAM.

I/O peripheral devices on the PCI bus are: SCSI chip, Ethernet chip,
graphics chip, Universe VMEbus interface ASIC, and one PMC slot.
Secondary SCSI and sec ondary Eth ernet are option al. Func tions provi ded
from the ISA bus are: a P1284/para llel port, two asynchronous se rial ports,
two sync/async serial ports, a real-time clock, and counters/timers.

Functional Description

1

The MVME3600/4600 series board interfaces to the VMEbus via the P1
and P2 connectors, which use the new 5-row 160-pin connectors as
specified in the propos ed VME64 Exten sion Sta ndard. I t also draws +5V,
+12V, and –12V power from the VMEbus backplane through these two
connectors. The 3.3V supply is regulated onboard from the +5V power.

Front panel connectors on the MVME3600/4600 series board include: a
three-row DB-15 connector for graphics, a 6-pin circular DIN connector
for the keyboard interface, a 6-pin circular DIN connector for the mouse
interface, and a 50-pin connector for an external floppy disk drive and
status hexadecimal LEDs. All signals f or the serial port s, the P1284/print er
port, the SCSI interface, and the Ethernet interface are routed to P2.

There are two P2 I/O options suppo rted by the MVME3600 ser ies and the
MVME4600 series: MVME712M mode and MVME761 mode. The
MVME761 mode provides an enha nce d P1284 parallel port i nt erf ac e a nd
full synchronous support for Serial Ports 3 and 4. The MVME712M
version provides backward compatibility with previous single board

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1

Board Description and Memory Maps

computers (SBCs). In either mode, 16- bit SCSI capability can only be used
by systems with 5-row DIN s upport because the addi ti ona l 8 bits of SCSI
data lines reside on row Z of P2.

The MVME3600/4600 series contains one IEEE1386.1 PCI Mezzanine
Card (PMC) slot. This PMC s lot i s 64-bit capable an d su ppor ts both front
and rear I/O. Pins 1 through 30 of th e PMC connector J14 are routed to pins
D1 through D30 of the 5-row DIN P2 connector. J14 pin 31 is connected
to P2 pin Z29, and J14 pin 32 is connected to P2 pin Z31.

Additional PCI expansion is supported with a 114-pin Mictor connector.
This connection allows stacking of a carrier board (such as a dual-PMC
carrier board) to increase the I/O capability.

Programming Model

Memory Maps

The following sections describe the memory maps for the
MVME3600/4600 series.

Processor Memory Maps

The processor memory map is controlled by the Raven ASIC and the
Falcon chipset. The Raven ASIC and the Falcon chipset have flexible
programming Map Decoder registers to customize the system to fit many
different applications.

1-8 Computer Group Literature Center Web Site

Programming Model

Default Processor Memory Map

After a reset, the Raven ASIC and the Falcon chipset provide the default
processor memory map as shown in the following table.

Table 1-2. Default Processor Memory Map

1

Processor Address

Start End

0000 0000 7FFF FFFF 2G Not mapped
8000 0000 8001 FFFF 128K PCI/ISA I/O Space 1
8002 0000 FEF7 FFFF 2G - 16M

FEF8 0000 FEF8 FFFF 64K Falcon Registers
FEF9 0000 FEFE FFFF 384K Not mapped
FEFF 0000 FEFF FFFF 64K Raven Registers
FF00 0000 FFEF FFFF 15M Not mapped
FFF0 0000 FFFF FFFF 1M ROM/Flash Bank A or Bank B 2

Size Definition

Not mapped

- 640K

Notes

1. This default map for PCI/ISA I/O space allows software to
determine if the system is MPC105-based or Falcon/Raven-based
by examining either the PHB Device ID or the CPU Type Register.

Notes

2. The first 1MB of ROM/Flash Bank A appears at this range after a
reset if the rom_b_rv control bit in the Falcon ch ip is cleared and t he
rom_a_rv control bit is set. If the rom_b_rv control bit is set then
this address range maps to ROM/Flash Bank B.

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1

Board Description and Memory Maps

Processor CHRP Memory Map

The following table shows a recomm ended CHRP memory map from the
point of view of the processor.

Table 1-3. CHRP Memory Map Example

Processor Address

Size Definition

Start End

0000 0000 top_dram dram_size System Memory (onboard DRAM) 1, 2
4000 0000 FCFF FFFF 3G - 48M PCI Memory Space:

4000 0000 to FCFF FFFF

FD00 0000 FDFF FFFF 16M Zero-Based PCI/ISA Memory Space

(mapped to 00000000 to 00FFFFFF)

FE00 0000 FE7F FFFF 8M Zero-Based PCI/ISA I/O Space

(mapped to 00000000 to 007FFFFF)

FE80 0000 FEF7 FFFF 7.5M Reserved
FEF8 0000 FEF8 FFFF 64K Falcon Registers
FEF9 0000 FEFE FFFF 3 84K Reserved
FEFF 0000 FEFF FFFF 64K Raven Registers (Table 1-7 has

MPIC)

FF00 0000 FF7F FFFF 8M ROM/Flash Bank A 1,7
FF80 0000 FF8F FFFF 1M ROM/Flash Bank B 1,7

Notes

3,4,8

3,8

3,5,8

9

FF90 0000 FFEF FFFF 6M Reserved
FFF0 0000 FFFF FFFF 1M ROM/Flash Bank A or Bank B 7

Notes

1. Programmable via Falcon chipset.

1-10 Computer Group Literature Center Web Site

Programming Model

2. To enable the “Processor-ho le” area, prog ram the Falcon chi pset to
ignore 0x000A0000 - 0x000BFFFF add ress range and progra m the
Raven to map this address range to PCI memory space.

3. Programmable via Raven ASIC.

4. CHRP requires the star ting addr ess for t he PCI memory space to b e
256MB-aligned.

5. Programmable via Raven ASIC for ei ther cont iguous or spr ead-I/O
mode.

6. The actual size of each ROM/Flash bank may vary.

7. The first 1MB of ROM/Flash Bank A appears at this range after a
reset if the rom_b_rv control bit in the Falcon ch ip is cleared and t he
rom_a_rv control bit is set. If the rom_b_rv control bit is set then
this address range maps to ROM/Flash Bank B.

8. This range can be mapped to the VMEbus by programming the
Universe ASIC accordingly. The map shown is the recommended
setting which uses the Sp eci al PCI Sl ave Ima ge a nd two of th e four
programmable PCI Slave Images.

1

9. The only method of generating a PCI Inter rupt Acknowledge cycle
(8259 IACK) is to perform a read access to the Raven’s PIACK
register at 0xFEFF0030.

The following table shows the programmed values for the associated
Raven MPC registers for the processor CHRP memory map.

Table 1-4. Raven MPC Register Values for CHRP Memory Map

Address Register Name Register Value

FEFF 0040 MSADD0 4000 FCFF

FEFF 0044 MSOFF0 & MSATT0 0000 00C2

FEFF 0048 MSADD1 FD00 FDFF

FEFF 004C MSOFF1 & MSATT1 0300 00C2

FEFF 0050 MSADD2 0000 0000

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1

Board Description and Memory Maps

Table 1-4. Raven MPC Register Values for CHRP Memory Map (Continued)

Address Register Name Register Value

FEFF 0054 MSOFF2 & MSATT2 0000 0002

FEFF 0058 MSADD3 FE00 FE7F

FEFF 005C MSOFF3 & MSATT3 0200 00C0

Processor PREP Memory Map

The Raven/Falcon chipset can be programmed for a PREP-compatible
memory map. The following table shows the PREP memory map of the
MVME3600/4600 series from the point of view of the processor.

Table 1-5. PREP Memory Map Example

Processor Address

Start End

0000 0000 top_dram dram_size System Memory (onboard DRAM) 1
8000 0000 BFFF FFFF 1G Zero-Based PCI I/O Space:

C000 0000 FCFF FFFF 1G - 48M Zero-Based PCI/ISA Memory

FD00 0000 FEF7 FFFF 40.5M Reserved
FEF8 0000 FEF8 FFFF 64K Falcon Registers
FEF9 0000 FEFE FFFF 384K Reserved
FEFF 0000 FEFF FFFF 64K Raven Registers (Table 1-10 on

FF00 0000 FF7F FFFF 8M ROM/Flash Bank A 1, 3
FF80 0000 FF8F FFFF 1M ROM/Flash Bank B 1, 3
FF90 0000 FFEF FFFF 6M Reserved
FFF0 0000 FFFF FFFF 1M ROM/Flash Bank A or Bank B 4

Size Definition Notes

2

0000 0000 - 3FFFF FFFF

2, 5

Space: 0000 0000 - 3CFFFFFF

6

page 1-17

has MPIC)

1-12 Computer Group Literature Center Web Site

Programming Model

Notes

1. Programmable via Falcon chipset.

2. Programmable via Raven ASIC.

3. The actual size of each ROM/Flash bank may vary.

4. The first 1MB of ROM/Flash Bank A appears at this range after a
reset if the rom_b_rv control bit in the Falcon ch ip is cleared and t he
rom_a_rv control bit is set. If the rom_b_rv control bit is set then
this address range maps to ROM/Flash Bank B.

5. This range can be mapped to the VMEbus by programming the
Universe ASIC accordingly.

6. The only method of generating a PCI Inter rupt Acknowledge cycle
(8259 IACK) is to perform a read access to the Raven’s PIACK
register at 0xFEFF0030.

The following table shows the programmed values for the associated
Raven MPC registers for the processor PREP memory map.

1

Table 1-6. Raven MPC Register Val ues for PREP Memory Map

Address Register Name Register Value

FEFF 0040 MSADD0 C000 FCFF
FEFF 0044 MSOFF0 & MSATT0 4000 00C2
FEFF 0048 MSADD1 0000 0000
FEFF 004C MSOFF1 & MSATT1 0000 0002
FEFF 0050 MSADD2 0000 0000
FEFF 0054 MSOFF2 & MSATT2 0000 0002
FEFF 0058 MSADD3 8000 BFFF
FEFF 005C MSOFF3 & MSATT3 8000 00C0

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Board Description and Memory Maps

PCI Configuration Access

PCI Configuration acc esses ar e accomplis hed via the CONFIG_ADD and
CONFIG_DAT registers. These two registers are implemented by the
Raven ASIC. In the CHRP memory map example, the CONFIG_ADD and
CONFIG_DAT registers are located at 0xFE000CF8 and 0xFE000CFC,
respectively. With the PREP memory map, the CONFIG_ADD register
and the CONFIG_DAT register are located at 0x80000CF8 and
0x80000CFC, respectively.

PCI Memory Maps

The PCI memory map is controlled by the Raven ASIC and the Universe
ASIC. The Raven ASIC and the Universe ASIC have flexible
programming Map Decoder registers to customize the system to fit many
different applications.

Default PCI Memory Map

After a reset, the Raven ASIC and the Univer se ASIC turn all the PCI slave
map decoders off. Software must program the appropriate map decoders
for a specific environment.

PCI CHRP Memory Map

The following table shows a PCI memory map of the MVME3600/4600
series that is CHRP-compatible fro m the point of view of the PCI local bu s.

Table 1-7. PCI CHRP Memory Map

PCI Address

Start End

0000 0000 top_dram dram_size Onboard ECC DRAM 1
4000 0000 EFFF FFFF 3G - 256M VMEbus A32/D32 (Super/Program) 3
F000 0000 F7FF FFFF 128M VMEbus A32/D16 (Super/Program) 3
F800 0000 F8FE FFFF 16M - 64K VMEbus A24/D16 (Super/Program) 4
F8FF 0000 F8FF FFFF 64K VMEbus A16/D16 (Super/Program) 4

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Size Definition Notes

Table 1-7. PCI CHRP Memory Map (Continued)

Programming Model

1

PCI Address

Size Definition Notes

Start End

F900 0000 F9FE FFFF 16M - 64K VMEbus A24/D32 (Super/Data) 4
F9FF 0000 F9FF FFFF 64K VMEbus A16/D32 (Super/Data) 4
FA00 0000 FAFE FFFF 16M - 64K VMEbus A24/D16 (User/Program) 4
FAFF 0000 FAFF FFFF 64K VMEbus A16/D16 (User/Program) 4
FB00 0000 FBFE FFFF 16M - 64K VMEbus A24/D32 (User/Data) 4
FBFF 0000 FBFF FFFF 64K VMEbus A16/D32 (User/Data) 4
FC00 0000 FC03 FFFF 256K RavenMPIC 1

FC04 0000 FCFF FFFF 16M - 256K PCI Memory Space

FD00 0000 FDFF FFFF 16M PCI Memory Space or

System Memory Alias Space
(mapped to 00000000 to 00FFFFFF)

FE00 0000 FFFF FFFF 48M Reserved

Notes

1

1. Programmable via the Raven’s PCI Configuration registers.

2. To enable the CHRP “io-hole”, program the Raven to ignore the
0x000A0000 - 0x000FFFFF address range.

3. Programmable mapping via the four PCI Slave Images in the
Universe ASIC.

4. Programmable mapping via the Special Slave Image (SLSI) in the
Universe ASIC.

The following table shows the programmed values for the associated
Raven PCI registers for the PCI CHRP memory map.

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Board Description and Memory Maps

Table 1-8. Raven PCI Register Values for CHRP Memory Map

Configuration

Address Offset

$14 RavenMPIC MBASE FC00 0000 FC00 0000
$80 PSADD0 0000 3FFF 0100 3FFF
$84 PSOFF0 & PSATT0 0000 00FX 0000 00FX
$88 PSADD1 0000 0000 FD00 FDFF
$8C PSOFF1 & PSATT1 0000 0000 0000 00FX
$90 PSADD2 0000 0000 0000 0000
$94 PSOFF2 & PSATT2 0000 0000 0000 0000
$98 PSADD3 0000 0000 0000 0000
$9C PSOFF3 & PSATT3 0000 0000 0000 0000

Configuration

Register Name

Register Value

(Aliasing OFF)

Register Value

(Aliasing ON)

The next table shows the programmed values for the associated Universe
PCI registers for the PCI CHRP memory map.

Table 1-9. Universe PCI Register Values for CHRP Memory Map

Configuration

Address Offset

Configuration

Register Name

Register Value

$100 LSI0_CTL C082 5100
$104 LSI0_BS 4000 0000
$108 LSI0_BD F000 0000
$10C LSI0_TO XXXX 0000
$114 LSI1_CTL C042 5100
$118 LSI1_BS F000 0000
$11C LSI1_BD F800 0000
$120 LSI1_TO XXXX 0000

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Programming Model

Table 1-9. Universe PCI Register Values for CHRP Memory Map (Continued)

1

Configuration

Address Offset

$128 LSI2_CTL 0000 0000
$12C LSI2_BS XXXX XXXX
$130 LSI2_BD XXXX XXXX
$134 LSI2_TO XXXX XXXX
$13C LSI3_CTL 0000 0000
$140 LSI3_BS XXXX XXXX
$144 LSI3_BD XXXX XXXX
$148 LSI3_TO XXXX XXXX
$188 SLSI C0A053F8

Configuration
Register Name

Register Value

PCI PREP Memory Map

The following table shows a PCI memory map of the MVME3600/4600
series that is PREP-compatible f rom the poi nt of view of t he PCI loca l bus.

Table 1-10. PCI PREP Memory Map

PCI Address

Start End

0000 0000 00FF FFFF 16M PCI/ISA Memory Space
0100 0000 2FFF FFFF 752M VMEbus A32/D32 (Super/Program) 3
3000 0000 37FF FF FF 128M VMEbus A32/D16 (Super/Program) 3
3800 0000 38FE FFFF 16M - 64K VMEbus A24/D16 (Super/Program) 4
38FF 0000 38FF FFFF 64K VMEbus A16/D16 (Super/Program) 4
3900 0000 39FE FFFF 16M - 64K VMEbus A24/D32 (Super/Data) 4
39FF 0000 39FF FFFF 64K VMEbus A16/D32 (Super/Data) 4

http://www.motorola.com/computer/literature 1-17

Size Definition Notes

1

Board Description and Memory Maps

Table 1-10. PCI PREP Mem ory Map (Continued)

PCI Address

Start End

3A00 0000 3AFE FFFF 16M - 64K VMEbus A24/D16 (User/Program) 4
3AFF 0000 3 A FF FFFF 64K VMEbus A16/D16 (User/Program) 4
3B00 0000 3BFE FFFF 16M - 64K VMEbus A24/D32 (User/Data) 4
3BFF 0000 3BFF FFFF 64K VMEbus A16/D32 (User/Data) 4
3C00 0000 7FFF FFFF 1 G + 64M PCI Memory Space
8000 0000 FBFF FFFF 2G - 64M Onboard ECC DRAM 1
FC00 0000 FC03 FFFF 256K RavenMPIC 1
FC04 0000 FFFF FFFF 64M - 256K PCI Memory Space

Size Definition Notes

Notes

1. Programmable via the Raven’s PCI Configuration registers.

2. To enable the CHRP “io-hole”, program the Raven to ignore the
0x000A0000 - 0x000FFFFF address range.

3. Programmable mapping via the four PCI Slave Images in the
Universe ASIC.

4. Programmable mapping via the Special Slave Image (SLSI) in the
Universe ASIC.

The following table shows the programmed values for the associated
Raven PCI registers for the PREP-compatible memory map.

1-18 Computer Group Literature Center Web Site

Programming Model

Table 1-11. Raven PCI Register Values for PREP Memory Map

1

Configuration

Address Offset

$14 RavenMPIC MBASE FC00 0000
$80 PSADD0 8000 FBFF
$84 PSOFF0 & PSATT0 8000 00FX
$88 PSADD1 0000 0000
$8C PSOFF1 & PSATT1 0000 0000
$90 PSADD2 0000 0000
$94 PSOFF2 & PSATT2 0000 0000
$98 PSADD3 0000 0000
$9C PSOFF3 & PSATT3 0000 0000

Configuration
Register Name

Register Value

The next table shows the programmed values for the associated Universe
PCI registers for the PCI PREP memory map.

Table 1-12. Universe PCI Register Values for PREP Memory Map

Configuration

Address Offset

Configuration
Register Name

Register Value

$100 LSI0_CTL C082 5100
$104 LSI0_BS 0100 0000
$108 LSI0_BD 3000 0000
$10C LSI0_TO XXXX 0000
$114 LSI1_CTL C042 5100
$118 LSI1_BS 3000 0000
$11C LSI1_BD 3800 0000
$120 LSI1_TO XXXX 0000

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1

Board Description and Memory Maps

Table 1-12. Universe PCI Register Values for PREP Memory Map

Configuration

Address Offset

$128 LSI2_CTL 0000 0000
$12C LSI2_BS XXXX XXXX
$130 LSI2_BD XXXX XXXX
$134 LSI2_TO XXXX XXXX
$13C LSI3_CTL 0000 0000
$140 LSI3_BS XXXX XXXX
$144 LSI3_BD XXXX XXXX
$148 LSI3_TO XXXX XXXX
$188 SLSI C0A05338

VMEbus Mapping

VMEbus Master Map

The processor can access a ny address range in the VME bus with help from
the address translation capabilities of the Universe ASIC. The
recommended mapping is shown i n
The following figure illustrates how the VMEbus master mapping is
accomplished.

Configuration

Register Name

Register Value

Processor Memory Maps on page 1-8 .

1-20 Computer Group Literature Center Web Site

Programming Model

1

ONBOARD

MEMORY

PCI MEMORY

SPACE

PCI/ISA

MEMORY SPACE

PCI

I/O SP AC E

NOTE 1

NOTE 1

PCI MEMORYPROCESSOR

NOTE 2

NOTE 3

VMEBUS

PROGRAMMABLE

SPACE

VME A24

VME A16

VME A24

VME A16

VME A24

VME A16

VME A24

VME A16

MPC

RESOURCES

11553.00 9609

Figure 1-3. VMEbus Master Mapping

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1

Board Description and Memory Maps

Notes

1. Programmable mapping done by the Raven ASIC.

2. Programmable mapping via the four PCI Slave Images in the
Universe ASIC.

3. Programmable mapping via the Special Slave Image (SLSI) in the
Universe ASIC.

VMEbus Slave Map

The four programmable VME Slave Images in the Universe ASIC allow
other VMEbus masters to get to any devices on the MVME3600/4600
series. The combination of the four Universe VME Slave Images and the
four Raven PCI Slave Deco ders offers a lo t of flexibility for mapping the
system resources as seen from the VMEbus. In most applications, the
VMEbus only needs to s ee the syste m memory and , pe rhaps, the so ftware
interrupt registe rs (SI R1 and SIR2 regis ters) . An exampl e of the VMEbus
slave map is shown below:

1-22 Computer Group Literature Center Web Site

Programming Model

1

Processor

Onboard

Memory

ISA Space

Software INT

Registers

NOTE 2

NOTE 3

PCI Memory

PCI I/O Space

VMEbus

NOTE 1

NOTE 1

1896 9609

Figure 1-4. VMEbus Slave Mapping

Notes

1. Programmable mapping via the four VME Slave Images in the
Universe ASIC.

2. Programmable mapping via PCI Slave Images in the Raven ASIC.

3. Fixed mapping via the PIB device.

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1

Board Description and Memory Maps

The following table shows the programmed values for the associated
Universe registers for the VMEbus slave function.

Table 1-13. Universe PCI Register Values for VMEbus Slave Map Example

Configuration

Address Offset

$F00 VSI0_CTL C0F2 0001 C0F2 0001
$F04 VSI0_BS 4000 000 0 4000 0000
$F08 VSI0_BD 4000 1000 4000 1000
$F0C VSI0_TO C000 1000 C000 1000
$F14 VSI1_CTL E0F2 00C0 E0F2 00C0
$F18 VSI1_BS 1000 000 0 1000 0000
$F1C VSI1_BD 2000 0000 2000 0000
$F20 VSI1_TO F000 0000 7000 0000
$F28 VSI2_CTL 0000 0000 0000 0000
$F2C VSI2_BS XXXX XXXX XXXX XXXX
$F30 VSI2_BD XXXX XXXX XXXX XXXX
$F34 VSI2_TO XXXX XXXX XXXX XXXX
$F3C VSI3_CTL 0000 0000 0000 0000

Configuration

Register Name

Register Valu e

(CHRP)

Register Value

(PREP)

$F40 VSI3_BS XXXX XXXX XXXX XXXX
$F44 VSI3_BD XXXX XXXX XXXX XXXX
$F48 VSI3_TO XXXX XXXX XXXX XXXX

The above register values yield the following VMEbus slave map:

1-24 Computer Group Literature Center Web Site

Table 1-14. VMEbus Slave Map Example

Programming Model

1

VMEbus Address

Size CHRP Map PREP Map

Range Mode

4000 0000 ­4000 0FFF

1000 0000 ­1FFF FFFF

A32 U/S/P/D
D08/16/32

A32 U/S/P/D
D08/16/32/64
RMW

4K PCI/ISA I/O Space:

0000 1000 - 0000 1FFF

256M PCI/ISA Memory Space

(On-board DRAM)
0000 0000 - 0FFF FFFF

Falcon-Controlled System Registers

The Falcon chipset latches the states of the DRAM data lines onto the
PR_STAT1 and PR_STAT2 registers. The MVME3600/4600 series uses
these status registers to provide the system configuration information. In
addition, the Falcon chipset performs the decode and control for an
external register port. This function is utilized by the MVME3600/4600
series to provide the system control registers.

Table 1-15. System Register Summary

0

BIT # ---->
FEF80400
FEF80404

FEF88000

FEF88300

123

System External Cache

Control Register

CPU Control Register

4

5678910111213141516171819202122232425262728293031

System Configuration Register (Upper Falcon’s PR_STAT1)

Memory Configuration Register (Lower Falcon’s PR_STAT1)

PCI/ISA I/O Space:
0000 1000 - 0000 1FFF

PCI/ISA Memory Space
(On-board DRAM)
8000 0000 - 8FFF FFFF

The following subsections describe these system registers in detail.

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1

Board Description and Memory Maps

System Configuration Register (SYSCR)

The states of the RD[0:31] DRAM data pins, which have weak internal
pull-ups, are l atched by the upper Falcon chip at a ris ing edge of th e power­up reset and stored in this System Configu ration Regist er to provid e some
information about t he system. Configuration is accomplished wit h external
pull-down resistors. This 32-bit read-only register is defined as follows:

REG System Configuration Register - $FEF80400

BIT

FIELD
OPER
RESET

012345678

SYSID SYSCLK SYSXC P0STAT P1STAT

$FE X X X X $F $F

SYSID System Identification. This field specifies the type of the

SYSCLK System Clock Speed. This field re lays the system clock

SYSCLK Value System Clock Speed PCI Clock Speed

0b0000 to 0b1100 Reserved Reserved

0b1101 50 MHz 25 MHz
0b1110 60 MHz 30 MHz
0b1111 66.66 MHz 33.33 MHz

101112131415161718192021222324252627282930

9

READ ONLY

overall system configuration so that the software may
appropriately hand le any softwa re visible differences . For
the MVME3600 series and the MVME4600 series, this
field returns a value of $FE.

speed and the PCI clock speed information as follows:

31

SYSXC System External Cache Size. This field reflec ts size of the

look-aside cache on the system bus.

1-26 Computer Group Literature Center Web Site

Programming Model

SYSXC V alue External Look-aside Cache Size

0b0000 to 0b1011 Reserved

0b1100 1M
0b1101 512K
0b1110 256K

0b1111 None

P0/1STAT Processor 0/1 Status. This field is encoded as follows:

1

P0/1STAT Value Processor 0/1 Present

0b0000 to 0b0011 Reserved Reserved

0b0100 YES 1M
0b0101 YES 512K
0b0110 YES 256K
0b0111 YES None

0b1000 to 0b1111 NO N/A

Memory Configuration Register (MEMCR)

The states of the RD[00:31] DRAM data pins, which have weak internal
pull-ups, are lat ched by the lowe r Falcon chip a t a rising edge of the power­up reset and s tored in this Memory Configuration Regis ter to provide some
information about the system memory. Configuration is accomplished
with external pull-d own resistors. Thi s 32-bit read-on ly register is defined
as follows :

External In-line

Cache Size

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1

Board Description and Memory Maps

REG Memory Configuration Register - $FEF80404

BIT

FIELD

OPER
RESET

32333435363738394041424344454647484950515253545556575859606162

M_FREF

111X1

1

M_SPD0

M_SPD1

X

X

R_A_TYP0

R_A_TYP1

R_A_TYP2

R_B_TYP0

R_B_TYP1

R_B_TYP2

XXX1XXXXXXXXXXXXXXXXXXX

1

M_FREF Block A/B/C/D Fast Refresh. When this bit is set, it

indicates that a DRAM block requires faster refresh rate.
If any of the four blocks requires faster refresh rate then
the ram ref

control bit should be set.

M_SPD[0:1]

Memory Speed. This field relays the memory speed
information as follows:

M_SPD[0:1] DRAM Speed DRAM Type

0b00 70ns Past Page
0b01 60ns Fast Page

63

0b10 Reserved Reserved
0b11 50ns EDO

These two bi ts reflect the combined status of the four
blocks of DRAM. Initialization software uses this
information to program the ram_spd0

and ram_spd1

control bits in the Falcon’s Chip Revision Register.

1-28 Computer Group Literature Center Web Site

R_A/B_TYP[0:1]

ROM/Flash Type. This field is encoded as follows:

ROM_A/B_TYP[0:2] ROM/Flash Type

0b000 to 0b101 Reserved

0b110 Intel 16-bit wide Flash with 1 6K B ot tom Boot

Block

0b111 Unknown type (for example, ROM/Flash Sockets)

Note The device width is different from the width of the Flash b ank. I f

the bank width is 64-bit and the device width is 16-bit then the
Flash bank consists of four Flash devices.

System External Cache Control Register (SXCCR)

The System Cache Control Register is accessed via the RD[32:39] data
lines of the upper Falcon device. This 8-bit register is defined as follows:

Programming Model

1

REG System External Cache Control Register - $FEF88000
BIT 0 1 2 3 4 5 6 7

SXC_DIS_

FIELD

OPER R/W
RESET 1 1 1 1 X X X X

SXC_RST_

SXC_MI_

SXC_FLSH_

SXC_DIS_

System External Cache Enable. When this bit is cleared,
it disables this cache from responding to any bus cycles.

SXC_FLSH_

System External Cache Flush. When this bit

for at least 8 clock periods

http://www.motorola.com/computer/literature 1-29

, it causes the system external

is pulsed true

1

Board Description and Memory Maps

cache to write back dirty cache lines out to system

!

Warning

memory and clears all the tag valid bits.

causes the Glance pair to request and hold the MPC bus
until it has compl ete d the flush operati on ( approximately
4100 clock cycles). This may be an issue if other devices
cannot wait that long to become MPC bus master.

SXC_RST_

System External Cache Reset. When thi s b it is cleared, it
invalidates all tags and holds the cache in a reset
condition.

hold the chip in a reset condition. The tag invalidate still
works okay though.

SXC_MI_

System External Cache Miss Inhibit. When this bit is
cleared, it prevents line fills on cache misses.

Software should never clear more than one of these bits at the same time.
If more than one is cleared at the same time, the Glance pair behaves
indeterminately.

There is a bug in Glance - It really does not

This operation

1-30 Computer Group Literature Center Web Site

ISA Local Resource Bus

CPU Control Register

The CPU Control Register is accesse d via the RD[32 :39] dat a lines of the
upper Falcon device. This 8-bit register is defined as follows:

REG CPU Control Register - $FEF88300
BIT 0 1 2 3 4 5 6 7

LEMODE

FIELD

OPER R R R/W R/W R R R R
RESET X 0 1 1 X X X X

LEMODE Little Endian Mode. This bit must be set in conjunction

P0/1_TBEN

P1_TBEN

with the LEND bit in the Raven for little endi an mode.

Processor 0/1 T ime Base Enable. When th is bit is cleared,
the TBEN pin of Processor 0/1 will be driven low.

P0_TBEN

1

ISA Local Resource Bus

W83C553 PIB Registers

The PIB contains ISA Bridge I/O registers for various functions. These
registers are actually accessible from the PCI bus. Refer to the W83C553
Data Book for details.

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1

Board Description and Memory Maps

PC87308VUL Super I/O (ISASIO) Strapping

The PC87308VUL Super I/O (ISASIO) provides the following functions
to the MVME3600/4600 series: a keyboard interface, a PS/2 mouse
interface, a PS/2 floppy port, two async serial ports and a parallel port.
Refer to the PC87308VUL Data Sheet for additional details and
programming information.

The following table shows the hardware strapping for the Super I/O
device:

Table 1-16. Strap Pins Configuration for the PC87308VUL

Pins Reset Configuration

CFG0 0 - FDC, KBC and RTC wake up inactive.
CFG1 1 - Xbus Data Buffer (XDB) enabled.

CFG3, CFG2 00 - Clock source is 24 MHz fed via X1 pin.

BADDR1, BADDR2 11 - PnP Motherboard, Wake in Config State. Index $002E.

SELCS 1 - CS0# on CS0# pin.

NVRAM/RTC & Watchdog Timer Registers

The MK48T59/559 provides t he MVME3600/4600 s eries wit h 8K of non ­volatile SRAM, a time-of-day clock, and a watchdog timer. Accesses to
the MK48T59/559 are accomplished via three registers: The
NVRAM/RTC Address Strobe 0 Register, the NVRAM/RTC Address
Strobe 1 Register, and the NVRAM/RTC Data Port Register. The
NVRAM/RTC Address Strobe 0 Register latches the lower 8 bits of the
address and the NVRAM/RTC Ad dress Strobe 1 Register latches the upper
5 bits of the address.

1-32 Computer Group Literature Center Web Site

ISA Local Resource Bus

Table 1-17. MK48T59/559 Access Registers

PCI I/O Address Function

0000 0074 NVRAM/RTC Address Strobe 0 (A7 - A0)
0000 0075 NVRAM/RTC Address Strobe 1 (A15 - A8)
0000 0077 NVRAM/RTC Data Register

The NVRAM and RTC is accessed through the above three registers.
When accessing a NVRAM/RTC location, follow the following
procedure:

1. Write the low address (A7-A0) of the NVRAM to the
NVRAM/RTC STB0 register,

2. Write the high address (A15-A8) of the NVRAM to the
NVRAM/RTC STB1 register, and

3. Then read or write the NVRAM/RTC Data Port.

1

Refer to the MK48T59/559 Data Sheet for additional details and
programming information.

Module Configuration and Status Registers

Four registers provide the configuration and status information about the
board. These registers are listed in the following table:

Table 1-18. Module Configuration and Status Registers

PCI I/O Address Function

0000 0800 CPU Configuration Register
0000 0802 Base Module Feature Register
0000 0803 Base Module Status Register
0000 08C0 - 0000 08C1 Seven-Segment Display Register

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1

Board Description and Memory Maps

The following subsections describe these registers in detail.

CPU Configuration Register

The CPU Configuration Register is an 8-bit register located at ISA I/O
address x0800. This register is def ined for the MVME3600/ 4600 series to
provide some backward compatibility with older MVME1600 products.
The Base Module Status Register should be used to identify the base
module type and the System Configuration Register should be used to
obtain information about the overall system.

REG Old CPU Configuration Register - $FE000800

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

FIELD CPUTYPE

OPER R R

RESET $E $F

CPUTYPE CPU Type. This field will always read as $E for the

MVME3600/4600 series. The System Configuration
Register should be used for additional information.

Base Module Feature Register

The Base Module Feature Register is an 8-bit register providing the
configuration information about the MVME3600/MVME4600 VME
Processor Module. This read-only register is located at ISA I/O address
x0802.

REG Base Module Feature Register - Offset $0802

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

FIELD

OPER R R R R R R R R

1-34 Computer Group Literature Center Web Site

SCCP_

PMC2P_

PMC1P_

VMEP_

GFXP_

LANP_

SCSIP_

ISA Local Resource Bus

REG Base Module Feature Register - Offset $0802

RESET X X X X X X X X

SCCP_ Z85230 ESCC Present. If set, there is no on-board sync

serial support. If cleared, there is on-board support for
sync serial interface.

PMC2P_ PMC/PCIX Slot 2 Present. If set, there is no PMC/PCIX

device installed in PMC/PCIX Slot 2. If cleared,
PMC/PCIX Slot 2 contains a PCI Mezzanine Card or a
PCI device.

PMC1P_ PMC Slot 1 Present. If set, there is no PCI Mezzanine

Card installed in PMC Slot 1. If cleared, PMC Slot 1
contains a PMC.

VMEP_ VMEbus Present. If se t, t her e i s no VM Ebus int er fac e. I f

cleared, VMEbus interface is supported.

GFXP_ Graphics Present. If set, there is no on-board Graphics

interface. If cleared, there is an on-board graphics
capability.

1

LANP_ Ethernet Present. If set, there is no Ethernet transceiver

interface. If cleared, there is on-boa rd Ethernet support.

SCSIP_ SCSI Present. If set, there is no on-board SCSI interface.

If cleared, on-board SCSI is supported.

Base Module Status Register (BMSR)

The Base Module Status Register is an 8-bit read-only register located at
ISA I/O address x0803.

REG Base Module Status Register - Offset $0803

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
FIELD BASE_TYPE
OPER R

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1

Board Description and Memory Maps

REG Base Module Status Register - Offset $0803

RESET N/A

BASE_TYPE

Base Module Type. This eight bit field is used to pr ovi de
the category of the bas e module and i s defined as follows:

BASE_TYPE Value Base Module Type

$0 to $F9

Reserved

$FA
$FB
$FC
$FD
$FE

$FF

MVME2600 with MVME712M I/O

MVME3600/4600 with MVME712M I/O

MVME3600/4600 with MVME761 I/O

MVME1600-001 or MVME1600-011

Reserved -- Special

MVME2600 with MVME761 I/O

Seven-Segment Display Register

This 16-bi t register allows data to be sent to the 4-d igit hexadec imal
diagnostic display. The register also allows the data to be read back.

REG 7-Segment Display Register - Offset $08C0

SD15

SD14

SD13

BIT

FIELD DIG3[3:0] DIG2[3:0] DIG1[3:0] DIG0[3:0]

OPER R/W

SD12

SD10

SD11

SD9

SD8

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

RESET X X X X X X X X X X X X X X X X

DIG3[3:0] Hexadecimal value of the most significant digit.
DIG2[3:0] Hexadecimal value of the third significant digit.

1-36 Computer Group Literature Center Web Site

DIG1[3:0] Hexadecimal value of the second significant digit.
DIG0[3:0] Hexadecimal value of the least significant digit.

VME Registers

The registers listed in the following table provide these functions for the
VMEbus inte rface: a softwa re interrupt cap ability, a location monitor
function, and a geographical address status. For these registers to be
accessible from the VMEbus , the Univ erse ASI C must be progr ammed to
map the VMEbus Slave Image 0 into the appropriate PCI I/O address
range. Refer to VMEbus Slave Map on page 1-22 for additional details .

Table 1-19. VME Registers

PCI I/O Address Function

0000 1000 LM/SIG Control Register
0000 1001 LM/SIG Status Register

ISA Local Resource Bus

1

0000 1002 VMEbus Location Monitor Upper Base Address
0000 1003 VMEbus Location Monitor Lower Base Address
0000 1004 VMEbus Semaphore Register 1
0000 1005 VMEbus Semaphore Register 2
0000 1006 VMEbus Geographical Address Status

These registers are described in the following subsections.

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1

Board Description and Memory Maps

LM/SIG Control Register

The LM/SIG Control Register is an 8-bit register located at ISA I/O
address x1000. This register provides a method to generate software
interrupts. The Universe ASIC is programmed so that this register can be
accessed from the VMEbus to generate software interrupts to the
processor(s).

REG LM/SIG Control Register - Offset $1000

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

FIELD SET

SIG1

OPER WRITE-ONLY

RESET 0 0 0 0 0 0 0 0

SET

SIG0

SET
LM1

SET
LM0

CLR

SIG1

CLR

SIG0

CLR
LM1

CLR
LM0

SET_SIG1 Writing a 1 to this bit will set the SIG1 status bit.
SET_SIG0 Writing a 1 to this bit will set the SIG0 status bit.
SET_LM1 Writing a 1 to this bit will set the LM1 status bit.
SET_LM0 Writing a 1 to this bit will set the LM0 status bit.
CLR_SIG1Writing a 1 to this bit will clear the SIG1 status bit.
CLR_SIG0Writing a 1 to this bit will clear the SIG0 status bit.
CLR_LM1 Writing a 1 to this bit will clear the LM1 status bit.
CLR_LM0 Writing a 1 to this bit will clear the LM0 status bit.

1-38 Computer Group Literature Center Web Site

ISA Local Resource Bus

LM/SIG Status Register

The LM/SIG Status Registe r is an 8-bit regi ster located at ISA I/O address
x1001. This register, in conjunction with the LM/SIG Control Register,
provides a method to generate interrupts. The Universe ASIC is
programmed so that this register can be accessed from the VMEbus to
provide a capability to generate software interrupts to the onboard
processor(s) from the VMEbus.

REG LM/SIG Status Register - Offset $1001

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

1

FIELD EN

SIG1

OPER R/W READ-ONLY

RESET 0 0 0 0 0 0 0 0

EN

SIG0

EN

LM1

EN

LM0

SIG1 SIG0 LM1 LM0

EN_SIG1 When the EN_SIG1 bit is set, a LM/SIG Interrupt 1 is

generated if the SIG1 bit is asserted.

EN_SIG0 When the EN_SIG0 bit is set, a LM/SIG Interrupt 0 is

generated if the SIG0 bit is asserted.

EN_LM1 When the EN_LM1 bit is set, a LM/SIG Interrupt 1 is

generated and the LM1 bit is asserted.

EN_LM0 When the EN_LM0 bit is set, a LM/SIG Interrupt 0 is

generated and the LM0 bit is asserted.

SIG1 SIG1 status bit. This bit can only be set by the SET_LM1

control bit. It can onl y be cle ar ed by a reset or by writing
a 1 to the CLR_LM1 control bit.

SIG0 SIG0 status bit. This bit can only be set by the SET_LM0

control bit. It can onl y be cle ar ed by a reset or by writing
a 1 to the CLR_LM0 control bit.

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1

Board Description and Memory Maps

LM1 LM1 status bit. This bit can be set by either the location

monitor function or the SET_LM1 control bit. LM1
correspond to offset 3 from the location monitor base
address. This bit can only be cleared by a reset or by
writing a 1 to the CLR_LM1 control bit.

LM0 LM0 status bit. This bit can be set by either the location

monitor function or the SET_LM0 control bit. LM0
correspond to offset 1 from the location monitor base
address. This bit can only be cleared by a reset or by
writing a 1 to the CLR_LM0 control bit.

Location Monitor Upper Base Address Register

The Location Monitor Upper Base Address Register is an 8-bit register
located at ISA I/O address x1002. The Universe ASIC is programmed so
that this register can be accessed from the VMEbus to provide VMEbus
location monitor function.

REG Location Monitor Upper Base Address Register - Offset $1002

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

FIELD VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8

OPER R/W

RESET 0 0 0 0 0 0 0 0

VA[15:8] Upper Base Address for the location monitor function.

Location Monitor Lower Base Address Register

The Location Monitor Lower Base Address Register is an 8-bit register
located at ISA I/O address x1003. The Universe ASIC is programmed so
that this register can be accessed from the VMEbus to provide VMEbus
location monitor function.

REG Location Monitor Lower Base Address Register - Offset $1003

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

1-40 Computer Group Literature Center Web Site

ISA Local Resource Bus

REG Location Monitor Lower Base Address Register - Offset $1003

FIELD VA7 VA6 VA5 VA4 LMEN
OPER R/W R R R

RESET 0 0 0 0 0 0 0 0

VA[7:4] Lower Base Address for the location monitor function.
LMEN This bit must be set to enable the location monitor

function.

Semaphore Register 1

The Semaphore Register 1 is an 8-bit register located at ISA I/O address
x1004. The Universe ASIC is programmed so that this register can be
accessible from the VMEbus. This register can only be updated if bit 7 is
low or if the new value has the most significant bit cleared. When bit 7 is
high, this register will not latch in the new value if the new value has the
most significant bit set.

1

REG Semaphore Register 1 - Offset $1004

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
FIELD SEM1
OPER R/W

RESET 0 0 0 0 0 0 0 0

Semaphore Register 2

The Semaphore Register 2 is an 8-bit register located at ISA I/O address
x1005. The Universe ASIC is programmed so that this register can be
accessible from the VMEbus. This register can only be updated if bit 7 is

http://www.motorola.com/computer/literature 1-41

1

Board Description and Memory Maps

low or if the new value has the most significant bit cleared. When bit 7 is
high, this register will not latch in the new value if the new value has the
most significant bit set.

REG Semaphore Register 2 - Offset $1005

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

FIELD SEM2

OPER R/W

RESET 0 0 0 0 0 0 0 0

VME Geographical Address Register (VGAR)

The VME Geographical Address Register is an 8-bit read-only register
located at ISA I/O address x1006. This register reflects the states of the
geographical address pins at the 5-row, 160-pin P1 connector.

REG VME Geographical Address Register - Offset $1006

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

FIELD GAP# GA4# GA3# GA2# GA1# GA0#

OPER READ ONLY

RESET X X X X X X X X

1-42 Computer Group Literature Center Web Site

ISA Local Resource Bus

Z85230 ESCC and Z8536 CIO Registers and Port Pins

The Z85230 ESCC (Enhanced Serial Communication Controller) is used
to provide the two sync/async serial ports on MVME3600/ 4600 series
models. The PCLK (master clock input) which can be used to derive the
baud rates, is 10 MHz. Refer to the SCC User’s Man ual for programming
information on the Z85230 ESCC device.

The Z8536 CIO furnishes the modem control lines not provided by the
Z85230 ESCC and supplies a method to inqui re the modul e ID of the two
sync/async seria l port s that resi de o n the MVME76 1 module. Re fe r to th e
Z8536 Data Sheet for programming information.

Z8536/Z85230 Registers

Accesses to the Z8536 CIO and the Z85230 ESCC are accomplished via
Port Control and Port Data Registers. The PCLK to the Z8536 is 5 MHz.
Also, a Pseudo IACK Register is also de fined to retri eve int errup t vecto rs
from these devices. The Z8536 CIO has higher priority than the Z85230
ESCC in the in terrupt daisy c hain. The following table lists the registers
associated with accessing these two devices:

1

Table 1-20. Z8536/Z85230 Access Registers

PCI I/O Address Function

0000 0840 Z85230: Port B (Serial Port 4) Control
0000 0841 Z85230: Port B (Serial Port 4) Data
0000 0842 Z85230: Port A (Serial Port 3) Control
0000 0843 Z85230: Port A (Serial Port 3) Data
0000 0844 Z8536 CIO: Port C’s Data Register
0000 0845 Z8536 CIO: Port B’s Data Register
0000 0846 Z8536 CIO: Port A’s Data Register
0000 0847 Z8536 CIO: Control Register
0000 084F Z85230/Z8536 Pseudo IACK

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1

Board Description and Memory Maps

Z8536 CIO Port Pins

The assignment for the Port pins of the Z8536 CIO is as follows:

Table 1-21. Z8536 CIO Port Pins Assignment

Port

Pin

PA0 TM3_

PA1 DSR3_

PA2 RI3_ Input Port 3 Ring Indicator
PA3 LLB3_

PA4 RLB3_ Output Port 3 Remote Loopback
PA5 DTR3_ Output Port 3 Data Terminal Ready
PA6 BRDFAIL Output Board Fail: When set will cause FAIL LED to be lit.
PA7 IDREQ_ Output Module ID Request - low true
PB0 TM4_

PB1 DSR4_

Signal

Name

MID0

MID1

MODSEL

MID2

MID3

Direction Descriptions

Input Port 3 Test Mode when IDREQ_ = 1;

Module ID Bit 0 when IDREQ_ = 0.

Input Port 3 Data Set Ready when IDREQ_ = 1;

Module ID Bit 1 when IDREQ_ = 0.

Output Port 3 Local Loopback (IDREQ_ = 1) or

Port Select (IDREQ_ = 0):

IDREQ_ = 0 & MODSEL = 0 => Port 3 ID Select
IDREQ_ = 0 & MODSEL = 1 => Port 4 ID Select

Input Port 4 Test Mode when IDREQ_ = 1;

Module ID Bit 2 when IDREQ_ = 0.

Input Port 4 Data Set Ready when IDREQ_ = 1;

Module ID Bit 3 when IDREQ_ = 0.

PB2 RI4_ Input Port 4 Ring Indicator
PB3 LLB4_ Output Port 4 Local Loopback
PB4 RLB4_ Output Port 4 Remote Loopback
PB5 DTR4_ Output Port 4 Data Terminal Ready
PB6 FUSE Input FUSE = 1 means that at least one of the fuses or

polyswitches is open.

PB7 ABORT_ Input Status of ABORT# signal

1-44 Computer Group Literature Center Web Site

ISA Local Resource Bus

Table 1-21. Z8536 CIO Port Pins Assignment (Continued)

1

Port

Pin

PC0 Reserved I/O Reserved
PC1 Reserved I/O Reserved
PC2 Reserved I/O Reserved
PC3 Reserved I/O

Signal
Name

Direction Descriptions

Note The direction and the polarity of the Z8536’s port pins are

software programmable.

The module ID signals, which are only valid when IDREQ_ is asserted,
indicate the type of the serial module that is installed on either Port 3 or
Port 4. The following table shows how to interpret the MID3-MID0
signals:

Table 1-22. Interpretati on of MI D3-MID0

MID3

MID2

MID1

MID0

IDREQ_

LLB3_

MODSEL

Serial Module Type

Module

Assembly

Number

1 X XXXXInvalid module ID
0 0 0000Module 3: EIA232 DCE 01-W3876B01
0 0 0001Module 3: EIA232 DTE 01-W3877B01
0 0 0010Module 3: EIA530 DCE 01-W3878B01
0 0 0011Module 3: EIA530 DTE 01-W3879B01
0 0 1111Module 3 Not Installed
0 1 0000Module 4: EIA232 DCE 01-W3876B01
0 1 0001Module 4: EIA232 DTE 01-W3877B01
0 1 0010Module 4: EIA530 DCE 01-W3878B01

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1

Board Description and Memory Maps

Table 1-22. Interpretation of MID3-MID0 (Continued)

MID3

MID2

MID1

IDREQ_

0 1 0011Module 4: EIA530 DTE 01-W3879B01
0 1 1111Module 4 Not Installed

LLB3_

MODSEL

MID0

Serial Module Type

Module

Assembly

Number

Note Because IDREQ_ and MID3-MID0 signals go through the

P2MX (P2 multiplexing) function used on MVME3600/4600
series modules configured for the MVME761-type transition
module, software must wait for the MID3-MID0 to become valid
after asserting IDREQ_. The waiting time should be about 4
microseconds because the sa mpling rate is about 1.6 microsecond
with a 10 MHz MXCLK clock.

ISA DMA Channels

There are seven ISA DMA channels in the PIB. Channels 0 through 3
support only 8-bit DMA devices whi le Channels 5 through 7 suppor t only
16-bit DMA devices. These DMA channels are assigned as follows:

1-46 Computer Group Literature Center Web Site

ISA Local Resource Bus

Table 1-23. PIB DMA Channel Assignments

1

PIB

Priority

Highest Channel 0 DMA1 Serial Port 3 Receiver (Z85230 Port A Rx)

Lowest Channel 7 Not Used

PIB Label Controller DMA Assignment

Channel 1 Serial Port 3 Transmitter (Z85230 Port A Tx)

Channel 2 Floppy Drive Controller

Channel 3 Parallel Port
Channel 4 DMA2 Not available - Cascaded from DMA1

Channel 5 Serial Port 4 Receiver (Z85230 Port B Rx)

Channel 6 Serial Port 4 Transmitter (Z85230 Port B Tx)

Note Because the Z85230 is an 8-bit device and Channels 5 and 6 are

16-bit DMA Channels, only every other byte (the even bytes)
from memory is val id .

http://www.motorola.com/computer/literature 1-47

2Raven PCI Host Bridge & Multi-Processor

Interrupt Controller Chip

Introduction

This chapter describes the architecture and usage of the Raven, a Power PC
to PCI Local Bus Bridge ASIC. The Raven is intended to provide
PowerPC 60x (MPC60x) compliant devices access to devices residing on
the PCI Local Bus. In the remainder of this chapter, the MPC60x bus will
be referred to as t he MPC bus an d the PCI Loca l Bus as PCI. PCI is a hi gh
performance 32-bit or 64-bit, burst mode, synchronous bus capable of
transfer rates of 1 32MB/s ec i n 32-bit mode or 264MB/sec in 6 4-bi t mode
using a 33 MHz clock.

Summary of Features

The following table summarizes th e characteri stics of the Raven PCI Host
Bridge.

Function Features

MPC Bus Interface Direct interface to MPC603 or MPC604 processors

64-bit data bus, 32-bit address bus
Four independent software programmable slave map decoders
Multi-level write post FIFO for writes to PCI
Support for MPC bus clock speeds up to 66 MHz
Selectable big or little-endian operation

3.3 V signal levels

PCI Interface Fully PCI Rev. 2.0 compliant

32-bit or 64-bit address/data bus
Support for accesses to all four PCI address spaces
Single-level write posting buffers for writes to the MPC bus
Read-ahead buffer for reads from the MPC bus
Four independent software programmable slave map decoders
5V tolerant I/O accommodates 3.3V or 5 V signal levels

2

2-1

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

Interrupt Controller MPIC compliant

Function Features

Support for 16 external interrupt sources and two processors
Multiprocessor interrupt control allowing any interrupt sou rce to

be directed to either processor
Multilevel cross processor interrupt control for multiprocessor

synchronization
Four 31-bit tick timers
Two 64-bit general purpose registers for cross-processor

messaging

Block Diagram

Figure 2-1 for a block diagram of the Raven ASIC.

See

2-2 Computer Group Literature Center Web Site

http://www.motorola.com/computer/literature 2-3

PCI Bus

Raven

PCI Slave

MPIC

PCI Dec

PCI Master

Figure 2-1. Raven Block Diagram

1914 9702

MPC Slave

PCIADIN

Reg

MPCADIN

Reg

MPC Dec

Mux

Mux

PCI Regs

Data Path ‘A’

Endian

Data Path ‘B’

Endian

MPC Regs

MPC Bus

FIFO

FIFO

Mux PCI

Mux

Mux MPC

Mux

MPC Master

Reg

Reg

Introduction

2

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

Functional Description

The Raven control logic is subdivided into the following functions: PCI
slave, PCI master, MPC slave and M PC master. The Raven dat a path logic
is subdivided into the following functions: Data Path ‘A’ FIFOs/muxes,
Data Path ‘B’ FIFOs/muxes, PCIADIN, MPCADIN, Mux PCI, and Mux
MPC. Address decoding is handled in the PCI Decode and MPC Decode
blocks. The control register logic is contained in the PCI Registers and
MPC Registers blocks. The interrupt controller (RavenMPIC) and the
MPC arbiter functions make up the remainder of the Raven design.

The data path function imposes some restrictions on access to the
RavenMPIC, the PCI Register s, and the MPC Regi sters. Th e RavenMPIC
and the PCI Registers are only accessible to PCI-originated transactions.
The MPC Registers are only accessible to MPC-originated transactions.

MPC Bus Interface

The MPC Bus Interface is designed to be coupled directly to up to two
MPC603 or MPC604 microprocessors as well as a memory/cache
subsystem. It uses a subset o f the capa biliti es of th e MPC60 x bus pr otocol.

MPC Address Mapping

The Raven will map either PCI memory spac e or PCI I/O space into MPC
address space using four programmable map decoders. These decoders
provide windows into t he PCI bus from t he MPC bus. The mos t significant
16 bits of the MPC address are compared with the address range of each
map decoder, and if the ad dress fal ls within the s pecified ran ge, the acces s
is passed on to PCI. An example of this is shown in

2-4 Computer Group Literature Center Web Site

Figure 2-2.

MPC Bus Address

8

0801234

16150

>= <=andDecode is

Functional Description

2

31

MSADDx Register

0809000

7

16150

31

Figure 2-2. MPC to PCI Address Decoding

There are no limits impo sed by Raven on how large of an address spac e a
map decoder can represent. There is a lower limit of a m in im um of 64KB
due to the resolution of the address compare logic.

For each map, there is an associated set of attributes. These attributes are
used to enable read accesses, enable write accesses, enable write posting,
and define the PCI transfer characteristics.

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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

offset is added to t he 16 most s ignif icant bit s of the MPC addre ss, and the
result is used as the PCI address. This offset allows PCI devices to reside
at any PCI address, independent of the MPC addre ss map. An example of
this is shown below.

Each map decoder also inc ludes a programmable 16-bi t address offset. The

MPC Bus Address

MSOFFx Register

PCI Bus Address

0801234

8

+

9

000

=

1

0801234

16150

150

151631

31

0

Figure 2-3. MPC to PCI Address Translation

Care should be taken to assure that all programmable decoders decode
unique address ranges since overlapping address ranges will lead to
undefined operation.

MPC Slave

The MPC slave provides the interface between the MPC bus and the Raven
FIFOs. The MPC slave is responsible for tracking and maintaining
coherency to the 60x processor bus protocol.

The MPC slave divides MPC command types into three categories:
address only, write, and read. If a co mmand type is an addr ess only and th e
address presented at the time of the command is a valid Raven ad dress, the

2-6 Computer Group Literature Center Web Site

Functional Description

MPC slave will respond immediately. The Raven will not respond to
address only cycles where the address presented is not a Raven address.
The response of the MPC slave to command types is listed in

Table 2-1. MPC Slave Response Command Types

MPC Transfer Type Transfer

Encoding

Clean Block 00000 Addr Only
Flush Block 00100 Addr Only
SYNC 01000 Addr Only
Kill Block 01100 Addr Only
EIEIO 10000 Addr Only
ECOWX 10100 No Response
TLB Invalidate 11000 Addr Only
ECIWX 11100 No Response
LWARX 00001 Addr Only
STWCX 00101 Addr Only
TLBSYNC 01001 Addr Only
ICBI 01101 Addr Only
Reserved 1XX01 No Response
Write-with-flush 00010 Write
Write-with-kill 00110 Write
Read 01010 Read
Read-with-intent-to-modify 01110 Read
Write-with-flush-atomic 10010 Write
Reserved 10110 No Response
Read-atomic 11010 Read
Read-with-intent-to-modify-atomic 11110 Read
Reserved 00011 No Response
Reserved 00111 No Response
Read-with-no-intent-to-cache 01011 Read
Reserved 01111 No Response
Reserved 1xx11 No Response

Transaction

2

Table 2-1.

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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

MPC Write Posting

The MPC writ e FIFO stores up to eight data beats in any combination of
single- and four-beat (b urst) transactions. If writ e posting is e nabled,
Raven stores the data necess ary to co mplete an MPC write transfer to the
PCI bus and immediately acknowledges the transaction on the MPC bus.
This frees the MPC bus from waiting for the potentially long PCI
arbitration and transfer. The MPC bus may be used for more useful work
while the Raven manages the completi on of the write posted transaction on
PCI.

All transactions will be completed on the PCI bus in the same order that
they are completed on the MPC bus. A read or a compelled write
transaction will force all previously issued write posted transactions to be
flushed from the FIFO. All write posted transfers will be completed before
a non-write posted read or write is begun, to assure that all transfers are
completed in the order issued. All write posted transfers will also be
completed before any access to the Raven’s registers is begun.

MPC Master

The MPC master will att empt to move d ata using burst trans fers wher ever
possible. A 64-bit by 16 entry FIFO is used to hold data between the PCI
slave and the MPC master to ensure that optimum data throughput is
maintained. While the PCI slave is filling the FIFO with one cache line
worth of data, the MPC master can be moving another cache line worth
onto the MPC bus. This will allow the PCI slave to receive long block
transfers without stalling.

When programmed in “read ahead” mode (the RAEN bit in the PSATTx
register is set) and the PCI slave rec eives a Memory Read Li ne or Memory
Read Multiple command, the MPC master will fetch data in bursts and
store it in the FI FO. The con tents of th e FIFO wil l th en be us ed to att empt
to satisfy the data requirements for the remainder of the PCI block
transaction. If the data requested is not in the FIFO, the MPC master will
read another cache lin e. The cont ent s of the FIFO are “invalid ate d” a t t he
end of each PCI block transaction.

2-8 Computer Group Literature Center Web Site

Functional Description

Notes

1. Read ahead mode should not be used when data coherency may be
a problem, as there is no way to sn oop all MPC bus transactions and
invalidate the contents of the FIFO.

2. Accesse s near the top of local memory with read-ahead mode
enabled could cause the MPC master to perform reads beyond the
top of local memory which could result in an MPC bus timeout
error.

The MPC bus transfer types generated by the MPC master depend on the
PCI command code and the INV/GBL bits in the PSATTx registers. The
GBL bit determines whether or not the GBL* signal is asserte d for all
portions of a transaction, and is fully independent of the PCI command
code and INV bit.

Table 2-2 shows the relationship betwee n PCI command

codes and the INV bit.

Table 2-2. MPC Transfer Types

PCI Command Code INV MPC Transfer Type MPC Transfer Size TT0-TT4

Memory Read
Memory Read Multiple
Memory Read Line

0 Read Burst/Single Beat 01010

2

Memory Read
Memory Read Multiple
Memory Read Line

Memory Write
Memory Write and

Invalidate
Memory Write

Memory Write and
Invalidate

1 Read With Intent to

Modify

x Write with Kill Burst 00110

x Write with Flush Single Beat 00010

Burst/Single Beat 01110

The MPC master incorporate s an optional operating mode cal led Bus Hog.
When Bus Hog is enabled, the MPC master will continually request the
MPC bus for the entire dura tion of each PCI transfer. When Bus Hog is not

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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

MPC Arbiter

MPC Bus Timer

enabled, the MPC master will structure i ts bus request actions acco rding to
the requirements of the FIFO. Caution should be exerci sed when using this
mode since the over-generosity of bus ownership to the MPC master can
be detrimental to th e host CP U’s p erforma nce. The Bus Hog mode c an be
controlled by the BHOG bi t within the GCSR. T he default sta te for BHOG
is disabled.

The MPC Arbiter is an optional fe ature in the Raven, and is not used on the
MVME3600. Arbitration for the MPC bus on the MVME3600 is
performed external to the Raven.

The MPC bus timer allows t he current bus master to recover from a lock­up condition caused when no slave responds to the transfer request.

The time-out length of the bus timer i s determined by t he MBT field in th e
Global Control/Status Register.

The bus timer starts ticking at the beginning of an address transfer (TS*
asserted), and if the address transfer is not terminated (AACK* asserted)
before the time -out period h as passed, the Raven will a ssert the M ATO bit
in the MPC Error Status Register, latch the MPC address in the MPC Error
Address Register, and then terminate the c cycle.

The MATO bit may be configured to generate an interrupt or a machine
check through the MEREN register.

The timer is disabled if the transfer is intended for PCI. PCI bound
transfers will be timed by the PCI master.

PCI Interface

The Raven PCI Interface is designed to connect directly to a PCI Local
Bus, and supports Master and Target transactions within Memory Space,
I/O Space, and Configuration Space.

2-10 Computer Group Literature Center Web Site

Functional Description

The PCI interface may operate at any clock speed up to 33 MHz. The
PCLK input must be externally synchronized with the MCLK input, and
the frequency of the PCLK input must be exactly hal f the frequency of the
MCLK input.

PCI Address Mapping

Raven provides three resources to PCI:

❏ Configuration registers mapped into PCI Configuration space
❏ MPC bus address space mapped into PCI Memory space
❏ RavenMPIC control registers mapped into either PCI I/O space or

PCI Memory space

Configuration Registers:

The Raven does not have an IDSEL pin. An internal connection is made
within the Raven that logi cally assoc iates the assert ion o f IDSEL wi th the
assertion of AD31.

Raven provides a configura tion spa ce th at is ful ly complia nt with the PCI
Local Bus Specification 2.0 definition for configuration space. There are
two base registers within the standard 64-byte header that are used to
control the mapping of Rave nMPIC. One regis ter is dedic ated to ma pping
RavenMPIC into PCI I/O space, and the other register is dedicated to
mapping RavenMPIC into PCI Memory space. The mapping of MPC
address space i s h andled by device s peci f ic registers located above the 64
byte header. These control registers support a mapping scheme that is
functionally similar to the PCI-to-MPC mapping scheme described in

MPC Address Mapping on page 2-4.

2

MPC Bus Address Space:

The Raven will map MPC address space into PCI Memory space using
four programmable map deco ders. The most sign ific ant 16 bits of t he PCI
address is compare d with the address ra nge of each map decoder , and if the
address falls withi n the specified range, the acce ss is passed on to the MPC
bus. An example of this is shown in

http://www.motorola.com/computer/literature 2-11

Figure 2-4.

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

PCI Bus Address 8 0801234

151631

0

>= <=andDecode is

PSADDx Register

7

0809000

151631

0

Figure 2-4. PCI to MPC Address Decoding

There are no limits impo sed by Raven on how large of an address spac e a
map decoder can represent. There is a lower limit of a m in im um of 64KB
due to the resolution of the address compare logic.

For each map, there is an independent set of attrib utes. These attr ibutes are
used to enable read accesses, enable write accesses, enable write posting,
and define the MPC bus transfer characteristics.

2-12 Computer Group Literature Center Web Site

Functional Description

Each map decoder also inc ludes a programmable 16-bi t address offset. The
offset is added to the 16 most significant bits of the PCI address, and the
result is used as the MPC address. This offset allows devices to reside at
any MPC address, independent of the PCI address map. An example of this
is show below.

PCI Bus Address 8 0801234

+

PSOFFx Register

000

9

=

MPC Bus Address

1

0801234

151631

1631

16150

0

31

Figure 2-5. PCI to MPC Address Translation

2

All Raven address decoders are prioritized so that programming multiple
decoders to respond to the same address is not a problem. When the PCI
address falls into the range of more than one decoder, only the highest
priority one will respond. The decoders are prioritized as shown below.

Decoder Priority

PCI Slave 0 highest
PCI Slave 1
PCI Slave 2
PCI Slave 3 lowest

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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

RavenMPIC Control Registers:

The RavenMPIC control registers are located within either PCI Memory
or PCI I/O space using traditional PCI defined base registers within the

Raven Interrupt Controller

PCI Slave

predefined 64-byte header. Please see

Implementation

The PCI slave provides the c ontrol logic need ed to interface the PCI bus to
Raven’s FIFOs. The PCI slave can accept either 32-bit or 64-bit
transactions, however it can only accept 32-bit addressing. There is no
limit to the length of the transfer tha t the slav e can hand le. During posted
write cycles, the slave will contin ue to accept write data until the wri te post
FIFO is full. If the write post FIFO is full, the slave will hold off the master
with wait states until there is more room in the FIFO. The slave will not
initiate a disconnect. If the write transaction is compelled, the slave will
hold off the master with wait states while each beat of data is being
transferred. The slave will acknowledge the completion of the transfer
only after the data tra nsf er ha s succ essfu lly compl eted on the MPC bu s. If
a read transaction is being performed within an address space marked for
prefetching, the slave (in conjunction with the MPC master) will attempt
to read ahead far enough on the MPC bus to allow for an uninterrupted
burst transaction on the PCI bus. Read transactions within address spaces
marked for no prefetchin g will be acknowle dged on the PCI bus onl y after
a single beat read has successfully completed on the MPC bus. Each read
on the MPC bus will only be started after the previous read has been
acknowledged on the PCI bus and there is an indication tha t the PCI master
wishes for mo re data to be tran sferred.

on page 2-59 for more information.

The following paragraphs identify some associations between the
operation of the PCI slave and the PCI 2.0 Local Bus Specification
requirements.

2-14 Computer Group Literature Center Web Site

Functional Description

Command Types:

The table below shows which types of PCI cycles the slave has been
designed to accept.

Table 2-3. PCI Slave Response Command Types

Command Type Slave Response?

Interrupt Acknowledge No
Special Cycle No
I/O Read Yes
I/O Write Yes
Reserved No
Reserved No
Memory Read Yes
Memory Write Yes
Reserved No
Reserved No
Configuration Read Yes
Configuration Write Yes
Memory Read Multiple Yes
Dual Address Cycle No
Memory Read Line Yes
Memory Write and

Invalidate

Yes

2

Addressing:

The slave will acce pt any combination of byte enable s during read or wr ite
cycles. During write cycles, a discontinuity (for example, a ‘hole’) in the
byte enables will force the slave to issue a disconnect. During all read
cycles, the s lave will return an entire word of data regardless of the byte
enables. During I/O read cyc les, th e slave will per form integr ity che cking
of the byte enables against the address being presented and assert SERR*
in the event there is an error.

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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

The slave will only honor the Linear Incrementing addressing mode. The
slave will perform a disconnect wit h data if any other mode of address ing
is attempted.

Device Selection:

The PCI slave will always respond valid decoded cycles as a medium
responder.

Target Initiated Termination:

The PCI slave normally strives to complete transactions without issuing
disconnects or retries. One exception is where the slave is performing
configuration cycles. All configuration cycles will be terminated with a
disconnect after one data beat has been transferred. Another exception is
the issue of a disconnect when asked to perform a transaction with byte
enable ‘holes’.

Fast Back-to-Back Transactions:

The PCI slave supports both of the fundamental target requirements for
fast back-to-back transactions. The PCI slave meets the first criteria of
being able to successfully track the state of the PCI bus without the
existence of an IDLE state between transactions. The second criteria
associate with signal turn-around timing is met by default since the slave
functions as a medium responder.

Latency:

The PCI slave does not have any hardware mechanisms in place to
guarantee that the initial and subsequent target latency requirements are
met. Typically this is not a problem since the bandwidth of the MPC bus
far exceeds the bandwidth of the PCI bus. The Raven MPC arbiter has been
designed to give t he highest priorit y for it’s own tra nsactions which furt her
reduces PCI bus latency.

Exclusive Access:

The PCI slave has no mechanism to support exclusive access.

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Functional Description

Parity:

The PCI slave supports address parity error detection, data parity
generation and data par ity error detec tion.

Cache Support:

The PCI slave does not participate in the PCI caching protocol.

PCI Write Posting

If write posting is enabled, the Raven sto res the ta rge t addr es s, att ri but es ,
and up to 128 bytes of data from one PCI write transaction and
immediately acknowled ges the transaction on the PCI bus. This allows t he
slower PCI to continue to transfer data at its maximum bandwidth, and the
faster MPC bus to accept data in high performance cache-line burst
transfers.

Only one PCI transaction may be write posted at any given time. If the
Raven is busy processing a previous write posted tra nsaction when a new
PCI transaction begi ns, t he next PCI transaction will be de la yed ( T RDY*
will not be asserte d) until the previou s transaction has compl eted. If during
a transaction the write post buffer gets full, subsequent PCI data transfers
will be delayed (TRDY* will not be asserted ) until the Raven has r emoved
some data from the FIFO. Under normal conditions, the Raven should be
able to empty the FIFO faster than the PCI bus can fill it.

2

PCI Configuration cy cles intended for internal Ra ven registers will also be
delayed if Raven is busy so that co ntrol bits which may affect writ e posting
do not change until all write posted transactions have completed.

PCI Master

The PCI master, in conju nction with the cap abilities of the MPC s lave, will
attempt to move data in either single- beat or four-bea t (burst) trans actions.
All single-beat transactions will be subdivided into one or two 32-bit
transfers, depen ding on the align ment and siz e of the t ransa ction. The P CI
master will attempt to transfer all four-beat transactions in 64-bit mode if
the PCI bus has 64 -bit mode e nabled . If at an y time d uring t he tr ans acti on
the PCI target indicates it can not support 64-bi t mode, the PCI master will
continue to transfer the remaining data in 32-bit mode.

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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

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PCI master will divide this transaction into two parts. The first part will
start on the add ress presen ted with t he CWF trans fe r requ est an d cont inue
up to the end of the curr ent cache l ine. The secon d trans fer will s tart at th e
beginning of the associated cache line and work its way up to (but not
including) the word addressed by the CWF request.

It should be noted that even though the master can support burst
transactions, a majority of the transaction types handled are single-beat
transfers. Typically PCI space is not configured as cacheable, therefore
burst transactions to PCI space would not naturally occur. It must be
supported since it is concei vable that burst ing could happen. For example,
nothing prevents the pr ocessor from loading up a ca che line with PCI write
data and manually flushing the cache line.

The following paragraphs identify some associations between the
operation of the PCI master and the PCI 2.0 Local Bus Specification
requirements.

Command Types:

The PCI Command Codes generat ed by the PCI master d epend on the type

The PCI master can support Crit ical Word First (CWF) burst tra nsfers. The

of transaction bein g performed on the MPC bus. Ple ase refer to

MPC Slav e

on page 2-6 for a further descri ption of M PC bus re ad and MPC bus wri te.
Table 2-4 summarizes the command types supported and how they are

generated.

Table 2-4. PCI Master Command Codes

Entity Addressed MPC

Trans fer Type

PIACK Read x x 0000 Interrupt Acknowledge
CONADD/CONDAT Write x x 0001 Special Cycle
MPC Mapped PCI Space Read x 0 0010 I/O Read

Write x 0 0011 I/O Write

-- Unsupported -- 0100 Reserved

-- Unsupported -- 0101 Reserved

MPC Mapped PCI Space Read 1 1 0110 Memory Read

Write x 1 0111 Memory Write

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TBST* MEM C/BE PCI Command

Functional Description

Table 2-4. PCI Master Command Codes (Continued)

Entity Addressed MPC

Trans fer Type

-- Unsupported -- 1000 Reserved

-- Unsupported -- 1001 Reserved
CONADD/CONDAT Read x x 1010 Configuration Read
CONADD/CONDAT Write x x 1011 Configuration Write

-- Unsupported -- 1100 Memory Read

-- Unsupported -- 1101 Dual Address Cycle
MPC Mapped PCI Space Read 0 1 1110 Memory Read Line

-- Unsupported -- 1111 Memory Write and

TBST* MEM C/BE PCI Command

Multiple

Invalidate

Addressing:

The PCI maste r will generate all memory transa ctions using the linear
incrementing addressing mode.

Combining, Merging, and Collapsing:

The PCI master does not participate in any of these protocols.

2

Master Initiated Termination:

The PCI master can handle any defined method of target retry, target
disconnect, or target abort. If the target responds with a retry, the PCI
master will wait for the required two clock periods and attempt the
transaction again. This will continue indefinitely until the transaction has
completed, the transaction is aborted by the target, or if the transaction is
aborted due to a Raven detected bridge lock. The same happens if the
target responds with a disconnect and there is still data to be transferred.

If the PCI master detects a target abort during a read, any untransferred
read data will be filled with ones. If the PCI master detects a target abort
during a write, any untransferred portions of data will be dropped. The
same rule applies if the PCI master generates a Master Abort cycle.

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Arbitration:

The PCI master can support pa rking on the PCI bus. If the PCI ma ster starts
a transaction tha t is goi ng to take more than one b eat , the PCI m as ter will
continuously asse rt its request u ntil the transac tion has complete d. The one
exception is when the PCI master receives a disconnect or a retry.

Fast Back-to-Back Transactions:

The PCI master does not generate fast back-to-back transactions.

Arbitrat ion Latency:

Because a bulk of the transactions are limited to single-beat transfers on
PCI, the PCI master does not implement a Master Latency Timer.

Exclusive Access:

The PCI master is not able to initiate exclusive access transactions.

Address/Data Stepping:

The PCI master does not participate in the Address/Data Stepping
protocol.

Parity:

The PCI master supports address par ity generation , data parit y generation,
and data parity error detection.

Cache Support:

The PCI master does not participate in the PCI caching protocol.

Generating PCI Cycles

There are four basic types of bus cycles that can be generated on the PCI
bus:

❏ Memory and I/O
❏ Configuration
❏ Special Cycle

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Functional Description

❏ Interrupt Acknowledge

Generating PCI Memory and I/O Cycles

Each programmable slave may be configured to generate PCI I/O or
memory accesses th rough the MEM and IOM fiel ds in its Attribute re gister
as shown below.

MEM IOM PCI Cycle Type

1xMemory
0 0 Contiguous I/O
0 1 Spread I/O

If the MEM bit is set, the Raven will perform Memory addressing on the
PCI bus. The Raven will take the MPC bus address, apply the offset
specified in the MSOFFx register, and map the result directly to the PCI
bus.

The IBM CHRP specification describes two approa che s f or handling PCI
I/O addressing: contiguous or spread address modes. When the MEM bit
is cleared, the IOM bit is used to sele ct between these two modes whenever
a PCI I/O cycle is to be perfor m ed.

2

The Raven will perform contiguous I/O addressing when the MEM bit is
clear and the IOM bit is clear. The Raven will take the MPC address, apply
the offset specified in the MSOFFx register , and map the result directly to
PCI.

The Raven will perfor m sprea d I/O a ddress ing when th e MEM bi t is clear
and the IOM bit is set. The Raven will take the MPC address, apply the
offset specified in the M SOFFx register, and map the result to PCI as
shown in Figure 2-6.

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MPC Address + Offset

31 12 11 5 4 0

31 0

0 0 0 0 0 0 0

0000000

PCI Address

25 24

54

1915 9702

Figure 2-6. PCI Spread I/O Address Translation

Spread I/O addressing allows each PCI device’s I/O registers to reside on
a different MPC memory page, so device drivers can be protected from
each other using memory page protection.

All I/O accesses must be performed within natural word boundari es. Any
I/O access that is not contai ned within a nat ural word boun dary will resul t
in unpredictable operation. For example, an I/O transfer of four bytes
starting at address $80000010 is considered a valid transfer. An I/O
transfer of four bytes starting at address $80000011 is considered an
invalid transfer since it crosses the natural word boundary at address
$80000013/$80000014.

Generating PCI Configuration Cycles

The Raven uses configuration mechanism #1 as defined in the PCI Local
Bus Specificati on 2.0 t o gene rate conf igu ratio n cyc les. Ple ase r efer to this
specification for a complete description of this function.

Configuration mechanism #1 use s an address register /data register for mat.
Performing a configur ation acce ss is a two step process . The first st ep is to
place the address of the configuration cycle within the
CONFIG_ADDRESS register. Note th at this acti on does not generate a ny
cycles on the PCI bus. The second step is to either read or write

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Functional Description

configuration data into the CONFIG_DATA register. If the
CONFIG_ADDRESS register has been set up correctly, the Raven will
pass this access on to the PCI bus as a configuration cycle.

The addresses of the CONFIG_ADDRESS and CONFIG_DATA registe rs
are actually embedded withi n PCI I /O space. If the CONFIG_ADDRESS
register has been set incorrectly or the access to either the
CONFIG_ADDRESS or CONFIG_DATA register is not 1,2, or 4 bytes
wide, the Raven will pass the access on to PCI as a normal I/O Space
transfer.

The CONFIG_ADDRESS register is located at offset $CF8 from the
bottom of PCI I/O space. The CONFI G_DATA register is l ocated at offset
$CFC from the bottom of PCI I/ O space . The Raven add ress decod e logi c
has been designed such that MSADD3 and MSOFF3 must be used for
mapping to PCI Configuration (consequently I/O) space. The
MSADD3/MSOFF3 register group is initialized at reset to allow PCI I/O
access starting at address $800 00000. The powerup location ( for example,
little-endian disabl ed) of the CONFIG_ADDRES S register is $800 00CF8,
and the CONFIG_DATA register is located at $80000CFC.

The CONFIG_ADDRESS register must be prefilled with four fields: the
Register Number, the Funct ion Number, th e Device Number , and the Bus
Number.

2

The Register Number and the Function Number get passed along to the
PCI bus as portion of the lower address bits.

When performing a configur at ion cycle, Raven uses the uppe r 20 address
bits as IDSEL lines. During the address phase of a configuration cycle,
only one of the upper addre ss bits will be set. The device that ha s its IDSEL
connected to the address bit being asserted will be selected for a

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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

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which of the upper address lines to assert. The decoding of the five-bit
Device Number is show as follows:

configuration cycle. Raven decodes the Device Number to determine

Device Number Address Bit

00000 AD31

00001 - 01010 All Zeros

01011 AD11
01100 AD12

(etc.) (etc.)
11101 AD29
11110 AD30
11111 All Zeros

The Bus Number determines which bus is the target for the configuration
read cycle. Raven will always host PCI bus #0. Accesses that are to be
performed on the PCI bus connected to the Raven must have zero
programmed into the Bus Number. If the configuration access is targeted
for another PCI bus, th en that bus numbe r shoul d be pr ogrammed i nto th e
Bus Number field. The Raven will det ect a non- zero fiel d and conve rt the
transaction to a Type 1 Configuration cycle.

Generating PCI Special Cycles

Raven supports the method sta ted in PCI Local Bus Specificatio n 2.0 using
Configuration Mechanism #1 to generate special cycles. To prime Raven
for a special cycle, the host processor must write a 32 bit value to the
CONFIG_ADDRESS register. The contents of the write are defined later
in this chapter under the CONFIG_ADDRESS register definition. After
the write to CONFIG_ADDRESS has been accomplished, the next write
to the CONFIG_DATA register causes the Raven to generate a special
cycle on the PCI bus. The write data is driven onto AD[31:0] during the
special cycle’s data phase.

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Functional Description

Generating PCI Interrupt Acknowledge Cycles

Performing a read from the PIACK register will initiate a single PCI
Interrupt Acknowledge cycle. Any single byte or combination of bytes
may be read from, and the act ual byte enable pat te rn used during the re ad
will be passed on to the PCI bus. Upon completion of the PCI interrupt
acknowledge cycle, the Raven will p resent the result ing vector inform ation
obtained from the PCI bus as read data.

Endian Conversion

The Raven supports both bi g- and little-end ian data formats . Since the PCI
bus is inherently little-endian, conversion is necessary if all MPC devices
are configured for big-endian operation. The Raven may be programmed
to perform the endian conversion described below.

When MPC Devices are Big-Endian

When all MPC devices are oper ating in big -endia n mode, al l data to/fro m
the PCI bus must be swapped s uch that t he PCI bus lo oks big-en dian from
the MPC bus’s perspective. This association is true regardless of whether
the transaction ori ginates on the PCI bus or the MPC bus. This is shown in

Figure 2-7.

2

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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

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DH07-00

DH15-08

DH23-16

DH31-24DL07-00

D0 D1 D2 D3 D4 D5 D6 D7

DL15-08

DL23-16

DL31-24

PPC Bus

D7 D6 D5 D4 D3 D2 D1 D0

AD31-24

AD23-16

AD15-08

DL23-16

AD07-00

DL31-24

AD63-56

AD55-48

AD47-40

AD39-32

DH07-00

DH15-08

DH23-16

DH31-24

DL07-00

DL15-08

D0 D1 D2 D3 D4 D5 D6 D7

D7 D6 D5 D4
D3 D2 D1 D0

AD31-24

AD23-16

AD15-08

32-bit PCI

AD07-00

Figure 2-7. Big to Little-Endian Data Swap

64-bit PCI

PPC Bus

1916 9610

When MPC Devices are Little-Endian

When all MPC devices are operat ing in little- endian mode, the or iginating
address is modified to remove the exclusive-ORing applied by MPC60x
processors before being passed on to the PCI bus. Note that no data
swapping is performed. Address modification happens to the originating
address regardless of whether the transaction originates from the PCI bus

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Functional Description

or the MPC bus. The t hree low or der address bits are exc lusive-ORed wi th
a three-bit value that depends on the length of the operand, as shown
below.

Table 2-5. Address Modification for Little-Endian Transfers

Data Length

(bytes)

1 XOR with 111
2 XOR with 110
4 XOR with 100
8 no change

Address Modification

Note The only legal data lengths su pported in little-e ndian mode are 1,

2, 4, or 8-byte aligned transfers.

Since this method has some difficulties dealing with unaligned PCI­originated transfers, the Raven MPC master will break up all unaligned
PCI transfers into multiple aligned PCI transfers into multiple aligned
transfers on the MPC bus.

2

Raven Registers

The Raven registers are not sensitive to changes in big-endian and
little-endian mode. With re spect to the MPC bus (but not always the
address internal to the processor), the MPC registers are always
represented in big-endian mode. This means that the processor’s internal
view of the MPC registers wi ll appear diff erent dependi ng on which mode
the processor is operating in.

With respect to the PCI bus, the RavenMPIC registers and the
configuration registers are always represented in little-endian mode.

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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

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represented in PCI space to the processor and are subject to the endian
functions. For example, the power up location of the CONFIG_ADDRESS
register with respect to the MPC bus is $80000cf8 when Raven is in big­endian mode. When Raven is switched to little-endian mode, the
CONFIG_ADDRESS register with respect to the MPC bus is $80000cfc.
Note that in both ca ses the a ddress gene rated in terna l to the pr ocessor wi ll
be $80000cf8.

The contents of the CONFIG_ADDRESS register are not subject to the
endian function.

The data associated with PIACK accesses is subject to the endian
swapping function. The addr ess of a PIACK cycle is undefined, therefore
address modification during little-endian mode is not an issue.

Error Handling

The Raven will be capable of de tecti ng and re porti ng the f ollowi ng error s
to one or more MPC masters:

❏ MPC address bus time-out
❏ PCI master signalled master abort

The CONFIG_ADDRESS and CONFIG_DATA registers are actually

❏ PCI master received target abort
❏ PCI parity er ror
❏ PCI system error

Each of these error condi tions wil l cause an err or st atus bi t to be se t in th e
MPC Error Status Register. If a second error is detected while any of the
error bits is set, the OVFL bit is asserted, but none of the error bits are
changed. Each bit in the MPC Error Status Register may be cleared by
writing a 1 to it; writing a 0 to it has no effect. New error bits may be set
only when all previous error bits have been cleared.

When any bit in the MPC Error St atus register is set, the Raven will
attempt to latch as much information as possible about the error in the
MPC Error Address and Attribute Registers. Information is saved as
follows:

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