Motorola MVME2603-31X1, MVME2700 Series, MVME2604-13X1, MVME2604-33X1, MVME2604-43X1 Reference Manual

MVME2600/2700 Series

Single Board Computer

Programmer’s

Reference Guide

V2600A/PG2

Notice

While reasonable efforts have been made to assure the accuracy of this document,
Motorola, Inc. a ssumes n o lia bility r esulti ng from any omissio ns in this docu ment, or from
the use of the information ob tained therein. Motorola reserv es the right to r evise this
document and to ma ke c hanges from time to ti me in t he content hereof witho ut o bligation
of Motorola to notify any person of such revision or changes.

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It is possible that this pu blicati on ma y cont ain r eferenc e to, or i nformat ion a bout Mot oro la
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DFARS 252.227-7013.

Motorola, Inc.

Computer Group

2900 South Diablo Way

Tempe, Arizona 85282

Preface

The MVME2600/2700 Series Single Board Computer Programmer’s Reference Guide
provides brief board level information, complete memory maps, and detailed ASIC chip
information includ ing regi ster b it desc riptions f or the MVME2600 and MVME2700 se ries
Single Board Computers. The information contained in this manual applies to the single
board computers built from some of the plug-together components in the following list:

Table 1:

MVME2603-11X1 MVME2603-21X1 MVME2603-31X1

MVME2604-13X1 MVME2604-33X1 MVME2604-43X1

MVME2700-12X1 MVME2700-13X1 MVME2700-14X1
MVME2700-32X1 MVME2700-33X

1 MVME2700-34X1

MVME2700-42X1 MVME2700-43X1 MVME2700-44X1

RAM200-04X RAM200-04XA

This manual is intended for anyone who wants to

program these boards in order to design

OEM systems, supply addi ti ona l capability to an exi st ing compa ti bl e s yst em, or work in a
lab environment for experimental purposes.

A basic knowledge of computers and digital logic is assumed.
To use this manual, you should be familiar with the publications listed in Appendix A,

Related Documentation.
The following conventions are used in this document:

bold

is used for user input that you type just as it appears. Bold is also used for
commands, options and arguments to commands, and names of programs,
directories, and files.

italic

is used for names of variables to which you assign values. Italic is also used for
comments in screen displays and examples.

courier

is used for system output (e.g., screen displays, reports), examples, and system
prompts.

<RETURN> or <CR>

represents the carriage return or enter key.

CTRL

represents t h e C ont ro l key. Execute c on trol c ha rac te rs b y pr es si ng th e CTRL key
and the letter simultaneously, e.g., CTRL-d.

The computer programs stored in the Read Only Memory of this device contain material
copyrighted by Motorola Inc., first published 1990, and may be used only under a license
such as the License f or Computer Progra ms (Article 14) contained in Moto rola’s Terms and
Conditions of Sale, Rev. 1/79.

All Motorola PWBs (printed wiring boards) are manufactured by UL-recognized
manufacturers, with a flammability rating of 94V-0.

This equipment generates, uses, and can radiate electro- magnetic

!

WARNING

energy. It may cause or be susceptible to electro-magnetic
interference (EMI) if not installed and used in a cabinet with
adequate EMI protection.

Motorola® and the Motorola symbol are registered trademarks of Motorola, Inc.

TM

PowerStack

, VMEmoduleTM, and VMEsystemTM are trademarks of Motorola, Inc.

TM

PowerPC

, PowerPC 603TM, and PowerPC 604TMare trademarks of IBM Corp, and are

used by Motorola, Inc. under license from IBM Corp.

TM

AIX
Timekeeper

is a trademark of IBM Corp.

TM

and ZeropowerTM are trademarks of Thompson Components.

All other products ment io ned i n this document are trademarks or re gi st ered trademarks of
their respective holders.

©Copyright Motorola 1999

All Rights Reserved

Printed in the United States of America

February 1999

Safety Summary

Safety Depends On You

The following general safety precautions must be observed during all phases of operation, service, and repair of this
equipment. Failure to comply with these prec autions or with spe cific warnings els ewhere in this manua l violates saf ety
standards of design, manufacture, and intended use of the equipment. Motorola, Inc. assumes no liability for the
customer’s failure to comply with these requirements.

The safety precaut ions listed be low represent warnings of ce rtain danger s of which Mot orola is awar e. You, as the
user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of
the equipment in your operating environment.

Ground the Instrument.

To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. The
equipment is supp lied with a three- conductor ac pow er cable. The power cable must be plu gged into an appro ved
three-contact electrical outlet. The power jack and mating plug of the power cable meet International Electrotechnical
Commission (IEC) safety standards.

Do Not Operate in an Explosive Atmosphere.

Do not operate the equipment in the presence of flammable gases or fumes. Operation of any electrical equipment in
such an environment constitutes a definite safety hazard .

Keep Away From Live Circuits.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other
qualified maint enance personnel may remove equipment covers for internal subassembly or com ponent replacement
or any internal adjustment. Do not replace components with power cable connected. Under certain conditions,
dangerous voltages may exist even with the power cable removed. To avoid injuries, always disconnect power and
discharge circuit s before touching them.

Do Not Service or Adjust Alone.

Do not attempt internal service or adjustment unless another person capable of rendering first aid and resuscitation is
present.

Use Caution When Exposing or Handling the CRT.

Breakage of the Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To
prevent CRT implosion, avoid rough handling or jarring of the equipment. Handling of the CRT should be done only
by qualified mainte nance personnel using appr oved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.

Because of the dan ger of i ntrodu cing add ition al haza rds, do not ins tall sub stitut e parts or perf orm an y unauth orized
modification of the equipment. Con tact your local Mot or ola representative for service and re pa ir to ensure that safety
features are maintained.

Dangerous Procedure Warnings.

W arn ings , such as th e exa mple be low, precede potentially dangerous p roce dure s thro ughou t this ma nual . Instr uctio ns
contained in the warnings m ust be follow ed. You should also employ all ot her safety precautions w hich you dee m
necessary for the operation of the equi pm ent in your operating en vi ronment.

Dangerous voltages, capable of causing death, are present in this

!

WARNING

equipment. Use extreme caution when handling, testing, and
adjusting.

Contents

CHAPTER 1 Board Description and Memory Maps

Revision Note.............................................................................................................1-1

Introduction ................................................................................................................1-1

Manual Terminology..................................................................................................1-2

Overview....................................................................................................................1-3

Feature Summary.................................................... ...... .............................................1-4

System Block Diagram..............................................................................................1-5

Functional Description ...............................................................................................1-7

Overview.............................................................................................................1-7

Programming Model..................................................................................................1-8

Memory Maps.....................................................................................................1-8

Processor Memory Maps................................................. ...... ......................1-8

PCI Memory Maps....................................................................................1-14

VMEbus Mapping .......................................... ...... ..... ................................1-21

Falcon-Controlled System Registers ................................................. ...............1-27

System Configuration Register (SYSCR).................................................1-28

Memory Configuration Register (MEMCR).............................................1-30

System External Cache Control Register (SXCCR)..................................1-31

CPU Control Register................................................................................1-33

ISA Local Resource Bus..........................................................................................1-34

W83C553 PIB Registers...................................................................................1-34

PC87308VUL Super I/O (ISASIO) Strapping..................................................1-34

NVRAM/RTC & Watchdog Timer Registers...................................................1-34

Module Configuration and Status Registers.....................................................1-35

CPU Configuration Register......................................................................1-36

Base Module Feature Register...................................................................1-37

Base Module Status Register (BMSR)......................................................1-38

Seven-Segment Display Register .................................... ...... ....................1-39

VME Registers..................................................................................................1-39

LM/SIG Control Register..........................................................................1-40

LM/SIG Status Register.............................................................................1-41

Location Monitor Upper Base Address Register.......................................1-42

Location Monitor Lower Base Address Register......................................1-43

Semaphore Register 1................................................................................1-43

Semaphore Register 2................................................................................1-44

VME Geographical Address Register (VGAR)........................................1-44

vii

Z85230 ESCC and Z8536 CIO Registers and Port Pins ..................................1-44

Z8536/Z85230 Registers........................................................... ..... ...... .....1-45

Z8536 CIO Port Pins.................................................................................1-46

ISA DMA Channels .........................................................................................1-49

CHAPTER 2 Raven PCI Host Bridge & Multi-Processor Interrupt Controller
Chip

Introduction ...............................................................................................................2-1

Overview............................................................................................................2-1

Requirements......................................................................................................2-2

Features ..............................................................................................................2-2

Block Diagram...........................................................................................................2-4

Functional Description ..............................................................................................2-5

MPC Bus Interface.............................................................................................2-5

MPC Arbiter................................................................................................2-5

MPC Map Decoders....................................................................................2-7

MPC Write Posting .....................................................................................2-8

MPC Master ................................................................................................2-9

MPC Bus Timer ........................................................................................ 2-10

PCI Interface.....................................................................................................2-11

PCI Map Decoders....................................................................................2-11

PCI Configuration Space...........................................................................2-12

PCI Write Posting .....................................................................................2-12

PCI Master ................................................................................................2-13

Generating PCI Memory and I/O Cycles.........................................................2-13

Generating PCI Configuration Cycles..............................................................2-15

Generating PCI Special Cycles ........................................................................2-15

Generating PCI Interrupt Acknowledge Cycles...............................................2-16

Endian Conversion...........................................................................................2-16

When MPC Devices are Big-Endian.........................................................2-16

When MPC Devices are Little Endian...................................................... 2-17

Cycles Originating From PCI....................................................................2-18

Error Handling................................................ ..... ...... .......................................2-18

PCI/MPC Contention Handling........................................................................2-20

Registers ..................................................................................................................2-22

MPC Registers..................................................................................................2-22

Vendor ID/Device ID Registers................................................................2-24

Revision ID Register.................................................................................2-24

General Control-Status/Feature Registers.................................................2-25

MPC Arbiter Control Register..................................................................2-28

Prescaler Adjust Register..........................................................................2-29

viii

MPC Error Enable Register.......................................................................2-30

MPC Error Status Register........................................................................2-32

MPC Error Address Register.....................................................................2-34

MPC Error Attribute Register - MERAT..................................................2-34

PCI Interrupt Acknowledge Register ........................................................2-36

MPC Slave Address (0,1 and 2) Registers................................................2-37

MPC Slave Address (3) Register...............................................................2-38

MPC Slave Offset/Attribute (0,1 and 2) Registers....................................2-39

MPC Slave Offset/Attribute (3) Registers.................................................2-40

General Purpose Registers.........................................................................2-41

PCI Registers....................................................................................................2-41

Vendor ID/ Device ID Registers ...............................................................2-43

PCI Command/ Status Registers................................................................2-43

Revision ID/ Class Code Registers............................................................2-45

I/O Base Register.......................................................................................2-46

Memory Base Register ................................... ...... ..... ................................2-46

PCI Slave Address (0,1,2 and 3) Registers................................................2-47

PCI Slave Attribute/ Offset (0,1,2 and 3) Registers ..................................2-48

CONFIG_ADDRESS................................................................................2-49

PCI I/O CONFIG_ADDRESS Register ....................................................2-50

PCI I/O CONFIG_DATA Register ...........................................................2-51

Raven Interrupt Controller Implementation.............................................................2-52

Introduction.......................................................................................................2-52

The Raven Interrupt Controller (RavenMPIC) Features...........................2-52

Architecture...............................................................................................2-52

CSR’s Readability .....................................................................................2-53

Interrupt Source Priority............................................................................2-53

Processor’s Current Task Priority..............................................................2-53

Nesting of Interrupt Events........................................................................2-53

Spurious Vector Generation ......................................................................2-54

Interprocessor Interrupts (IPI)...................................................................2-54

8259 Compatibility....................................................................................2-54

Raven-Detected Errors ..............................................................................2-55

Timers........................................................................................................2-55

Interrupt Delivery Modes ..........................................................................2-55

Block Diagram Description..............................................................................2-57

Program Visible Registers......................................... ...... ..........................2-58

Interrupt Pending Register (IPR)...............................................................2-58

Interrupt Selector (IS)................................................................................2-58

Interrupt Request Register (IRR)...............................................................2-59

In-Service Register (ISR)..........................................................................2-59

Interrupt Router.........................................................................................2-59

ix

MPIC Registers ................................................................................................2-61

RavenMPIC Registers...............................................................................2-61

Feature Reporting Register ............................................................ ...........2-65

Global Configuration Register............................................................. .....2-66

Vendor Identification Register................................. ..... ............................2-67

Processor Init Register .................................................. ...... ......................2-67

IPI Vector/Priority Registers.....................................................................2-68

Spurious Vector Register..........................................................................2-69

Timer Frequency Register.........................................................................2-69

Timer Current Count Registers.................................................................2-70

Timer Basecount Registers .......................................................................2-70

Timer Vector/Priority Registers................................................................2-71

Timer Destination Registers......................................................................2-72

External Source Vector/Priority Registers................................................2-72

External Source Destination Registers......................................................2-74

Raven-Detected Errors Vector/Priority Register ......................................2-74

Raven-Detected Errors Destination Register............................................2-75

Interprocessor Interrupt Dispatch Registers..............................................2-76

Interrupt Task Priority Registers...............................................................2-76

Interrupt Acknowledge Registers..............................................................2-78

End-of-Interrupt Registers ........................................................................2-78

Programming Notes..........................................................................................2-79

External Interrupt Service.........................................................................2-79

Reset State.................................................................................................2-80

Operation..........................................................................................................2-81

Interprocessor Interrupts...........................................................................2-81

Dynamically Changing I/O Interrupt Configuration.................................2-81

EOI Register........................... ..... ...... ........................................................2-81

Interrupt Acknowledge Register...............................................................2-82

8259 Mode ................................................................................................2-82

Current Task Priority Level ......................................................................2-82

Architectural Notes...........................................................................................2-82

CHAPTER 3 Falcon ECC Memory Controller Chip Set

Introduction ...............................................................................................................3-1

Overview............................................................................................................3-1

Bit Ordering Convention....................................................................................3-1

Features .......................................................... ....................................................3-1

Block Diagrams.........................................................................................................3-2

Functional Description ..............................................................................................3-6

x

Performance........................................................................................................3-6

Four-beat Reads/Writes................................................... ...... ..... .................3-6

Single-beat Reads/Writes ............................................................................3-7

DRAM Speeds.............................................................................................3-7

ROM/Flash Speeds....................................................................................3-11

PowerPC 60x Bus Interface..............................................................................3-12

Responding to Address Transfers..............................................................3-12

Completing Data Transfers........................................................................3-12

Cache Coherency.......................................................................................3-12

Cache Coherency Restrictions...................................................................3-13

L2 Cache Support......................................................................................3-13

ECC...................................................................................................................3-13

Cycle Types...............................................................................................3-13

Error Reporting..........................................................................................3-13

Error Logging.......................... ...... ............................................................3-15

DRAM Test er....................... ...... ..... ..................................................................3-15

ROM/Flash Interface ........................................................................................3-16

Refresh/Scrub....................................................................................................3-20

Blocks A and/or B Present, Blocks C and D Not Present .........................3-20

Blocks A and/or B Present, Blocks C and/or D present............................3-21

DRAM Arbitration................................................. ...... ..... ................................3-21

Chip Defaults....................................................................................................3-22

External Register Set ........................................................................................3-22

CSR Accesses...................................................................................................3-23

Programming Model................................................................................................3-24

CSR Architecture..............................................................................................3-24

Register Summary.............................................................................................3-29

Detailed Register Bit Descriptions ...................................................................3-32

Vendor/Device Register ........................................................ ....................3-33

Revision ID/ General Control Register .....................................................3-34

DRAM Attributes Register................................... ..... ................................3-36

DRAM Base Register.................... ...... ..... .................................................3-37

CLK Frequency Register...........................................................................3-38

ECC Control Register ................................................................................3-38

Error Logger Register............................... .................................................3-41

Error_Address Register.............................................................................3-43

Scrub/Refresh Register..............................................................................3-43

Refresh/Scrub Address Register................................................................3-44

ROM A Base/Size Register.......................................................................3-45

ROM B Base/Size Register .......................................................................3-48

DRAM Tester Control Registers............................................................ ...3-51

32-Bit Counter...........................................................................................3-51

xi

Test SRAM................................................................................................3-52

Power-Up Reset Status Register 1 ............................................................3-53

Power-Up Reset Status Register 2 ............................................................3-53

External Register Set.................................................................................3-54

Software Considerations..........................................................................................3-55

Parity Checking on the PowerPC Bus..............................................................3-55

Programming ROM/Flash Devices..................................................................3-55

Writing to the Control Registers.......................................................................3-55

Sizing DRAM...................................................................................................3-56

ECC Codes ..............................................................................................................3-59

Data Paths................................................................................................................3-61

CHAPTER 4 Universe (VMEbus to PCI) Chip

General Information ..................................................................................................4-1

Introduction........................................................................................................4-1

Product Overview - Features..............................................................................4-1

Functional Description ..............................................................................................4-2

Architectural Overview......................................................................................4-2

VMEbus Interface.................. ..... ................................................................4-4

PCI Bus Interface........................................................................................4-5

Interrupter and Interrupt Handler................................................................4-6

DMA Controller..........................................................................................4-7

Registers - Universe Control and Status Registers (UCSR)......................................4-7

Universe Register Map.......................................................................................4-8

PCI Reset Problems Associated with the Initial Version of the Universe Chip ......4-14

Problem Description.........................................................................................4-14

Examples..........................................................................................................4-16

Example 1: MVME2600 Series Board Exhibits Problem.........................4-16

Example 2: MVME3600 Series Board Acts Differently ..........................4-18

Example 3: Universe Chip is Checked at Tundra.....................................4-20

CHAPTER 5 Programming Details

Introduction ...............................................................................................................5-1

PCI Arbitration..........................................................................................................5-1

Interrupt Handling .....................................................................................................5-2

RavenMPIC........................................................................................................5-3

8259 Interrupts ...................................................................................................5-4

ISA DMA Channels...................................................................................................5-7

Exceptions .................................................................................................................5-8

xii

Sources of Reset..................................................................................................5-8

Soft Reset............................. ...... .........................................................................5-9

Universe Chip Problems after a PCI Reset.........................................................5-9

Error Notification and Handling.......................................................................5-10

Endian Issues ...........................................................................................................5-11

Processor/Memory Domain.................................................... ...... ..... ...............5-14

Raven’s Involvement ........................................................................................5-14

PCI Domain ......................................................................................................5-14

PCI-SCSI...................................................................................................5-14

PCI-Ethernet..............................................................................................5-15

PCI-Graphics.............................................................................................5-15

Universe’s Involvement....................................................................................5-15

VMEbus Domain.............................................................. ...... ...... ....................5-15

ROM/Flash Initialization .........................................................................................5-16

APPENDIX A Related Documentation

Overview...................................................................................................................A-1

MCG Customer Services .............................................. ...... ..... .................................A-2

Motorola Computer Group Documents....................................................................A-3

Manufacturers’ Documents.......................................................................................A-5

Related Specifications.............................................................................................A-10

GLOSSARY

Abbreviations, Acronyms, and Terms to Know.....................................................GL-1

INDEX

xiii

xiv

List of Figures

Figure 1-1. MVME2600 Series System Block Diagram ...........................................1-6

Figure 1-2. VMEbus Master Mapping.....................................................................1-22

Figure 1-3. VMEbus Slave Mapping.......................................................................1-24

Figure 2-1. Raven Block Diagram.............................................................................2-4

Figure 2-2. PCI Spread I/O Cycle Mapping............................................................2-14

Figure 2-3. Big to Little Endian Data Swap ............................................................2-17

Figure 2-4. RavenMPIC Block Diagram.................................................................2-57

Figure 3-1. Falcon Pair Used with DRAM in a System ............................................3-3

Figure 3-2. Falcon Internal Data Paths (Simplified)..................................................3-4

Figure 3-3. Overall DRAM Connections...................................................................3-5

Figure 3-4. Data Path for Reads from the Falcon Internal CSRs.............................3-24

Figure 3-5. Data Path for Writes to the Falcon Internal CSRs.................................3-25

Figure 3-6. Memory Map for Byte Reads to the CSR.............................................3-26

Figure 3-7. Memory Map for Byte Writes to the Internal Register Set and

Test SRAM...............................................................................................................3-27

Figure 3-8. Memory Map for 4-Byte Reads to the CSR..........................................3-28

Figure 3-9. Memory Map for 4-Byte Writes to the Internal Register Set and

Test SRAM...............................................................................................................3-28

Figure 3-10. PowerPC Data to DRAM Data Correspondence.................................3-62

Figure 4-1. Architectural Diagram for the Universe..................................................4-3

Figure 4-2. UCSR Access Mechanisms.....................................................................4-8

Figure 5-1. MVME2600/2700 Series Interrupt Architecture.....................................5-2

Figure 5-2. PIB Interrupt Handler Block Diagram....................................................5-5

Figure 5-3. Big-Endian Mode..................................................................................5-12

Figure 5-4. Little-Endian Mode...............................................................................5-13

xv

xvi

List of T ables

Table 1-1. MVME2600 Series Features Summary ...................................................1-4

T ab le 1-2. Default Processor Memory Map ................................................... ...... .....1-9

T ab le 1-3. CHRP Memory Map Example................................ ...... ...... ....................1-10

Table 1-4. Raven MPC Register Values for CHRP Memory Map...........................1-11

Table 1-5. PREP Memory Map Example.................................................................1-12

Table 1-6. Raven MPC Register Values for PREP Memory Map ...........................1-13

Table 1-7. PCI CHRP Memory Map .......................................................................1-14

Table 1-8. Raven PCI Register Values for CHRP Memory Map.............................1-16

Table 1-9. Universe PCI Register Values for CHRP Memory Map ........................1-16

Table 1-10. PCI PREP Memory Map.......................................................................1-18

Table 1-11. Raven PCI Register Values for PREP Memory Map............................1-19

Table 1-12. Universe PCI Register Values for PREP Memory Map........................1-20

Table 1-13. Universe PCI Register Values for VMEbus Slave Map Example ........1-25

Table 1-14. VMEbus Slave Map Example ...............................................................1-26

Table 1-15. System Register Summary....................................................................1-27

Table 1-16. Strap Pins Configuration for the PC87308VUL...................................1-34

Table 1-17. MK48T59/559 Access Registers ..........................................................1-35

Table 1-18. Module Configuration and Status Registers.........................................1-36

Table 1-19. VME Registers......................................................................................1-40

Table 1-20. Z8536/Z85230 Access Registers..........................................................1-45

Table 1-21. Z8536 CIO Port Pins Assignment .......................................................1-46

Table 1-22. Interpretation of MID3-MID0 ..............................................................1-48

Table 1-23. PIB DMA Channel Assignments..........................................................1-49

T ab le 2-1. CHRP Compliant Memory Map...............................................................2-7

Table 2-2. MPC Transfer Types...............................................................................2-10

T ab le 2-3. PCI Command Codes....... ..... ..................................................................2-13

Table 2-4. Address Modification for Little Endian Transfers..................................2-18

T ab le 2-5. Raven MPC Register Map ................................ ..... ................................2-22

Table 2-6. Raven PCI Configuration Register Map.................................................2-42

Table 2-7. Raven PCI I/O Register Map..................................................................2-42

T ab le 2-8. RavenMPIC Register Map...................................... ...... ..........................2-61

Table 3-1. PowerPC 60x Bus to DRAM Access Timing When Configured for

70ns Page Devices .....................................................................................................3-8

Table 3-2. PowerPC 60x Bus to DRAM Access Timing When

Configured for 60ns Page Devices. ...........................................................................3-9

xvii

Table 3-3. PowerPC 60x Bus to DRAM Access Timing When

Configured for 50ns Hyper Devices........................................................................3-10

Table 3-4. PowerPC 60x Bus to ROM/Flash Access Timing When

Configured for 32/64-bit Devices............................................................................3-11

Table 3-5. PowerPC 60x Bus to ROM/Flash Access Timing When

Configured for 8-bit Devices...................................................................................3-11

T ab le 3-6. Error Reporting.......................................................................................3-14

Table 3-7. PowerPC 60x to ROM/Flash Address Mapping with Two

8-bit Devices............................................................................................................3-17

Table 3-8. PowerPC 60x Address to ROM/Flash Ad dress Mapping with

Two 32-bit or One 64-bit Device(s) ........................................................................3-19

T ab le 3-9. Register Summary ............................... ..... .............................................3-30

Table 3-10. ram spd1,ram spd0 and DRAM Type...................................................3-35

Table 3-11. Block_A/B/C/D Configurations...........................................................3-36

Table 3-12. rtest encodings......................................................................................3-44

Table 3-13. ROM Block A Size Encoding..............................................................3-46

Table 3-15. Read/Write to ROM/Flash....................................................................3-47

Table 3-14. rom_a_rv and rom_b_rv encoding .......................................................3-47

Table 3-16. ROM Block B Size Encoding ..............................................................3-50

T ab le 3-17. Sizing Addresses................................ ..................................................3-57

Table 3-18. PowerPC 60x Address to DRAM Address Mappings..........................3-58

Table 3-19. Syndrome Codes Ordered by Bit in Error............................................3-59

Table 3-20. Single-Bit Errors Ordered by Syndrome Code.....................................3-60

Table 3-21. PowerPC Data to DRAM Data Mapping.............................................3-63

Table 4-1. Universe Register Map ............................................................................4-9

T ab le 5-1. PCI Arbitration Assignments.......................... ...... ..... ..............................5-1

T ab le 5-2. RavenMPIC Interrupt Assignmen ts ....................................................... .5-3

Table 5-3. PIB PCI/ISA Interrupt Assignments........................................................5-6

Table 5-4. Reset Sources and Devices Affected .......................................................5-9

Table 5-5. Error Notification and Handling ............................................................5-10

T ab le 5-6. ROM/FLASH Bank Default..................................................................5-16

Table A-1. Motorola Computer Group Documents .................................................A-3

Table A-2. Manufacturers’ Documents ..................................................................A-5

Table A-3. Related Specifications ........................................................................A-10

xviii

1Board Description and Memory

Revision Note

This manual has been updated for the following reasons:

❏ To reflect that, since the differences between the MVME2600 and

the MVME2700 series SBCs are primarily related to the processor
and the implementation of L2 cache, the two share th e same
programming model. While much of this manual refers specifically
to MVME2600 hardware, the programming information is
applicable to both the MVME2600 and MVME2700 families.

❏ To reflect that a Universe II chip is available and that it includes

fixes for PCI reset problems which existed in the earlier version of
the Universe chip. For more details, see PCI Reset Problems
Associated with the Initial Version of the Universe Chip on page
4-14.

Introduction

Maps

1

This manual provides programming infor mat ion for the MVME2600 and
MVME2700 Single Board Computers (SBCs). Extensive programming
information is pr ovided for several Appl ication-Specific I ntegrated Circuit
(ASIC) devices used on the boards. Reference information is included in
Appendix A for the Large Scale Integration (LSI) devices used on the
boards and sources for additional information are listed.

This chapter briefly describes the board level hardware features of the
MVME2600 series Single Board Computers. The chapter begins with a
board level overvi ew and feat ures lis t. Memo ry maps are n ext, and are the
major feature of this chapter.

1-1

1

Board Description and Memory Maps

Programmable registers in the MVME2600/2700 series that reside in
ASICs are covered in the chapters on those ASICs. Chapter 2 covers the
Raven chip, Chapter 3 cover s the Falcon chip set, Chapter 4 covers the
Universe chip, and Chapter 5 covers certain programming features, such
as interrupts and exceptions. Appendix A lists all related documentation.

Manual Terminology

Throughout this manual, a convention is used which precedes data and
address parameters by a character identifying the numeric format as
follows:

$

dollar

%

percent

&

ampersand

For example, “12” is t he decimal numbe r twelve, and “$12” is the decimal
number eighteen.

Unless otherwise specified, all address references are in hexadecimal.

specifies a hexadecimal character
specifies a binary number
specifies a decimal number

1-2

An asterisk (*) following the signal name for signals which are level
significant denotes that the signal is true or valid when the signal is low.

An asterisk (*) following the signal name for signals which are edge
significant denotes that the acti ons initiat ed by that s ignal occur on h igh to

low transitio n.

Note In some places in this docum ent, an undersc ore (_) foll owing

the signal name is used to indicate an active low signal.

In this manual, assertion and negation are used to specify forcing a signal
to a particula r sta te. In pa rtic ular, asser ti on and a ssert ref er to a signal that
is active or true; negation and negate indicate a signal that is inactive or
false. These terms ar e used independently of the vo ltage level (high or l ow)
that they represent.

Data and address sizes for MPC60x chips are defined as follows:

Overview

❏ A byte i s eight bits, numb ered 0 through 7, wit h bit 0 being the leas t

significant.

❏ A half-word is 16 b its, number ed 0 thr oug h 15, with bit 0 b eing th e

least significant.

❏ A word or single wor d is 32 bits , numbered 0 t hrough 31, wit h bit 0

being the least significant.

❏ A double word is 64 bits, numbered 0 through 63, with bit 0 being

the least significant.

Refer to Chapter 5 for Endian Issues, which covers which parts of the
MVME2600/2700 series use big-endian byte ordering, and which use
small-endian byte ordering.

The terms control bit and status bit are used extensively in this document.
The term control b it is used to d escribe a bit in a register that can be set and
cleared under softwar e c ont rol . The te rm tr ue is used to indica te tha t a bit
is in the state that enables the function it controls. The term false is used to
indicate that the bit is in the state that disables the function it controls. In
all tables, th e terms 0 and 1 are used to describe the actual va lue that should
be written to the bit, or the value that it yields when read. The term status
bit is us ed to describe a bit in a register that reflects a specific condition.
The status bit can be read by software to determine operational or
exception conditions.

1

Overview

The MVME2600/2700 series SBC families provide many standard
features required by a computer system: SCSI, Ethernet interface,
keyboard interface, mouse interface, sync and async serial ports, parallel
port, boot Flash, and up to 256MB of ECC DRAM.

1-3

1

Board Description and Memory Maps

Feature Summary

There are many models based on the MVME2600/27 00 series architecture.
The following table summarizes the major features of the MVME2600
series:

Table 1-1. MVME2600 Series Features Summary

Feature Description

Processors Single

Supports BGA processors only:

MVME2600: MPC603, MPC604.

MVME2700: MPC750

Bus Clock Frequencies up to 66MHz
L2 Cache Build-option for 256KB Look-aside L2 Cache
Flash 4MB or 8MB (64-bit wide), with socketed 1MB (16-bit wide)
DRAM 16MB to 256MB, ECC Protected (Single-bit Correction, Double-bit

Detection)

Two-way Interleaved
NVRAM 8KB
RTC MK48T59/559 Device
Peripheral

Support

VME Interface 32-bit Address/64-bit Data PCI

1-4

Two async serial ports

Two sync/async serial ports

One (IEEE1284, or printer) Parallel Port

8-bit or 16-bit single-ended SCSI interface

AUI or 10Base-T/100Base-TX Ethernet interface

NO Graphics Interface on MVME2600 series

One PS/2 Keyboard and one PS/2 Mouse

One PS/2 Floppy Port

A32/A24/A16, D64 (MBLT)/D32/D16/D08 Master and Slave

Programmable Interrupter & Interrupt Handler

Full System Controller Functions

Programmable DMA Controller with link list support

Location Monitor

Table 1-1. MVME2600 Series Features Summary (Continued)

Feature Description

PMC Slots One 32/64-bit Slot
Miscellaneous RESET/ABORT Switch

Status LEDs

System Block Diagram

The MVME2600/2700 series provides the 256KB look-aside external
cache option. The Falcon chip set controls the boot Flash and the ECC
DRAM. The Raven ASIC functions as the 64-bit PCI host bridge and the
MPIC interrupt contro ller. PCI devices include: SCSI, VME, Ethernet, and
one PMC slot. Standar d I/O functions are provided by the S uper I/O device
which resides on the ISA bus. The NVRAM/RTC and the optional
synchronous serial ports also reside on the ISA bus. The general system
block diagram for MVME2600/2700 series is shown below:

System Block Diagram

1

1-5

1

Board Description and Memory Maps

CLOCK

GENERATOR

PHB & MPIC

RAVEN ASIC

64-BIT PMC SLOT

L2 CACHE

256K

PROCESSOR

MPC603/604

REGISTERS

ISA

FLASH

1MB

MEMORY CONTROLLER

66MHz MPC604 PROCESSOR BUS

33MHz 32/64-BIT PCI LOCAL BUS

PIB

W83C553

ISA BUS

ETHERNET

DEC21140

AUI/10BT/100BTX

RTC/NVRAM/WD

MK48T559

FALCON CHIPSET

MEMORY EXPANSION CONNECTORSDEBUG CONNECTOR

SCSI

53C825A

FLASH

4MB or 8MB

SYSTEM

REGISTERS

VME BRIDGE

UNIVERSE

BUFFERS

PCI EXPANSION

1-6

MOUSE KBD FLOPPY & LED

PMC FRONT I/O SLOT

SUPER I/O

PC87308

PARALLEL

FRONT PA N EL

ESCC
85230

SERIAL

712/761 P2 I/O OPTIONS

VME P2 VME P1

CIO

Z8536

Figure 1-1. MVME2600 Series System Block Diagram

11536.00 9611

Functional Description

Overview

The MVME2600/2700 series is a family of single-slot SBCs. The
MVME2600 family consists of t he MPC603/604 processor, the Ra ven PCI
Bridge & Interrupt Controller, the ECC Memory Controller Falcon
chipset, 5MB or 9MB of Flash memory, 16MB to 256MB of ECC­protected DRAM, and a rich set of features of I/O peripherals. The
MVME2700 family offers the same hardware features, but with the
MCP750 processor.

I/O peripheral devices on the PCI bus are: SCSI chip, Ethernet chip,
Universe VMEbus interface ASIC, and one PMC slot . Functions prov ided
from the ISA bus are: a P1 284/Parallel port, two asynchronous serial por ts,
two sync/async serial ports, a real-time clock, and counters/timers.

The MVME2600/2700 series board interfaces to the VMEbus via the P1
and P2 connectors, which use the new 5-row 160-pin connectors as
specified in the propos ed VME64 Exten sion Sta ndard. I t also draws +5V,
+12V, and -12V power from the VMEbus backplane through these two
connectors. 3.3V supply is regulated onboard from the +5V power.

Functional Description

1

Front panel connector s on the MVME2600 /2700 seri es board include: a 6 ­pin circular DIN conn ector for the keyboar d interface, a 6-pin circular DIN
connector for the mouse interface, and a 50-pin connector for the floppy
and status LEDs. All signals fo r the serial ports, the P1284/Pri nter port, the
SCSI interface, and the Ethernet interface are routed to P2.

There are two P2 I/O options supported by the MVME2600/2700 series:
the MVME712M mode and the MVME761 mode. The MVME761 mode
provides the enhanced P1284 parallel port interface and the full
synchronous support for Serial Ports 3 and 4. The MVME712M version
provides backward comp at ibi lity wit h pr evi ous SBCs. I n ei ther mode, 16­bit SCSI capability can only be used by systems with 5-row DIN support
because the additional 8 bits of SCSI data lines reside on row Z of P2.

1-7

1

Board Description and Memory Maps

The MVME2600/2700 series contains one IEEE1386.1 PCI Mezzanine
Card (PMC) slot. This PMC s lot i s 64-bit capable and su ppor ts bo th front
and rear I/O. Pins 1 through 30 of th e PMC connector J14 are routed to pins
D1 through D30 of the 5-row DIN P2 connector. J14 pin 31 is connected
to P2 pin Z29, and J14 pin 32 is connected to P2 pin Z31.

Additional PCI expansion is supported with a 114-pin Mictor connector.
This connection allows stacking of a carrier board to increase the I/O
capability, such as a dual-PMC carrier board.

Programming Model

Memory Maps

The following sections describe the memory maps for the
MVME2600/2700 series.

Processor Memory Maps

1-8

The Processor memory map is controlled by the Raven ASIC and the
Falcon chipset. The Raven ASIC and the Falcon chipset have flexible
programming Map Decoder registers to customize the system to fit many
different applications.

Programming Model

Default Processor Memory Map

After a reset, the Raven ASIC and the Falcon chipset provide the default
processor memory map as shown in the following table.

Table 1-2. Default Processor Memory Map

1

Processor Address

Start End

0000 0000 7FFF FFFF 2G Not mapped
8000 0000 8001 FFFF 128K PCI/ISA I/O Space 1
8002 0000 FEF7 FFFF 2G - 16M

FEF8 0000 FEF8 FFFF 64K Falcon Registers
FEF9 0000 FEFE FFFF 384K Not mapped
FEFF 0000 FEFF FFFF 64K Raven Registers
FF00 0000 FFEF FFFF 15M Not mapped
FFF0 0000 FFFF FFFF 1M ROM/FLASH Bank A or Bank B 2

Size Definition

Not mapped

- 640K

Notes:

1. This default map for PCI/ISA I/O space allows software to
determine if the system is MPC105-based or Falcon/Raven-based
by examining either the PHB Device ID or the CPU Type Register.

2. The first one Mbyte of ROM/FLASH Bank A appears at this range
after a reset if the rom_b_rv control bit is cleared. If the rom_b_rv
control bit is set t hen this address range maps t o ROM/FLASH Bank
B.

Notes

1-9

1

Board Description and Memory Maps

Processor CHRP Memory Map

The following table shows a recommended CHRP memory map from the
point of view of the processor.

Table 1-3. CHRP Memory Map Example

Processor Address

Size Definition

Start End

0000 0000 top_dram dram_size System Memory (onboard DRAM) 1, 2
4000 0000 FCFF FFFF 3G - 48M PCI Memory Space:

4000 0000 to FCFF FFFF

FD00 0000 FDFF FFFF 16M Zero-Based PCI/ISA Memory Space

(mapped to 00000000 to 00FFFFFF)

FE00 0000 FE7F FFFF 8M Zero-Based PCI/ISA I/O Space

(mapped to 00000000 to 007FFFFF)
FE80 0000 FEF7 FFFF 7.5M R eserved
FEF8 0000 FEF8 FFFF 64K Falcon Registers
FEF9 0000 FEFE FFFF 384K Reserved
FEFF 0000 FEFF FFFF 64K Raven Registers 9
FF00 0000 FF7F FFFF 8M ROM/FLASH Bank A 1,7
FF80 0000 FF8F FFFF 1M ROM/FLASH Bank B 1,7
FF50 0000 FFEF FFFF 6M Reserved

Notes

3,4,8

3,8

3,5,8

FFF0 0000 FFFF FFFF 1M ROM/FLASH Bank A or Bank B 7

Notes:

1. Programmable via Falcon chipset.

2. To enable the “Processor-hole” area, program the Falcon chi pset to

3. Programmable via Raven ASIC.

1-10

ignore 0x000A0000 - 0x000BFFFF add ress range and progra m the
Raven to map this address range to PCI memory space.

Programming Model

4. CHRP requires the starting address for t he PCI memory space to b e
256MB-aligned.

5. Programmable via Raven ASIC for either contiguous or spr ead-I/O
mode.

6. The actual size of each ROM/FLASH bank may vary.

7. The first one Mbyte of ROM/FLASH Bank A appears at this range
after a reset if the rom_b_rv control bit is cleared. If the rom_b_rv
control bit is set t hen this address range maps t o ROM/FLASH Bank
B.

8. This range can be mapped to the VMEbus by programming the
Universe ASIC accordingly. The map shown is the recommended
setting which uses the Sp ecial PCI Sl ave Ima ge and two of the f our
programmable PCI Slave Images.

9. The only method to generate a PCI Interrupt Acknowledge cycle

(8259 IACK) is to perform a read access to the Raven’s PIACK
register at 0xFEFF0030.

The following table shows the programmed values for the assoc- iated
Raven MPC registers for the processor CHRP memory map.

1

Table 1-4. Raven MPC Register Values for CHRP Memory Map

Address Register Name Register Value

FEFF 0040 MSADD0 4000 FCFF
FEFF 0044 MSOFF0 & MSATT0 0000 00C2
FEFF 0048 MSADD1 FD00 FDFF
FEFF 004C MSOFF1 & MSATT1 0300 00C2
FEFF 0050 MSADD2 0000 0000
FEFF 0054 MSOFF2 & MSATT2 0000 0002
FEFF 0058 MSADD3 FE00 FE7F
FEFF 005C MSOFF3 & MSATT3 0200 00C0

1-11

1

Board Description and Memory Maps

Processor PREP Memory Map

The Raven/Falcon chipset can be programmed for PREP-compatible
memory map. The following table shows the PREP memory map of the
MVME2600/2700 series from the point of view of the processor.

Table 1-5. PREP Memory Map Example

Processor Address

Start End

0000 0000 top_dram dram_size System Memory (onboard DRAM) 1

Size Definition Notes

8000 0000 BFFF FFFF 1G Zero-Based PCI I/O Space:

0000 0000 - 3FFFF FFFF

C000 0000 FCFF FFFF 1G - 48M Zero-Based PCI/ISA Memory Space:

0000 0000 - 3CFFFFFF
FD00 0000 FEF7 FFFF 40.5M Reserved
FEF8 0000 FEF8 FFFF 64K Falcon Registers
FEF9 0000 FEFE FFFF 384K Reserved
FEFF 0000 FEFF FFFF 64K Raven Registers 6
FF00 0000 FF7F FFFF 8M ROM/FLASH Bank A 1, 3
FF80 0000 FF8F FFFF 1M ROM/FLASH Bank B 1, 3
FF90 0000 FFEF FFFF 6M Reserved
FFF0 0000 FFFF FFFF 1M ROM/FLASH Bank A or Bank B 4

2

2, 5

Notes:

1. Programmable via Falcon chipset.

2. Programmable via Raven ASIC.

3. The actual size of each ROM/FLASH bank may vary.

4. The first 1 Mbyte of ROM/FLASH Bank A appears at this range

1-12

after a reset if the rom_b_rv control bit is cleared. If the rom_b_rv

Programming Model

control bit is set t hen this address range maps t o ROM/FLASH Bank
B.

5. This range can be mapped to the VMEbus by programming the
Universe ASIC accordingly.

6. The only method to generate a PCI Interrupt Acknowledge cycle

(8259 IACK) is to perform a read access to the Raven’s PIACK
register at 0xFEFF0030.

The following table shows the programmed values for the associated
Raven MPC registers for the processor PREP memory map.

Table 1-6. Raven MPC Register Values for PREP Memory Map

Address Register Name Register Value

FEFF 0040 MSADD0 C000 FCFF
FEFF 0044 MSOFF0 & MSATT0 4000 00C2
FEFF 0048 MSADD1 0000 0000
FEFF 004C MSOFF1 & MSATT1 0000 0002

1

FEFF 0050 MSADD2 0000 0000
FEFF 0054 MSOFF2 & MSATT2 0000 0002
FEFF 0058 MSADD3 8000 BFFF
FEFF 005C MSOFF3 & MSATT3 8000 00C0

PCI Configuration Access

PCI Configuration acc esses ar e accomplis hed via t he CONFIG_ADD and
CONFIG_DAT registers. These two r egisters are implemented b y the
Raven ASIC. In the CHRP memory map example, the CONFIG_ADD and
CONFIG_DAT registers are located at 0xFE000CF8 and 0xFE000CFC,
respectively. With the PREP memory map, the CONFIG_ADD register
and the CONFIG_DAT register are located at 0x80000CF8 and
0x80000CFC, respectively.

1-13

1

Board Description and Memory Maps

PCI Memory Maps

The PCI memory map is controlled by the Raven ASIC and the Universe
ASIC. The Raven ASIC and the Universe ASIC have flexible
programming Map Decoder registers to customize the system to fit many
different applications.

Default PCI Memory Map

After a reset, the Raven ASIC and the Univer se ASIC turn all the PCI slave
map decoders off. Software must program the appropriate map decoders
for a specific environment.

PCI CHRP Memory Map

The following table shows a PCI memory map of the MVME2600/2700
series that is CHRP-compatible fro m the point of view of the PCI local bu s.

Table 1-7. PCI CHRP Memory Map

PCI Address

Start End

0000 0000 top_dram dram_size Onboard ECC DRAM 1
4000 0000 EFFF FFFF 3G - 256M VMEbus A32/D32 (Super/Program) 3
F000 0000 F7FF FFFF 128M VMEbus A32/D16 (Super/Program) 3
F800 0000 F8FE FFFF 16M - 64K VMEbus A24/D16 (Super/Program) 4
F8FF 0000 F8FF FFFF 64K VMEbus A16/D16 (Super/Program) 4
F900 0000 F9FE FFFF 16M - 64K VMEbus A24/D32 (Super/Data) 4
F9FF 0000 F9FF FFFF 64K VMEbus A16/D32 (Super/Data) 4
FA00 0000 FAFE FFFF 16M - 64K VMEbus A24/D16 (User/Program) 4
FAFF 0000 FAFF FFFF 64K VMEbus A16/D16 (User/Program) 4
FB00 0000 FBFE FFFF 16M - 64K VMEbus A24/D32 (User/Data) 4
FBFF 0000 FBFF FFFF 64K VMEbus A16/D32 (User/Data) 4
FC00 0000 FC03 FFFF 256K RavenMPIC 1

Size Definition Notes

1-14

Table 1-7. PCI CHRP Memory Map (Continued)

Programming Model

1

PCI Address

Size Definition Notes

Start End

FC04 0000 FCFF FFFF 16M - 256K PCI Memory Space
FD00 0000 FDFF FFF F 16M PCI Memory Space or

System Memory Alias Space (mapped
to 00000000 to 00FFFFFF)

FE00 0000 FFFF FFFF 48M Reserved

Notes:

1. Programmable via the Raven’s PCI Configuration registers.

2. To enabled the CHRP “io-hole”, program the Raven to ignore the
0x000A0000 - 0x000FFFFF address range.

3. Programmable mapping via the four PCI Slave Images in the
Universe ASIC.

4. Programmable mapping via the Special Slave Image (SLSI) in the
Universe ASIC.

1

1-15

1

Board Description and Memory Maps

The following table shows the programmed values for the associated
Raven PCI registers for the PCI CHRP memory map.

Table 1-8. Raven PCI Register Values for CHRP Memory Map

Configuration

Address Offset

$14 RavenMPIC MBASE FC00 0000 FC00 0000
$80 PSADD0 0000 3FFF 0100 3FFF
$84 PSOFF0 & PSATT0 0000 00FX 0000 00FX
$88 PSADD1 0000 0000 FD00 FDFF
$8C PSOFF1 & PSATT1 0000 0000 0000 00FX
$90 PSADD2 0000 0000 0000 0000
$94 PSOFF2 & PSATT2 0000 0000 0000 0000
$98 PSADD3 0000 0000 0000 0000
$9C PSOFF3 & PSATT3 0000 0000 0000 0000

Configuration

Register Name

Register Value

(Aliasing OFF)

Register Value

(Aliasing ON)

The next table shows the programmed values for the associated Universe
PCI registers for the PCI CHRP memory map.

Table 1-9. Universe PCI Register Values for CHRP Memory Map

Configuration

Address Offset

Configuration

Register Name

Register Value

$100 LSI0_CTL C082 5100
$104 LSI0_BS 4000 0000
$108 LS I0_B D F000 0000
$10C LSI0_TO XXXX 0000
$114 LSI1_CTL C042 5100
$118 LSI1_BS F000 0000
$11C LSI1_BD F800 0000

1-16

Programming Model

Table 1-9. Universe PCI Register Values for CHRP Memory Map (Continued)

1

Configuration

Address Offset

$120 LSI1_TO XXXX 0000
$128 LSI2_CTL 0000 0000
$12C LSI2_BS XXXX XXXX
$130 LSI2_BD XXXX XXXX
$134 LSI2_TO XXXX XXXX
$13C LSI3_CTL 0000 0000
$140 LSI3_BS XXXX XXXX
$144 LSI3_BD XXXX XXXX
$148 LSI3_TO XXXX XXXX
$188 SLSI C0A053F8

Configuration

Register Name

Register Value

1-17

1

Board Description and Memory Maps

PCI PREP Memory Map

The following table shows a PCI memory map of the MVME2600/2700
series that is PREP-compatible f rom the poi nt of view of t he PCI loca l bus.

Table 1-10. PCI PREP Memory Map

PCI Addres s

Start End

0000 0000 00FF FFFF 16M PCI/ISA Memory Space
0100 0000 2FFF FFFF 752M VMEbus A32/D32 (Super/Program) 3
3000 0000 37FF FFFF 128M VMEbus A32/D16 (Super/Program) 3
3800 0000 3 8FE FFFF 16M - 64K VMEbus A24/D16 (Super/Program) 4
38FF 0000 38FF FFFF 64K VMEbus A16/D16 (Super/Program) 4
3900 0000 3 9FE FFFF 16M - 64K VMEbus A24/D32 (Super/Data) 4
39FF 0000 39FF FFFF 64K VMEbus A16/D32 (Super/Data) 4
3A00 0000 3AFE FFFF 16M - 64K VMEbus A24/D16 (User/Program) 4
3AFF 0000 3AFF FFFF 64K VMEbus A16/D26 (User/Program) 4
3B00 0000 3BFE FFFF 16M - 64K VMEbus A24/D32 (User/Data) 4
3BFF 0000 3BFF FFFF 64K VMEbus A16/D32 (User/Data) 4
3C00 0000 7FFF FFFF 1G + 64M PCI Memory Space
8000 0000 FBFF FFFF 2G - 64M Onboard ECC DRAM 1

Size Definition Notes

FC00 0000 FC03 FFFF 256K RavenMPIC 1
FC04 0000 FFFF FFFF 64M - 256K PCI Memory Space

Notes:

1. Programmable via the Raven’s PCI Configuration registers.

2. To enabled the CHRP “io-hole”, program the Raven to ignore the

1-18

0x000A0000 - 0x000FFFFF address range.

Programming Model

3. Programmable mapping via the four PCI Slave Images in the
Universe ASIC.

4. Programmable mapping via the Special Slave Image (SLSI) in the
Universe ASIC.

The following table shows the programmed values for the associated
Raven PCI registers for the PREP-compatible memory map.

Table 1-11. Raven PCI Register Values for PREP Memory Map

1

Configuration

Address Offset

$14 RavenMPIC MBASE FC00 0000
$80 PSADD0 8000 FBFF
$84 PSOFF0 & PSATT0 8000 00FX
$88 PSADD1 0000 0000
$8C PSOFF1 & PSATT1 0000 0000
$90 PSADD2 0000 0000
$94 PSOFF2 & PSATT2 0000 0000
$98 PSADD3 0000 0000
$9C PSOFF3 & PSATT3 0000 0000

Configuration

Register Name

Register Value

1-19

1

Board Description and Memory Maps

The next table shows the programmed values for the associated Universe
PCI registers for the PCI PREP memory map.

Table 1-12. Universe PCI Register Values for PREP Memory Map

Configuration

Address Offset

$100 LSI0_CTL C082 5100
$104 LSI0_BS 0100 0000
$108 LSI0_BD 3000 0000
$10C LSI0_TO XXXX 0000
$114 LSI1_CTL C042 5100
$118 LSI1_BS 3000 0000
$11C LSI1_BD 3800 0000
$120 LSI1_TO XXXX 0000
$128 LSI2_CTL 0000 0000
$12C LSI2_BS XXXX XXXX
$130 LSI2_BD XXXX XXXX
$134 LSI2_TO XXXX XXXX
$13C LSI3_CTL 0000 0000

Configuration

Register Name

Register Value

$140 LSI3_BS XXXX XXXX
$144 LSI3_BD XXXX XXXX
$148 LSI3_TO XXXX XXXX
$188 SLSI C0A05338

1-20

VMEbus Mapping

VMEbus Master Map

The processor can access any address range in the VMEbus with the help
from the address translation capabilities of the Universe ASIC. The
recommended mapping is shown in the Processor Memory Map section.
The following figure illustrates how the VMEbus master mapping is
accomplished.

Programming Model

1

1-21

1

Board Description and Memory Maps

ONBOARD

MEMORY

PCI MEMORY

SPACE

PCI/ISA

MEMORY SPACE

PCI

I/O SP AC E

NOTE 1

NOTE 1

PCI MEMORYPROCESSOR

NOTE 2

NOTE 3

VMEBUS

PROGRAMMABLE

SPACE

VME A24

VME A16

VME A24

VME A16

VME A24

VME A16

VME A24

VME A16

MPC

RESOURCES

Notes:

1. Programmable mapping done by the Raven ASIC.

1-22

11553.00 9609

Figure 1-2. VMEbus Master Mapping

Programming Model

2. Programmable mapping via the four PCI Slave Images in the
Universe ASIC.

3. Programmable mapping via the Special Slave Image (SLSI) in the
Universe ASIC.

VMEbus Slave Map

The four programmable VME Slave Images in the Universe ASIC allow
other VMEbus masters to get to any devices on the MVME2600/2700
series. The combination of the four Universe VME Slave Images and the
four Raven PCI Slave Decoders offers a lot of flexibility for mapping the
system resources as seen from the VMEbus. In most applications, the
VMEbus only needs to s ee the syste m memory and , pe rhaps, the so ftware
interrupt registe rs (SI R1 and SIR2 regis ters) . An exampl e of the VMEbus
slave map is shown below:

1

1-23

1

Board Description and Memory Maps

Processor

Onboard

Memory

ISA Space

Software INT

Registers

NOTE 2

NOTE3

PCI Memory

PCI I/O Space

VMEbus

NOTE 1

NOTE 1

1896 9609

Notes:

1. Programmable mapping via the four VME Slave Images in the

2. Programmable mapping via PCI Slave Images in the Raven ASIC.

3. Fixed mapping via the PIB device.

1-24

Figure 1-3. VMEbus Slave Mapping

Universe ASIC.

Programming Model

The following table shows the programmed values for the associated
Universe registers for the VMEbus slave function.

Table 1-13. Universe PCI Register Values for VMEbus Slave Map Example

1

Configuration

Address Offset

$F00 VSI0_CTL C0F2 0001 C0F2 0001
$F04 VSI0_BS 4000 0000 4000 0000
$F08 VSI0_BD 4000 1000 4000 1000
$F0C VSI0_TO C000 1000 C000 1000
$F14 VSI1_CTL E0F2 00C0 E0F2 00C0
$F18 VSI1_BS 1000 0000 1000 0000
$F1C VSI1_BD 2000 0000 2000 0000
$F20 VSI1_TO F000 0000 7000 0000
$F28 VSI2_CTL 0000 0000 0000 0000
$F2C VSI2_BS XXXX XXXX XXXX XXXX
$F30 VSI2_BD XXXX XXXX XXXX XXXX
$F34 VSI2_TO XXXX XXXX XXXX XXXX
$F3C VSI3_CTL 0000 0000 0000 0000

Configuration

Register Name

Register Value

(CHRP)

Register Value

(PREP)

$F40 VSI3_BS XXXX XXXX XXXX XXXX
$F44 VSI3_BD XXXX XXXX XXXX XXXX
$F48 VSI3_TO XXXX XXXX XXXX XXXX

The above register values yield the following VMEbus slave map:

1-25

1

Board Description and Memory Maps

Table 1-14. VMEbus Slave Map Example

VMEbus Address

Range Mode

4000 0000 ­4000 0FFF

1000 0000 ­1FFF FFFF

A32 U/S/P/D
D08/16/32

A32 U/S/P/D
D08/16/32/64
RMW

Size CHRP Map PREP Map

4K P CI/IS A I/O Spac e:

0000 1000 - 0000 1FFF

256M PCI/ISA Memory Space

(On-board DRAM)
0000 0000 - 0FFF FFFF

PCI/ISA I/O Space:
0000 1000 - 0000 1FFF

PCI/ISA Memory Space
(On-board DRAM)
8000 0000 - 8FFF FFFF

1-26

Falcon-Controlled System Registers

The Falcon chipset latches the states of the DRAM data lines onto the
PR_STAT1 and PR_STAT2 registers. The MVME2600/2700 series use
these status registers to provide the system configuration information. In
addition, the Falcon chipset performs the decode and control for an
external register port. This function is utilized by the MVME2600/2700
series to provide the system control registers.

Table 1-15. System Register Summary

0

BIT # ---->
FEF80400
FEF80404

FEF88000

FEF88300

123

System External Cache

Control Register

CPU C

4

5

6789101112131415161718192021222324252627282930

System Configuration Register (Upper Falcon’s PR_STAT1)

Memory Configuration Register (Lower Falcon’s PR_STAT1)

ontrol Register

The following sub-sections describe these system registers in detail.

Programming Model

1

31

1-27

1

Board Description and Memory Maps

System Configuration Register (SYSCR)

The states of the RD[0:31] DRAM data pins, which have weak internal
pull-ups, are l atched by the upper Falcon chip at a ris ing edge of th e power­up reset and stored in this System Configu ration Regist er to provid e some
information about t he system. Configuration is accomplished wit h external
pull-down resistors. This 32-bit read-only register is defined as follows:

REG System Configuration Register - $FEF80400

BIT

FIELD
OPER
RESET

012345678

SYSID SYSCLK SYSXC P0STAT P1STAT

$FE X X X X $F $F

SYSID System Identification. This field specifies the type of the

SYSCLK System Clock Speed. This field relays the syst em clock

SYSCLK Value System Clock Speed PCI Clock Speed

0b0000 to 0b1100 Reserved Reserved

0b1101 50MHz 25MHz
0b1110 60MHz 30MHz
0b1111 66.66MHz 33.33MHz

101112131415161718192021222324252627282930

9

READ ONLY

overall system configuration so that the software may
appropriately hand le any softwa re visible differences . For
the MVME2600/2700 series, this field returns a value of
$FE.

speed and the PCI clock speed information as follows:

31

SYSXC System External Cache S ize. This field reflec ts size of the

0b0000 to 0b1011 Reserved

1-28

look-aside cache on the system bus.

SYSXC Value External Look-aside Cache Size

Programming Model

SYSXC Value External Look-aside Cache Size

0b1100 1M
0b1101 512K
0b1110 256K

0b1111 None

P0/1STAT Processor 0/1 Status. This field is encoded as follows:

1

P0/1STAT Value Processor 0/1 Present

0b0000 to 0b0011 Reserved Reserved

0b0100 YES 1M
0b0101 YES 512K
0b0110 YES 256K

0b0111 YES None

0b1000 to 0b1111 NO N/A

External In-line Cache

Size

1-29

1

Board Description and Memory Maps

Memory Configuration Register (MEMCR)

The states of the RD[00:31] DRAM data pins, which have weak internal
pull-ups, are lat ched by the lowe r Falcon chip a t a rising edge of the power­up reset and s tored in this Memory Configuration Regis ter to provide some
information about the system memory. Configuration is accomplished
with external pull-down re sistors. This 32-bit read-onl y Register is defined
as follows :

REG Memory Configuration Register - $FEF80404

BIT

FIELD

OPER
RESET

32333435363738394041424344454647484950515253545556575859606162

M_FREF

111X1

1

M_SPD0

M_SPD1

X

X

R_A_TYP0

R_A_TYP1

R_A_TYP2

R_B_TYP0

R_B_TYP1

R_B_TYP2

XXX1XXXXXXXXXXXXXXXXXXX

1

M_FREF Block A/B/C/D Fast Refresh. When this bit is set, it

indicates that a DRAM block requires faster refresh rate.
If any of the four blocks requires faster refresh rate then
the ram ref

control bit should be set.

M_SPD[0:1] Memory Speed. This field relays the memory speed

information as follows:

M_SPD[0:1] DRAM Speed DRAM Type

0b00 70ns Past Page
0b01 60ns Fast Page
0b10 Reserved Reserved

63

1-30

0b11 50ns EDO

Programming Model

These two bi ts reflect the co mbined status of the four
blocks of DRAM. Initialization software uses this
information to program the ram_spd0

and ram_spd1

control bits in the Falcon’s Chip Revision Register.

R_A/B_TYP[0:1] ROM/Flash Type. This field is encoded as

follows:

ROM_A/B_TYP[0:2] ROM/FLASH Type

0b000 to 0b101 Reserved

1

0b110

0b111 Unknown type (i.e. ROM/FLASH Sockets)

Intel 16-bit wide FLASH with 16K Bottom Boot
Block

Note: The device width i s dif ferent f rom the widt h of t he FLASH bank . If
the bank width is 64-bit and the device width is 16-bit then the FLASH
bank consists of four FLASH devices.

System External Cache Control Register (SXCCR)

The System Cache Control Register is accessed via the RD[32:39] data
lines of the upper Falcon device. This 8-bit register is defined as follows:

REG System External Cache Control Register - $FEF88000
BIT 0 1 2 3 4 5 6 7

SXC_DIS_

FIELD

OPER R/W

SXC_RST_

SXC_MI_

SXC_FLSH_

RESET 1 1 1 1 X X X X

SXC_DIS_ System External Cache Enable. When this bit is cleared,

it disables this cache from responding to any bus cycles.

1-31

1

Board Description and Memory Maps

SXC_FLSH_System External Cache Flush. When this bit is pulsed

true for at least 8 clock periods, it causes the system
external cache to write back dirty cache lines out to
system memory and clears all the tag valid bits. This

operation causes the Glance pair to r eque st and hold the
MPC bus until it has completed the flush operation
(approximately 4100 clock cycles). This may be an issue
if other devices cannot wait that long to become MPC bus
master .

SXC_RST_System External Cache Reset. When this bit is cleared, it

invalidates all tags and holds the cache in a reset
condition. There is a bug in Glance - It really does not

hold the chip in a reset condition. The tag invalidate still
works okay though.

SXC_MI_ System External Cache Miss Inhibit. When this bit is

cleared, it prevents line fills on cache misses.

Software should never clear more than one of these bi ts at the

!

Warning

same time. If more than one is cleared at the same time, the
Glance pair behaves indeterminately.

1-32

Programming Model

CPU Control Register

The CPU Control Register is accesse d via the RD[32 :39] dat a lines of the
upper Falcon device. This 8-bit register is defined as follows:

REG CPU Control Register - $FEF88300
BIT 0 1 2 3 4 5 6 7

LEMODE

FIELD

OPER R R R/W R/W R R R R
RESET X 0 1 1 X X X X

P1_TBEN

P0_TBEN

LEMODE Little Endian Mode. This bit must be set in conjunction

with the LEND bit in the Raven for little-endian mode.

P0/1_TBENProcessor 0/1 T ime Base Enable . When this bit is clea red,

the TBEN pin of Processor 0/1 will be driven low.

1

1-33

1

Board Description and Memory Maps

ISA Local Resource Bus

W83C553 PIB Registers

The PIB contains ISA Bridge I/O registers for various functions. These
registers are actually accessible from the PCI bus. Refer to the W83C553
Data Book for details.

PC87308VUL Super I/O (ISASIO) Strapping

The PC87308VUL Super I/O (ISASIO) provides the following functions
to the MVME2600/2700 series: a keyboard interface, a PS/2 mouse
interface, a PS/2 floppy port, two async serial ports and a parallel port.
Refer to the PC87308VUL Data Sheet for additional details and
programming information.

The following table shows the hardware strapping for the Super I/O
device:

Table 1-16. Strap Pins Configuration for the PC87308VUL

Pins Reset Configuration

CFG0 0 - FDC, KBC and RTC wake up inactive.
CFG1 1 - Xbus Data Buffer (XDB) enabled.

CFG3, CFG2 00 - Clock source is 24MHz fed via X1 pin.

BADDR1, BADDR2 11 - PnP Motherboard, Wake in Config State. Index $002E.

SELCS 1 - CS0# on CS0# pin.

NVRAM/RTC & Watchdog Timer Registers

The MK48T59/559 provides t he MVME2600/2700 s eries wit h 8K of non ­volatile SRAM, a time-of-day clock, and a watchdog timer. Accesses to
the MK48T59559 are accomplished via three registers: The
NVRAM/RTC Address Strobe 0 Register, the NVRAM/RTC Address

1-34

ISA Local Resource Bus

Strobe 1 Register, and the NVRAM/RTC Data Port Register. The
NVRAM/RTC Address Strobe 0 Register latches the lower 8 bits of the
address and the NVRAM/RTC Ad dress Strobe 1 Register latches the upper
5 bits of the address.

Table 1-17. MK48T59/559 Access Registers

PCI I/O Address Function

0000 0074 NVRAM/RTC Address Strobe 0 (A7 - A0)
0000 0075 NVRAM/RTC Address Strobe 1 (A15 - A8)
0000 0077 NVRAM/RTC Data Register

The NVRAM and RTC is accessed through the above three registers.
When accessing a NVRAM/RTC location, follow the following
procedure:

1. Write the low address (A7-A0) of the NVRAM to the
NVRAM/RTC STB0 register,

1

2. Write the high address (A15-A8) of the NVRAM to the
NVRAM/RTC STB1 register, and

3. Then read or write the NVRAM/RTC Data Port.

Refer to the MK48T59 Data Sheet for addit ional detai ls and programmi ng
information.

Module Configuration and Status Registers

Four registers provide the configuration and status information about the
board. These registers are listed in the following table:

1-35

1

Board Description and Memory Maps

Table 1-18. Module Configuration and Status Registers

PCI I/O Address Function

0000 0800 CPU Configuration Register
0000 0802 Base Module Feature Register
0000 0803 Base Module Status Register
0000 08C0 - 0000 08C1 Seven-Segment Display Register

The following sub sections describe these registers in detail.

CPU Configuration Register

The CPU Configuration Register is an 8-bit register located at ISA I/O
address x0800. This register is def ined for the MVME2600/ 2700 series to
provide some backward compatibility with older MVME1600 products.
The Base Module Status Register should be used to identify the base
module type and the System Configuration Register should be used to
obtain information about the overall system.

REG Old CPU Configuration Register - $FE000800

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

FIELD CPUTYPE

OPER R R

RESET $E $F

CPUTYPE CPU Type. This field will always read as $E for the

MVME2600/2700 series. The System Configuration
Register should be used for additional information.

1-36

ISA Local Resource Bus

Base Module Feature Register

The Base Module Feature Register is an 8-bit register providing the
configuration info rmation about th e Genesis Single Board Computer. This
read-only register is located at ISA I/O address x0802.

REG Base Module Feature Register - Offset $0802

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

FIELD

OPER R R R R R R R R

RESET X X X X X X X X

SCCP_

PMC2P_

PMC1P_

VMEP_

GFXP_

LANP_

SCCP_ Z85230 ESCC Present. If set, there is no on-board sync

serial support. If cleared, there is on-board support for
sync serial interface.

1

SCSIP_

PMC2P_ PMC/PCIX Slot 2 Present. If set, there is no PMC/PCIX

device installed in the PMC/PCIX Slot 2. If cleared, the
PMC/PCIX Slot 2 contains a PCI Mezzanine Card or a
PCI device.

PMC1P_ PMC Slot 1 Present. If set, there is no PCI Mezzanine

Card installed in the PMC Slot 1. If cleared, the PMC Slot
1 contains a PMC.

VMEP_ VMEbus Present. If set, ther e i s no VM Ebus int er fac e. I f

cleared, VMEbus interface is supported.

GFXP_ Graphics Present. If set, there is no on-board Graphics

interface. If cleared, there is an on-board graphics
capability.

LANP_ Ethernet Present. If set, there is no Ethernet transceiver

interface. If cleared, there is on-board Ethernet su pport.

1-37

1

Board Description and Memory Maps

SCSIP_ SCSI Present. If set, there is no on-board SCSI interface.

If cleared, on-board SCSI is supported.

Base Module Status Register (BMSR)

The Base Module Status Register is an 8-bit read-only register located at
ISA I/O address x0803.

REG Base Module Status Register - Offset $0803

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

FIELD BASE_TYPE

OPER R

RESET N/A

BASE_TYPEBase Module Type. This eight bit field is used to

provide the category of the base mo dule and is def ined as
follows:

1-38

BASE_TYPE Value Base Mo dule Type

$0 to $F9 Reserved

$FA
$FB MVME2600/2700 with MVME712M I/O

$FC MVME2600/2700 with MVME761 I/O
$FD MVME3600 with MVME712M I/O
$FE MVME3600 with MVME761 I/O
$FF MVME1600-001 or MVME1600-011

Reserved -- Special with MVME712M I/O and

100BaseT4 on row Z

ISA Local Resource Bus

Seven-Segment Display Register

This 16-bit register allows data to be sent to the 4-digit hexadecimal
diagnostic display. The register al so a ll ows the data to be read
back.

REG 7-Segment Display Register - Offset $08C0

SD15

SD14

SD13

BIT

FIELD DIG3[3:0] DIG2[3:0] DIG1[3:0] DIG0[3:0]
OPER R/W

RESET X X X X X X X X X X X X X X X X

SD12

SD10

SD11

SD9

SD8

SD7

SD6

SD5

SD4

SD3

SD2

SD1

DIG3[3:0] Hexadecimal value of the most significant digit.
DIG2[3:0] Hexadecimal value of the third significant digit.
DIG1[3:0] Hexadecimal value of the second significant digit.

1

SD0

DIG0[3:0] Hexadecimal value of the least significant digit.

VME Registers

The following registers provide the following functions for the VMEbus
interface: a software interrupt capability, a location monitor function, and
a geographical a ddress st atus. For these regist ers to b e accessi ble fro m the
VMEbus, the Universe ASIC must be programmed to map the VMEbus
Slave Image 0 into the appropriate PCI I/O address range. Refer to the
VMEbus Slave Map section for additional details. The following table
shows the registers provided for various VME functions:

1-39

1

Board Description and Memory Maps

Table 1-19. VME Registers

PCI I/O Address Function

0000 1000 SIG/LM Control Register
0000 1001 SIG/LM Status Register
0000 1002 VMEbus Location Monitor Upper Base Address
0000 1003 VMEbus Location Monitor Lower Base Address
0000 1004 VMEbus Semaphore Register 1
0000 1005 VMEbus Semaphore Register 2
0000 1006 VMEbus Geographical Address Status

These registers are described in the following sub-sections.

LM/SIG Control Register

The LM/SIG Control Register is an 8-bit register located at ISA I/O
address x1000. This register provides a method to generate software
interrupts. The Universe ASIC is programmed so that this register can be
accessed from the VMEbus to generate software interrupts to the
processor(s).

REG LM/SIG Control Register - Offset $1000

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

FIELD SET

SIG1

OPER WRITE-ONLY

RESET 0 0 0 0 0 0 0 0

SET

SIG0

SET
LM1

SET
LM0

CLR

SIG1

CLR

SIG0

CLR
LM1

CLR
LM0

SET_SIG1 Writing a 1 to this bit will set the SIG1 status bit.
SET_SIG0 Writing a 1 to this bit will set the SIG0 status bit.

1-40

ISA Local Resource Bus

SET_LM1 Writing a 1 to this bit will set the LM1 status bit.
SET_LM0 Writing a 1 to this bit will set the LM0 status bit.
CLR_SIG1Writing a 1 to this bit will clear the SIG1 status bit.
CLR_SIG0Writing a 1 to this bit will clear the SIG0 status bit.
CLR_LM1 Writing a 1 to this bit will clear the LM1 status bit.
CLR_LM0 Writing a 1 to this bit will clear the LM0 status bit.

LM/SIG Status Register

The LM/SIG Status Registe r is an 8-bit regi ster locate d at ISA I/O address
x1001. This register, in conjunction with the LM/SIG Control Register,
provides a method to generate interrupts. The Universe ASIC is
programmed so that this register can be accessed from the VMEbus to
provide a capability to generate software interrupts to the onboard
processor(s) from the VMEbus.

REG LM/SIG Status Register - Offset $1001

1

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

FIELD EN

SIG1

OPER R/W READ-ONLY

RESET 0 0 0 0 0 0 0 0

EN

SIG0

EN

LM1

EN

LM0

SIG1 SIG0 LM1 LM0

EN_SIG1 When the EN_SIG1 bit is set, a LM/SIG Interrupt 1 is

generated if the SIG1 bit is asserted.

EN_SIG0 When the EN_SIG0 bit is set, a LM/SIG Interrupt 0 is

generated if the SIG0 bit is asserted.

EN_LM1 When the EN_LM1 bit is set, a LM/SIG Interrup t 1 is

generated and the LM1 bit is asserted.

EN_LM0 When the EN_LM0 bit is set, a LM/SIG Interrup t 0 is

generated and the LM0 bit is asserted.

1-41

1

Board Description and Memory Maps

SIG1 SIG1 status bit. This bit can only be set by the SET_LM1

control bit. It can onl y be cle ar ed by a reset or by writing
a 1 to the CLR_LM1 control bit.

SIG0 SIG0 status bit. This bit can only be set by the SET_LM0

control bit. It can onl y be cle ar ed by a reset or by writing
a 1 to the CLR_LM0 control bit.

LM1 LM1 status bit. This bit can be set by either the location

monitor function or the SET_LM1 control bit. LM1
correspond to offset 3 from the location monitor base
address. This bit can only be cleared by a reset or by
writing a 1 to the CLR_LM1 control bit.

LM0 LM0 status bit. This bit can be set by either the location

monitor function or the SET_LM0 control bit. LM0
correspond to offset 1 from the location monitor base
address. This bit can only be cleared by a reset or by
writing a 1 to the CLR_LM0 control bit.

Location Monitor Upper Base Address Register

The Location Monitor Upper Base Address Register is an 8-bit register
located at ISA I/O address x1002. The Universe ASIC is programmed so
that this register can be accessed from the VMEbus to provide VMEbus
location monitor function.

REG Location Monitor Upper Base Address Register - Offset $1002

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

FIELD VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8

OPER R/W

RESET 0 0 0 0 0 0 0 0

VA[15:8] Upper Base Address for the location monitor function.

1-42

ISA Local Resource Bus

Location Monitor Lower Base Address Register

The Location Monitor Lower Base Address Register is an 8-bit register
located at ISA I/O address x1003. The Universe ASIC is programmed so
that this register can be accessed from the VMEbus to provide VMEbus
location monitor function.

REG Location Monitor Lower Base Address Register - Offset $1003

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
FIELD VA7 VA6 VA5 VA4 LMEN
OPER R/W R R R

RESET 0 0 0 0 0 0 0 0

VA[7:4] Lower Base Address for the location monitor function.
LMEN This bi t must be set to enable the location monitor

function.

1

Semaphore Register 1

The Semaphore Register 1 is an 8-bit register located at ISA I/O address
x1004. The Universe ASIC is programmed so that this register can be
accessible from the VMEbus. This register can only be updated if bit 7 is
low or if the new value has the most significant bit cleared. When bit 7 is
high, this register will not latch in the new value if the new value has the
most significant bit set.

REG Semaphore Register 1 - Offset $1004

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
FIELD SEM1
OPER R/W

RESET 0 0 0 0 0 0 0 0

1-43

1

Board Description and Memory Maps

Semaphore Register 2

The Semaphore Register 2 is an 8-bit register located at ISA I/O address
x1005. The Universe ASIC is programmed so that this register can be
accessible from the VMEbus. This register can only be updated if bit 7 is
low or if the new value has the most significant bit cleared. When bit 7 is
high, this register will not latch in the new value if the new value has the
most significant bit set.

REG Semaphore Register 2 - Offset $1005

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

FIELD SEM2

OPER R/W

RESET 0 0 0 0 0 0 0 0

VME Geographical Address Register (VGAR)

The VME Geographical Address Register is an 8-bit read-only register
located at ISA I/O address x1006. This register reflects the states of the
geographical address pins at the 5-row, 160-pin P1 connector.

REG VME Geographical Address Register - Offset $1006

BIT SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

FIELD GAP# GA4# GA3# GA2# GA1# GA0#

OPER READ ONLY

RESET X X X X X X X X

Z85230 ESCC and Z8536 CIO Registers and Port Pins

The Z85230 ESCC is used to provide the two sync/async serial ports on
some MVME2600/2700 series models. The PCLK which can be used to

derived the baud rates, is 10 MHz. Refer to the SCC User’s Manual for
programming information on the Z85230 ESCC device.

1-44

The Z8536 CIO is used to provide the modem control lines not provided
by the Z85230 ESCC and a method to inquire the module ID of the two
sync/async seria l port s that resi de o n the MVME76 1 module. Re fe r to th e
Z8536 Data Sheet for programming information.

Z8536/Z85230 Registers

Accesses to the Z8536 CIO and the Z85230 ESCC are accomplished via
Port Control and Port Data Registers. The PCLK to the Z8536 is 5 MHz.
Also, a Pseudo IACK Register is also de fined to retri eve int errup t vecto rs
from these devices. The Z8536 CIO has higher priority than the Z85230
ESCC in the interrupt daisy chain. The following list the registers
associated with accessing these two devices:

Table 1-20. Z8536/Z85230 Access Registers

PCI I/O Address Function

0000 0840 Z85230: Port B (Serial Port 4) Control
0000 0841 Z85230: Port B (Serial Port 4) Data

ISA Local Resource Bus

1

0000 0842 Z85230: Port A (Serial Port 3) Control
0000 0843 Z85230: Port A (Serial Port 3) Data
0000 0844 Z853 6 CIO: Port C’s Data Regist er

0000 0845 Z8536 CIO: Port B’s Data Register
0000 0846 Z8536 CIO: Port A’s Data Register
0000 0847 Z8536 CIO: Control Register
0000 084F Z85230/Z8536 Pseudo IACK

1-45

1

Board Description and Memory Maps

Z8536 CIO Port Pins

The assignment for the Port pins of the Z8536 CIO is as follows:

Table 1-21. Z8536 CIO Port Pins Assignment

Port

Pin

PA0 TM3_

PA1 DSR3_

PA2 RI3_ Input Port 3 Ring Indicator
PA3 LLB3_

PA4 RLB3_ Output Port 3 Remote Loopback
PA5 DTR3_ Output P ort 3 Data Terminal Ready
PA6 BRDFAIL Output Board Fail: When set will cause FAIL LED to be lit.
PA 7 IDREQ_ Output Module ID Request - low true
PB0 TM4_

PB1 DSR4_

Signal
Name

MID0

MID1

MODSEL

MID2

MID3

Direction Descriptions

Input Port 3 Test Mode when IDREQ_ = 1;

Module ID Bit 0 when IDREQ_ = 0.

Input Port 3 Data Set Ready when IDREQ_ = 1;

Module ID Bit 1 when IDREQ_ = 0.

Output Port 3 Local Loopback (IDREQ_ = 1) or

Port Select (IDR EQ_ = 0):

IDREQ_ = 0 & MODSEL = 0 => Port 3 ID Select
IDREQ_ = 0 & MODSEL = 1 => Port 4 ID Select

Input Port 4 Test Mode when IDREQ_ = 1;

Module ID Bit 2 when IDREQ_ = 0.

Input Port 4 Data Set Ready when IDREQ_ = 1;

Module ID Bit 3 when IDREQ_ = 0.
PB2 RI4_ Input Port 4 Ring Indicator
PB3 LLB4_ Output Port 4 Local Loopback
PB4 RLB4_ Output Port 4 Remote Loopback
PB5 DTR4_ Output Port 4 Data Terminal Ready
PB6 FUSE Input FUSE = 1 means that at least one of the fuses or

PB7 ABORT_ Input Status of ABORT# signal

1-46

polyswitches is open.

ISA Local Resource Bus

Table 1-21. Z8536 CIO Port Pins Assignment (Continued)

1

Port

Pin

PC0 Reserved I/O Reserved
PC1 Reserved I/O Reserved
PC2 Reserved I/O
PC3 Reserved I/O

Signal

Name

Direction Descriptions

Reserved

NOTE: The direction and the polarity of th e Z8536’s port pins are software
programmable.

1-47

1

Board Description and Memory Maps

The module ID signals, which are only valid when IDREQ_ is asserted,
indicate the type of the serial module that is installed on either Port 3 or
Port 4. The following table shows how to interpret the MID3-MID0
signals:

Table 1-22. Interpretation of MID3-MI D 0

MID3

MID2

MID1

IDREQ_

1 X XXXXInvalid module ID
0 0 0 0 0 0 Module 3: EIA232 DCE 01-W3876B01
0 0 0 0 0 1 Module 3: EIA232 DTE 01-W3877B01
0 0 0 0 1 0 Module 3: EIA530 DCE 01-W3878B01
0 0 0 0 1 1 Module 3: EIA530 DTE 01-W3879B01
0 0 1 1 1 1 Module 3 Not Installed
0 1 0 0 0 0 Module 4: EIA232 DCE 01-W3876B01

LLB3_

MODSEL

MID0

Serial Module Type

Module

Assembly

Number

0 1 0 0 0 1 Module 4: EIA232 DTE 01-W3877B01
0 1 0 0 1 0 Module 3: EIA530 DCE 01-W3878B01
0 1 0 0 1 1 Module 3: EIA530 DTE 01-W3879B01
0 1 1 1 1 1 Module 4 Not Installed

Note Because IDREQ_ and MID3-MID0 signals go through the

P2MX (P2 multiplexing) function used on
MVME2600/2700 series modules configured for the
MVME761-type transition module, software must wait for
the MID3-MID0 to become valid afte r asserting IDREQ_.
The waiting time should be about 4 microseconds because
the sampling rate is about 1.6 microsecond with a 10MHz
MXCLK clock.

1-48

ISA DMA Channels

There are seven ISA DMA channels in the PIB. Channels 0 through 3
support only 8-bit DMA devices whi le Channels 5 through 7 suppor t only
16-bit DMA devices. These DMA channels are assigned as follows:

Table 1-23. PIB DMA Channel Assignments

ISA Local Resource Bus

1

PIB

Priority

Highest Channel 0 DMA1 Serial Port 3 Receiver (Z85230 Port A Rx)

Lowest Channel 7 Not Used

PIB Label Controller DMA Assignment

Channel 1 Serial Port 3 Transmitter (Z85230 Port A Tx)
Channel 2 Floppy Driv e Control ler
Channel 3 Paralle l Por t
Channel 4 DMA2 Not available - Cascaded from DMA1
Channel 5 Serial Port 4 Receiver (Z85230 Port B Rx)
Channel 6 Serial Port 4 Transmitter (Z85230 Port B Tx)

Note Because the Z85230 is an 8-bit device and Channels 5 and 6

are 16-bit DMA Channels, only every other byte (the even
bytes) from memory is valid .

1-49

1

Board Description and Memory Maps

1-50

2Raven PCI Host Bridge & Multi-

Processor Interrupt Controller Chip

Introduction

Overview

This document describes the architecture and usage of the Raven, a
PowerPC to PCI Local Bus Bridge ASIC. The Raven is intended to
provide MPC60x compliant devic es acce ss to device s resi ding on th e PCI
Local Bus in a very efficient manner. In the remainder of this chapter, the
MPC60x bus will be re ferr ed to as th e MPC b us and th e PCI Loc al Bus as
PCI.

No manufacturer currently has plans to support the MPC bus directly.
Therefore, some alternative I/O bus will be necessary in any PowerPC
product. This I/O bus must be robust and efficient enough to handle the
high bandwidth, burst oriented traffic required for Ethernet, SCSI,
graphics, and VMEbus interfaces.

PCI is a high performance 32-bit or 64-bit, burst mode, synchronous bus
capable of transfer rates of 132 MByte/sec in 32-bit mode or 264
MByte/sec in 64-bit mode. While the PCI spec ification is relatively new,
it has received overwhelming support among PC clone manufacturers.
Many peripheral device manufacturers have designed PCI Local Bus
compliant products. NCR tested a PCI SCSI con troller and a PCI Ether net
controller. Ethernet controllers from AMD and National Semiconductor
are available. Graphics controllers are available from Trident, S3, Oak
Technologies, Weitek, Chips and Technologies, Headland Technologies,
and NCR.

2

2-1

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

Requirements

The Raven must provide a high throughput interface between multiple
MPC60x processors and 32/64-bit PCI local bus. It must be capable of
supporting up to two MPC60x processors and contain a multiprocessing
interrupt st ructur e to eff icie ntly di stri bute inter rupts d ynamical ly b etwe en
these processors.

Features

❏ MPC Bus Interface

– Direct interface to MPC601, MPC603 or MPC604 processors.
– 64-bit data bus, 32-bit address bus.
– Optional bus arbitr ation logic supporting up to three bus mast ers.
– Four independent software programmable slave map decoders.
– Multi-le vel write post FI FO for writes to PCI.
– Support for MPC bus clock speeds up to 66 MHz.
– Selectable big or little endian operation.

❏ PCI Interface

– Fully PCI Rev. 2.0 compliant.
– 32-bit or 64-bit address/data bus.

2-2

– Support for accesses to all four PCI address spaces.
– Single-level write posting buffers for writes to the MPC bus.
– Read-ahead buffer for reads from the MPC bus.
– Four independent software programmable slave map decoders.

❏ Interrupt Controller

– MPIC compliant.
– Support for 16 external interrupt sources and two processors.
– Multiprocessor i nterrupt control allowing any inter rupt source to

be directed to either processor.

– Multilevel cross processor interrupt control for multiprocessor

synchronization.

Introduction

– Four 31 b it tick timers.

❏ Two 64-bit general purpose registers for cross-processor

messaging.

2

2-3

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

Block Diagram

PCI Master

MPIC

PCI Bus

PCI Regs

Mux PCI

Data Path ‘A’

Reg

Mux

FIFO

Endian

Mux

Reg

Mux MPC

Mux

FIFO

Endian

Data Path ‘B’

Mux

MPC Master

MPC Regs

MPC Arbiter

MPC Bus

2-4

PCI Dec

PCI Slave

Reg

PCIADIN

Reg

MPC Dec

MPC Slave

Raven

1914 9610

Figure 2-1. Raven Block Diagram

Functional Description

Functional Description

MPC Bus Interface

The MPC Bus Interface is designed to be coupled directly to up to two
MPC601, MPC603, or MPC604 microprocessors as well as a
memory/cache subsystem. It uses a subset of the capabilities of the
MPC60x bus protocol.

MPC Arbiter

The MPC Arbiter is an optional feature in the Raven. The Raven MPC
Arbiter is enabled i f both CPUID pi ns are sampl ed high on t he rising edg e
of RST*. When this feature is enabled, the MARB bit in the General
Control/Status Register (GCSR) will be set. When this feature is not
enabled, the MARB bit will be cleared and the Raven will be configured
for external arbitration.

The MPC Arbiter function is responsible for determining address bus
ownership. The MPC Arbiter function does not provide data bus
arbitration. Determining data bus ownership is the responsibility of each
MPC master and follows the ownership ordering established on the
address bus.

2

The MPC Arbiter supports a total of four participants. One participant is
the Raven MPC master function, which represents PCI initiated MPC
transactions. The remaining three participants are external to the Raven,
and are represented as request/grant signal pairs.

The MPC Arbiter supports a mixture of Fixed Priority and Round-Robin
Priority arbitration schemes. PCI initiated transactions will always have
the highest priority over all external requests. The external requests will be
honored in a Round-Robin algorithm. This al gorithm enforces fairness fo r
bus ownership by assigning the lo west priority t o the most rec ently granted
bus requester. If a bus requester is not granted bus ownership during an
arbitration even t, the priority of that r equester will be increased f or the next
arbitration event.

2-5

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

bits in the MPC Arbiter Control Register (MARB). Following reset, all
requests will be enabled.

The MPC Arbiter supports optional bus parking in order to reduce
arbitration latency. If bus parking is enabled, then one of two modes may
be selected. The arbiter can be configured to grant the bus to the last

selected master, or it can be configured to grant the bus to one “default”
device. The parking enable , parking mode a nd defa ult mas ter inf ormatio n
is represented as control bits within the MARB register.

There is a special ‘Glance Mode’ incorporated into the MPC Arbiter
design. This mode was designed to compensate for an undesirable
characteristi c associate d with early r elease Glance look-aside cache chip s.
Under certain conditions, the Glance would not maintain single-level
pipelined operation when the Raven was MPC bus master. When Glance
Mode is enabled, the MPC Arbiter tr acks address and data tenure s and will
grant bus ownership to non-Rav en bus masters in a manner that guara ntees
single-level pipelined depth. This mode is controlled by the GLMD bit
within the MPC Arbiter Control register. The default state is to have this
mode disabled.

There is another special mode called ‘Benign Address Retry Mode’. This
mode was designed to compensate for an anomaly discovered when
running a PPC603 and a pair of early release Falcon memory controllers.
It is possible that conte ntion of the PPC603 single por t cache tag memory
causes the PPC603 to issue a false (benign) address retry. Under certain
circumstances, these benign address retry cycles would create problems
with Falcon. When the Benign Address Retry Mode is enabled, the MPC
Arbiter will be watching for benign address retry cycles. When one is
detected, the arbiter will hold-off all non-Raven bus masters for a short
period of time. This mode is controlled by the BAMD bit within the MPC
Arbiter Control register. The default state is to have this mode enabled.

Each external reque st can be individually ena bled or disabled using cont rol

A side benefit of the Benign Address Retry Mode is that it provides a
possible solution to a k nown live- lock con dition t hat can happen whe n the
603 is executing a tig ht loop out of cach e and another ma ster is atte mpting
to transfer a coheren t ca che line to or from memory. The Benign Addres s
Retry Mode effectively introduces jitter between the contesting
participants.

2-6

Functional Description

MPC Map Decoders

The Raven address decoders have been designed to be as flexible as
possible to provide a wide range of addre ssing possi bilities . There are five
address map decoders in the Raven which determine the MPC bus
addresses to which the Raven will respond: the MPC Register File
Decoder, and four programmable decoders. Table 2-1 shows a typical
CHRP compliant memory map. (Another si milar map is shown i n Table 1-

3.)

Table 2-1. CHRP Compliant Memory Map

MPC Address Function

$00000000-$7FFFFFFF System Memory (2G)
$80000000-$FCFFFFFF PCI Memory (2G - 48M)
$FD000000-$FDFFFFFFF ISA Memory (16M )
$FE000000-$FE7FFFFF Discontiguous PCI IO (8M)
$FE800000-$FEBFFFFF Contiguous PCI IO (4M)
$FEC00000-$FEF7FFFF reserved (3.5M)
$FEF80000-$FEF8FFFF Falcon 0 Registers (64K)

2

$FEF90000-$FEF9FFFF Falcon 1 Registers (64K)
$FEFA000 0-$ F EFAFFFF Falcon 2 Registers (64K)
$FEFB0000-$FEFBFFFF Falcon 3 Registers (64K)
$FEFC0000-$FEFEFFFF reserved (192K)
$FEFF0000-$FEFFFFFF Raven Registers (64K) (EXT00 => 0)
$FF000000-$FFFFFFFF System ROM /Fl as h (16MB)

The MPC Register File decoder determines the address location of the

Raven’s MPC registers from the MPC bus. These registers may be
accessed using only 1-, 2- , 3-, 4-, or 8-b yte operat ions. The loc ation of t he
MPC register file is fixed beginning at MPC address $FEFE0000 or
$FEFF0000, depending on the state of the EXT01 bit at the time RST* is

2-7

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

file will start at address $FEFE0000. If the EXT01 pin is sampled in the
high state, the MPC register file will start at address $FEFF0000. All
references to the MPC register file within this specification will assume a
base address of FEFF0 000. All Raven re gisters are described in d etail later
in this chapter.

The Raven includes four programmable decoders which control accesses
from the MPC bus to the PCI bus. These dec ode rs pr ovi de a window into
the PCI bus from the MPC bus. The most significant 16 bits of the MPC
address are compared with the address range of each map decoder, and if
the address fal ls with in the s pecif ied range , the acc ess is passed on to PCI .
For each map, there is an associated set of attributes. These attributes are
used to enable read accesses, enable write accesses, enable write posting,
and define the PCI t ransfer characteri stics. Each map decoder also includes
a programmable 16-bit address offset. The offset is added to the 16 most
significant bits of the MPC address, and the result is used as the PCI
address. This offset allows PCI devices to reside at any PCI address,
independent of the MPC address map.

Care should be taken to assure that all programmable decoders decode
unique address ranges. Ove rlapp ing addr ess ra nges wil l lea d to undef ined
operation.

released. If the EXT01 pin is sampled in the low state, the MPC regist er

MPC Write Posting

The MPC writ e FIFO stores u p to eight data beats in any combination of
single- and burst trans actions. If writ e posting is e nabled, Raven st ores the
data necessary to complete an MPC write transfer to the PCI bus and
immediately ackno wledges the tra nsaction on th e MPC bus. This f rees the
MPC bus from waiting for the potent ially long PCI arbitration and transfer.
The MPC bus may be used for more useful work whil e the Raven manages
the completion of the write posted transaction on PCI.

If the write post FIFO is full, any other accesses to the Rav en ar e de lay ed
(AACK* will not be asserted) until there is room in the FIFO to store the
complete transaction.

2-8

Functional Description

MPC Master

All write posted tra nsfers will be complete d before a non-write post ed read
or write is begun to assure that all transfers are completed in the order
issued. All write posted t ransfers will al so be completed befor e any access

to the Raven’s registers is begun.

Wherever possible, the MPC master will attempt to consolidate data
movement into a pair of burst transfers called couplets. If th ere is not
enough data movement to pe rform a couple t, the MPC master will attempt
singular burst transfer s. The MPC master will perform single beat tr ansfers
as required during all non-cache aligned writes and some non-cache
aligned reads. A 64-bit by 16 entry FIFO is used to hold data between the
PCI slave and the MPC master to ensure that optimum data throughput is
maintained. While the PCI slave is filling the FIFO with one cache line
worth of data, the MPC master can be moving another cache line worth
onto the MPC bus. This will allow the PCI slave to receive long block
transfers without stalling.

When programmed in “read ahead” mode (the RAEN bit in the PSATTx
register is set) and the PCI slave rec eives a Memory Read Li ne or Memory
Read Multiple command, the MPC mas ter will fetch data in bursts and
store it in the FI FO. The con tents of th e FIFO wil l th en be us ed to att empt
to satisfy the data requirements for the remainder of the PCI block
transaction. If the data requested is not in the FIFO, the MPC master will
read another cache lin e. The cont ent s of the FIFO are “invalidated” at the
end of each PCI block transaction.

2

Notes 1. Read ahead mode sho uld not be used when data coherency

The MPC bus transfer types generated by the MPC master depend on the
PCI command code and the INV bit in the PSATTx registers.

may be a problem as there is no way to snoop all MPC bus
transactions and invalidate the contents of the FIFO.

2. Accesses near the top of local memory with read-ahead
mode enabled could cau se the MPC maste r to perf orm read s
beyond the top of local memory which could result in an
MPC bus timeout error.

2-9

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

Table 2-2. MPC Transfer Types

PCI Command Code INV

Memory Read,
Memory Read
Multiple,
Memory Read Line

Memory Read,
Memory Read
Multiple,
Memory Read Line

Memory Write,
Memory Write and
Invalidate

Memory Write,
Memory Write and
Invalidate

The MPC master incorporate s an optional operating mode cal led Bus Hog.
When Bus Hog is enabled, the MPC master will continually request the
MPC bus for the entire dura tion of each PCI transfer. When Bus Hog is not
enabled, the MPC master will structure its bus request actions around its
desire to perform couplets. This means the bus request will be deasserted
between couplets. Caution sh ould be exercised when using this mode si nce
the over-generosity of bus ownership to the MPC master can be

detrimental to the host CPU’s performance. The Bus Hog mode can be
controlled by the BHOG bi t within the GCSR. T he default sta te for BHOG
is disabled.

MPC Transfer
Type

0 Read Burst/Single Beat 01010

1 Read With Intent to

Modify

x Write with Kill Burst 00110

x Write with Flush Single Beat 00010

MPC Transfer Size TT0-TT4

Burst/Single Beat 01110

MPC Bus Timer

The MPC bus timer allows the current bus master to reco ver from a lock ­up condition caused when no slave responds to the transfer request.

The time-out length of the bus timer i s determined by t he MBT field in th e
Global Control/Status Register.

2-10

Functional Description

The bus timer starts ticking at the beginning of an address transfer (TS*
asserted), and if the address transfer is not terminated (AACK* asserted)
before the time -out period h as passed, the Raven will a ssert the M ATO bit
in the MPC Error Status Register, latch the MPC address in the MPC Error
Address Register, and then immediately assert AACK*.

The MATO bit may be configured to generate an interrupt or a machine
check through the MEREN register.

The timer is disabled if the transfer is intended for PCI. PCI bound
transfers will be timed by the PCI master.

PCI Interface

The Raven PCI Interface is desi gned to connect directly to a PCI Loca l Bus
compliant I/O bus.

The PCI interface may operate at any clock speed up to 33 MHz. The
PCLK input must be externally synchronized with the MCLK input, and
the frequency of the PCLK input must be exactly hal f the frequency of the
MCLK input.

PCI Map Decoders

2

The Raven contains four prog rammable decod ers which provide win dows
into the MPC bus from the PCI bus. The most significant 16 bits of the PCI
address is compare d with the address ra nge of each map decoder , and if the
address falls withi n the specified range, the acce ss is passed on to the MPC
bus. For each map, there is an independent set of attributes. These
attributes are used to enable read accesses, enable write accesses, enable
write posting, and define the MPC bus transfer characteristics. Each map
decoder also includes a programmable 16-bit address offset. The offset is
added to the 16 most significant bits of the PCI address, and the result is
used as the MPC address. This offse t allows devices to reside at any MPC
address, independent of the PCI address map.

All Raven address decoders are prioritized so that programming multiple
decoders to respond to the same address will not be a problem. When the
PCI address fall s into the range of more than one decoder, only the high est
priority one will respond. The decoders are prioritized as shown below.

2-11

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

:

Decoder Priority

PCI Slave 0 highest
PCI Slave 1
PCI Slave 2
PCI Slave 3 lowest

PCI Configuration Space

The Raven does not have an IDSEL pin. An internal connection is made
within the Raven that logi cally assoc iates t he ass erti on of I DSEL with the
assertion of either AD30 or AD31. The exact association depends on the
state of the EXT02 pin when the RST* pin is released. If EXT02 is
sampled low, the Raven will associate AD30 with IDSEL. If EXT02 is
sampled high, the Raven will associate AD31 with IDSEL.

PCI Write Posting

If write posting is enabled, the Raven sto res the ta rge t addr es s, att ri but es ,
and up to 128 bytes of data from one PCI write transaction and
immediately acknowled ges the transaction on the PCI bus. This allows t he
slower PCI to continue to transfer data at its maximum bandwidth, and the
faster MPC bus to accept data in high performance cache-line burst
transfers.

Only one PCI transaction may be write posted at any given time. If the
Raven is busy processing a previous write posted transa ct ion when a new
PCI transaction begin s, t he next PCI transaction will be de la yed ( TRDY*
will not be asserte d) until the previou s transaction has compl eted. If during
a transaction the write post buffer gets full, subsequent PCI data transfers
will be delayed (TRDY* will not be asserted ) until the Raven has r emoved
some data from the FIFO. Under normal conditions, the Raven should be
able to empty the FIFO faster than the PCI bus can fill it.

PCI Configuration cy cles intended for internal Ra ven registers will also be
delayed if Raven is busy so that co ntrol bits which may affect writ e posting
do not change until all write posted transactions have completed.

2-12

Functional Description

PCI Master

The PCI master, in conju nction with the cap abilities of the MPC s lave, will
attempt to move data in either singl e beat or burst transactions. All single
beat transactions will be subdivided into one or two 32-bit transfers,
depending on the alignment and size of the transaction. The PCI master
will attempt to transf er all burst t ransac tions in 64- bit mode. If at a ny time
during the transaction the PCI target indicates it can not support 64-bit
mode, the PCI mast er will c ontinue to transfer t he remai ning data i n 32-bit
mode.

The PCI Command Codes generated by the PCI master depend on the
MPC transfer type, TBST*, and the MEM field in the MSATTx registers.

Table 2-3. PCI Command Codes

MPC Transfer Type TBST* MEM PCI Command

Write w/ Flush
Write w/ Flush Atomic
Write w/ Kill
Graphics Write

Read
Read w/ ITM
Read w/ ITM Atomic
Graphics Read

x 1 0111

(Memory Write)

x00011

(I/O Write)

0 1 1110

(Memory Read Line)

110110

(Memory Read)

x 0 0010

(I/O Read)

2

Generating PCI Memory and I/O Cycles

Each programmable slave may be configured to generate PCI I/O or
memory accesses th rough the MEM and IOM fiel ds in its Attribute re gister
as shown below.

2-13

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

:

2

MEM IOM PCI Cycle Type

1 x Memory
0 0 Contiguous I/O
0 1 Spread I/O

The IBM CHRP specification describes two approache s f or hand ling PCI
I/O addressing: contiguous or spread address modes. When the MEM bit
is cleared, the I OM bit is used to select between these two modes whene ver
a PCI I/O cycle is to be perform ed.

When MEM is clea r or IOM is c lear, the Ra ven will take the MPC address ,
apply the offset specified in the MSOFFx register, and map the result
directly to PCI.

When MEM is clear an d IOM is set, t he Raven will t ake the MP C address,
apply the offset specified in the MSOFFx register, and map the result to
PCI as shown in Figure 2-2.

.

MPC Address + Offset

31 12 11 5 4 0

31 0

0 0 0 0 0 0 0

0000000

PCI Address

25 24

Figure 2-2. PCI Spread I/O Cycle Mapping

This CHRP compliant spread I/O mode allows each PCI device’s I/O
registers to res ide on a dif ferent MPC memor y page, so device drive rs can
be protected from each other using memory page protection.

2-14

54

1915 9610

Functional Description

All I/O accesses must be performed within natural word boundaries. Any
I/O access that is not contai ned within a nat ural word boun dary will resul t
in unpredictable operation. For exampl e, an I/O transfer of 4 bytes start ing
at address $80000010 is considered a valid transfer. An I/O transfer of 4
bytes startin g at ad dress $8 0000011 is consi dered an inva lid tr ansfer since
it crosses the natural word boundary at address $80000013/$80000014.

Generating PCI Configuration Cycles

Mechanism one (as just described above) is utilized to generate
configuration cycle s. Two 32 bit PCI I/O po rts at $CF8 and $CFC are used
to access PCI configuration space. One of the four MPC Slave Address
Registers is used to ga in access to $ CF8 and $CFC. Note that MSADD3 is
initialized at reset to access PCI I/O space with an MPC address of
$80000000.

The resource at $CF8 is a 32 bi t config urati on addr ess p ort and i s ref erre d
to as the CONFIG_ADDRESS register. The resource at $CFC is a 32 bit
configuration data port and is referred to as the CONFIG_DATA register.

Accessing a PCI functions’s configuration port is a two step process;

❏ Write the bus number, physical device number, function number

and register number to the CONFIG_ADDRESS register.

2

❏ Perform an I/O read from or a write to the CONFIG_DATA register.

Generating PC I Special Cycles

To prime Raven to generate a speci al cyc le, the hos t proce ssor must write
a 32 bit value to the CONFIG_ADDRESS register. The contents of the
write are defined later in this chapter under the CONFIG_ADDRESS
register definition. After the write to $CF8 has been accomplished, the
next write to the CONFI G_DATA re giste r causes the Raven t o gene rate a
special cycle on the PCI bus. The write data is driven onto AD[31:0]
during the special cycle’s data phase.

2-15

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

Generating PCI Interrupt Acknowledge Cycles

Performing a read from the PIACK register will initiate a single PCI
Interrupt Acknowledge cycle. Any single byte or combination of bytes
may be read from, and the act ual byte enable patte rn u sed during the read
will be passed on to the PCI bus. Upon completion of the PCI interrupt
acknowledge cycle, the Raven will p resent the result ing vector inform ation
obtained from the PCI bus as read data.

Endian Conversion

The Raven supports both Big- and Little-Endian data formats. Since PCI
is inherently Little- Endian, convers ion is necessa ry if all MPC devices ar e
configured for Big-Endian operation. The Raven may be programmed to
perform the Endian conversion described below.

When MPC Devices are Big-Endian

When all MPC devices are op erating in Bi g-Endian mode, a ll data to/fr om

PCI must be swapped such th at PCI looks big endia n from the MPC bus ’s
perspective. This is shown in Figure 2-3.

2-16

Functional Description

.

2

DH07-00

DH15-08

DH23-16

DH31-24DL07-00

D0 D1 D2 D3 D4 D5 D6 D7

DL15-08

DL23-16

DL31-24

PPC Bus

D7 D6 D5 D4 D3 D2 D1 D0

AD31-24

AD23-16

AD15-08

DL23-16

AD07-00

DL31-24

AD63-56

AD55-48

AD47-40

AD39-32

DH07-00

DH15-08

DH23-16

DH31-24

DL07-00

DL15-08

D0 D1 D2 D3 D4 D5 D6 D7

D7 D6 D5 D4
D3 D2 D1 D0

AD31-24

AD23-16

AD15-08

32-bit PCI

AD07-00

Figure 2-3. Big to Little Endian Data Swap

64-bit PCI

PPC Bus

1916 9610

When MPC Devices are Little Endian

When all MPC devices are operating in little endian mode, the MPC
address must be modified to remove the exclusive-ORing applied by
MPC60x processors before being passed on to PCI. The three low order
processor bus address bits are exclusive-ORed with a three-bit value that
depends on the length of the operand, as shown in Table 2-4.

2-17

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

Table 2-4. Address Modification for Little Endian Transfers

Data Length

(bytes)

1XOR with 111
2XOR with 110
4 XOR with 100
8 no change

Note The only legal data lengths supported in little endian mode

are 1, 2, 4, or 8-byte aligned transfers.

Cycles Originating From PCI

For bus cycles initiated by PCI masters, the PCI address will be modified
the same way the MCP60x processor does in little endian mode. The
modification will be the same as that described in Section 3.7.2 above.
Since this method has some difficulties dealing with unaligned transfers,
the Raven will break up all unaligned PCI transfers into multiple aligned
transfers on the MPC bus.

Address Modification

Error Handling

The Raven will be capable of de tecti ng and re porti ng the f ollowi ng error s
to one or more MPC masters:

❏ MPC address bus time-out
❏ PCI master signalled master abort
❏ PCI master received target abort
❏ PCI parity er ror
❏ PCI system error

2-18

Functional Description

Each of these error condi tions wil l cause an err or st atus bi t to be se t in th e
MPC Error Status Register. If a second error is detected while any of the
error bits is set, the OVFL bit is asserte d, but none of t he error bits ar e
changed. Each bit in the MPC Error Status Register may be cleared by
writing a 1 to it; writing a 0 to it has no effect. New error bits may be set
only when all previous error bits have been cleared.

When any bit in the MPC Error Status register is s et, the Raven will
attempt to latch as much information as possible about the error in the
MPC Error Address and Attribute Registers. Information is saved as
follows:

Error Status Error Address and Attributes

MATO From MPC bus

SMA From PCI bus

RTA From PCI bus
PERR Invalid
SERR Invalid

Each MERST error bit may be programmed to generate a machine check
and/or a standard in terrupt. The er ror response is programmed thro ugh the
MPC Error Enable Register on a sour ce by sourc e basis . When a machi ne
check is enabled, eit her the MID fiel d in the MPC Error Attribute Reg ister
or the DFLT bit in the MEREN Register determine the master to which the
machine check is directed. For errors in which the master who originated
the transaction can be det ermined, the MID field is used, provided th e MID
is%00 (processor 0), %01 (processor 1), or %10 (proce ssor 2). For errors
not associated with a particular MPC master, or associated with masters
other than processor 0,1 or 2, the DFLT bit is used. One example of an
error condition which cannot be associated with a particular MPC master
would be a PCI system error.

2

2-19

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

PCI/MPC Contention Handling

The Raven has a stall detection mechanism that detects when there is a
possible resource contention problem (i.e. deadlock) as a result of
overlapping MPC and PCI initiated transactions. The MPC Slave and the
PCI Slave functions contain the logic needed to implement this fe ature.

The PCI Slave function contributes to the stall detection mechanism by
issuing a stall signal to the MPC Slave function whenever it is currently
processing a t ransa ction t hat must have contr ol o f the MPC bus b efore the
transaction can be completed. The events that activate this signal are:

❏ PCI read cycle
❏ PCI non-posted write cycle
❏ PCI posted write cycle with flush-before-read (FLBRD) enabled
❏ PCI posted w rite cycle an d internal FIFO full

The MPC Slave function determines its future actions based on the stall
signal and the current MPC bus activity. If the MPC Slave function
determines there will be contention between a cycle completing on the
MPC bus and an incoming PCI cycle , the MPC Slave will issu e a retry fo r
the current MPC t ransaction. This re try will free up the MPC bus and al low
the PCI initiated transaction to complete. An idle MPC bus obviously gives
immediate access to the pending PCI initiated transaction.

2-20

If the MPC bus is currently supporting a read cycle of any type, the cycle
will be terminated wi th a retry. Note that i f the read cycle is ac ros s a mod­4 address boundary (i.e. f rom address 0 x...02, 3 bytes) , it is poss ible that a
portion of the read could have been completed before the stall condition
was detected. The previously read data will be discarded and the current
transaction will be retried.

If the MPC bus is currently supporting a posted write transaction, the
transaction will be allowed to complete since this type of transaction is
guaranteed completion. If the MPC bus is currently supporting a non­posted write transaction, the transaction will be terminated with a retry.
Note that a mod-4 non-posted write transaction could be interrupted

Functional Description

between write cycles, and thereby result in a partially completed write
cycle. It is recommended that write cycles to write-sensitive non- posted
locations be performed on mod-4 address boundaries.

The Raven has a programmable option to guarantee all PCI write posted
transactions are completed before an MPC initiated read transaction may
be allowed to comple te. Th is opt ion is contr olled by t he FLBRD b it i n the
GSCR register. If this bit is set, all MPC read transactions will be retried
until all posted PCI write tr ansact ions have c omplete d. It is re commended
that this option be disabled, and the FLBRD bit be left in the default
(disabled) state.

2

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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

2Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

Registers

This chapter provides a detailed description of all Raven registers. These
registers are broken into two groups: the MPC Registers and the PCI
Configuration Registe rs. The MP C Regist ers are a cce ssible onl y from t he
MPC bus using any valid transfer size. The PCI Configuration Registers
reside in PCI configurat io n spa ce. They are accessible from the MPC bus
through the Raven. The MPC Registers are described first; the PCI
Configuration Registers are described next.

The following conventions are used in the Raven register charts:

❏ R Read O nly field.
❏ R/W Read/Write field.
❏ S Writing a ONE to this field sets this field.
❏ C Writing a ONE to this field clears this field.

MPC Registers

The Raven MPC register map is shown in Table 2-5.

Table 2-5. Raven MPC Register Map

Bit --->

$FEFF0000 VENID DEVID
$FEFF0004 REVID
$FEFF0008 GCSR FEAT

$FEFF000C MARB

$FEFF0010 PADJ
$FEFF0014
$FEFF0018

$FEFF001C

$FEFF0020 MEREN

2-22

0 1 2 3 4 5 6 7 8 9

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1

Registers

Table 2-5. Raven MPC Register Map (Continued)

Bit --->

$FEFF0024 MERST
$FEFF0028 MERAD

$FEFF002C MERAT

$FEFF0030 PIACK
$FEFF0034
$FEFF0038

$FEFF003C

$FEFF0040 MSADD0
$FEFF0044 MSOFF0 MSATT0
$FEFF0048 MSADD1

$FEFF004C MSOFF1 MSA T T1

$FEFF0050 MSADD2
$FEFF0054 MSOFF2 MSATT2
$FEFF0058 MSADD3

0 1 2 3 4 5 6 7 8 9

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2

1

$FEFF005C MSOFF3 MSA T T3

$FEFF0060
$FEFF0064
$FFEF0068

$FEFF006C

$FEFF0070 GPREG0(Upper)
$FEFF0074 GPREG0(Lower)

$FEFF078 GPREG1(Upper)

$FEFF07C GPREG1(Lower)

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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

Vendor ID/Device ID Registers

Address $FEFF0000
Bit

0 1 2 3 4 5 6 7 8 9
Name VENID DEVID
Operation R R
Reset $1057 $4801

VENID Vendor ID. This register identifies the manufacturer of

DEVID Device ID. This register identifies this particular device.

Revision ID Register

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1

the device. This identifier is allocated by the PCI SIG to
ensure uniqueness. $1 057 has bee n assigne d to Motor ola.
This register is duplicated in the PCI Configuration
Registers.

The Raven will always return $4801. This register is
duplicated in the PCI Configuration Registers.

Address $FEFF0004
Bit

0 1 2 3 4 5 6 7 8 9
Name REVID
OperationRRRR
Reset $00 $02 $00 $00

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1

REVID Revision ID. This register identifies the Raven revision

level. This register is dupli cated in t he PCI Configura tion
Registers.

2-24

Registers

General Control-Status/Feature Registers

Address $FEFF0008
Bit

0 1 2 3 4 5 6 7 8 9

Name GCSR FEAT

Operation

Reset

LEND

R/WRRRR/W

00000000000000000

BHOG

FLBRD

R/W

MBT1

MBT0

R/W

R/WRRRRRRRRRRRRRRRRRRRRRRRR

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P64

MARB

MPIC

MID1

MID0

EXT14

0/1

EXT13

0/1

EXT12

0/1

EXT11

0/1

EXT10

0/1

EXT09

0/1

EXT08

0/1

LEND Endian Select. If set, the MPC bus is operating in little

endian mode. The MPC address will be modified as
described in the section When MPC Devices are Little
Endian. When LEND is clear, the MPC bus is operating
in big endian mode, and all data to/from PCI is swapped
as described in the section When MPC Devices are Big-
Endian.

FLBRD Flush Before Read. If set, the Raven will guarantee that

all PCI initiated posted write transactions will be
completed before any MPC initiated read transactions will
be allowed to complet e. When FLBRD is clear , there wi ll
be no correlation between these transaction types and
their order of completion. Please refer to the section on
PCI/MPC Contention Handling for more information.

EXT07

0/1

EXT06

0/1

EXT05

0/1

EXT04

0/1

EXT03

0/1

EXT02

0/1

EXT01

0/1

2

1

EXT00

0/1

BHOG Bus Hog. If set, the Raven MPC master will o perate in the

Bus Hog mode. Bus Hog mode means the MPC master
will continually request the MPC bus for the entire
duration of each PCI transfer. If Bus Hog is not enabled,
the MPC master will reques t t he bus i n a normal manner.
Please refer to the section on MPC Master for more
information.

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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

time-out length. The time-out length is encoded as
follows:

MBTx MPC Bus Time-out. This field specifies the MPC bus

MBT Time Out Length

00 256 µsec

01 64 µsec
10 8 µsec
11 disabled

P64 6 4-bit PCI Mode Enable. If set, the Raven is connected

to a 64-bit PCI bus. This bit is set if REQ64* is asserted
on the rising edge of RESET*.

MARB MPC Arbiter Enable. If set, the Raven internal MPC

Arbiter is enabled. This bit is set if CPUID is %111 on the
rising edge of RESET*.

MPIC Multi-Processor Interrupt Controller Enable. If set,

the Raven internal MPIC interrupt controller is enabled.
This bit is set if EXT15 is high on the rising edge of
RESET*. If cleared, Raven detected errors wi ll be pa ssed
on to processor 0 INT pin.

2-26

MIDx Master ID. This field is encoded as shown below to

indicate who is currently the MPC bus master. When the
internal MPC arbiter is enabl ed (MARB is set), these bi ts
are controlled by the internal arbiter. When the internal
arbiter is disabled (MARB is clear) these bits reflect the
status of the CPUID pins. In a multiprocessor
environment, these bits allow software to determine on
which processor it i s currently runni ng. The internal MPC
arbiter encodes this field as follows:

Registers

.

MID Current MPC Data Bus Master

00 device on ABG0*
01 device on ABG1*
10 device on ABG2
11 Raven

2

FEAT Feature Register. Each bit in this register reflects the

state of one of the external interrupt input pins on the
rising edge of RESET*. This register may be used to
report hardware configuration parameters to system
software.

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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

MPC Arbiter Control Register

Address $FEFF000C
Bit

0 1 2 3 4 5 6 7 8 9
Name MARB

Operation R R

Reset $00 $00

BREN2 Bus Request 2 Enable. If set, the processor bus request

BREN1 Bus Request 1 Enable. If set, the processor bus request

BREN0 Bus Request 0 Enable. If set, the processor bus request

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BREN2

BREN1

BREN0

PKEN

PKMD

GLMD

BAMD

RRRRR

000001110001001

R/W

R/W

R/W

R/W

R/W

R/W

R/WRR

signal ABR2* is enabled. If cleared, ABR2* is not
enabled, and ABG2* will never be asserted.

signal ABR1* is enabled. If cleared, ABR1* is not
enabled, and ABG1* will never be asserted.

signal ABR0* is enabled. If cleared, ABR0* is not
enabled, and ABG0* will never be asserted.

1

DEFM1

DEFM0

R/W

R/W

1

2-28

PKEN Bus Parking Enable. If set, the MPC arbiter will park an

MPC master on the bus when no b us requests are pen ding.
If cleared, no MPC master will be granted the bus witho ut
first asserting its ABRx*.

PKMD Bus Parking Mode. When bus parking is enabled (PKEN

is set), this bit defines the method used to determine which
MPC master is parked on the bus. If set, the master
specified in the DEFM field is parked on the bus when no
bus requests are pending. If cleared, the last active MPC
master is parked on the bus when no bus requests are
pending. This field has no meaning when PKEN is clear.

Registers

GLMD Glance Mode. If set, the MPC arb iter will operate in the

BAMD Benign Address Retry Mode. If set, the MPC arbiter wil l

DEFMx Default Master. This field specifies which MPC bus

DEFM1 DEFM0 Parked Device

Prescaler Adjust Register

Glance mode. Please ref er to the section on the MPC
Arbiter for more information.

operate in the benign address retry mode. Please refer to
the section on the MPC Arbiter for more information.

master will be parked on the bus when default parking is
enabled. DEFM only has meaning when PRKEN and
PRKMD are both set.

0 0 device on ABR0*
0 1 device on ABR1*
1 0 device on ABR2*
11 Raven

2

Address $FEFF0010
Bit

0 1 2 3 4 5 6 7 8 9

Name PADJ
Operation R R R R/W
Reset $00 $00 $00 $B4

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PADJ Pr escaler Adjust. This registe r is used to specify a scale

factor for the presca ler to ensure tha t the time base for the
bus timer is 1 MHz. The scale factor is calculated as
follows:

PADJ = 256 - Clk,

1

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Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

following table shows the scale factor s for some common
CLK frequencies.

where Clk is the frequency of the CLK inp ut in MHz. The

Frequency PADJ

66 $B4
50 $CE
40 $D8
33 $DF
25 $E7

MPC Error Enable Register

Address $FEFF0020
Bit

0 1 2 3 4 5 6 7 8 9
Name MEREN

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DFLT

MAT OM

PERRM

SERRM

SMAM

RTAM

MAT OII

PERRI

SERRI

SMAI

RTAI

1

Operation R R

Reset $00 $00

DFLT Default MPC Master ID. This bit dete rmines which

MCHK* pin will be asserte d for error con ditions in which
the MPC master ID can not be determined or the Raven
was the MPC master. For example, in event of a PCI

parity error for a transaction in which the Raven’s PCI
master was not involved, the MPC master ID can not be
determined. When DFLT is set, MCHK1* is used. When
DFLT is clear, MCHK0* will be used.

2-30

R

R/W

R/WRR/W

000000000000000

R/W

R/W

R/WRR

R/WRR/W

R/W

R/W

R/W

0

Registers

MATOM MPC Address Bus Time-out Machine Check Enable.

When this bit is set, the MA T O bit in the MERST register
will be used to assert the MCHK output to the current
address bus master. When this bit is clear , MCHK will not
be asserted.

PERRM PCI Parity Error Machine Check Enable. When this

bit is set, the PERR bit i n the MERST register wil l be used
to assert the MCHK output to bu s master 0. When thi s bit
is clear, MCHK will not be asserted.

SERRM PCI System Error Machine Check Enable. When this

bit is set, the SERR bit i n the MERST register wil l be used
to assert the MCHK output to bu s master 0. When thi s bit
is clear, MCHK will not be asserted.

SMAM PCI Signalled Master Abort Machine Check Enable.

When this bit is set, the SMA bit in the MERST register
will be used to asse rt t he MCHK ou tput t o the bus mast er
which initia ted the transac tion. When this bi t is clear,
MCHK will not be asserted.

RTAM PCI Master Received Target Abort Ma chine Check

Enable.When this bit is set, the RTA bit in the MERST

register will be used t o assert the MCHK ou tput to the bus
master which initiated the transaction. Whe n this bit is
clear, MCHK will not be asserted.

2

MATOI MPC Address Bus Time-out Interrupt Enable.When

this bit is set, the MA TO bit in the MERST register will be
used to assert an interrupt through the MPIC interrupt
controller. When this bit is clear, no interrupt will be
asserted.

PERRI PCI Parity Err or Interrupt Enabl e.When th is bit is s et,

the PERR bit in the MERST registe r will be u sed to asse rt
an interrupt throu gh the MP IC int erru pt co ntrol ler. When
this bit is clear, no interrupt will be asserted.

2-31

Raven PCI Host Bridge & Multi-Processor Interrupt Controller Chip

2

set, the PERR bit in the MERST register will be used to
assert an interrupt through the MPIC interrupt controller.
When this bit is clear, no interrupt will be asserted.

SMAI PCI Master Signalled Master Abort Interrupt

Enable.When this bit is set, the SMA bit in the MERST

register will be used to assert an interrupt through the
MPIC interrupt controller. When this bit is clear, no
interrupt will be asserted.

RTAI PCI Master Received Target Abort Interrupt

Enable.When this bit is set, the RTA bit in the MERST

register will be used to assert an interrupt through the
MPIC interrupt controller. When this bit is clear, no
interrupt will be asserted.

MPC Error Status Register

Address $FEFF0024

SERRI PCI System Error Interrupt Enable.When this bit is

Bit

0 1 2 3 4 5 6 7 8 9
Name MERST

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OVF

MATO

PERR

SERR

SMA

RTA

1

Operation R R R

Reset $00 $00 $00

OVF Error Status Overflow. This bit is set when any error is

detected and any of t he error status bits a re already set. It
may be cleared by writing a 1 to it; writing a 0 to it has no
effect.

MATO MPC Address Bus Time-out. This bit is set when the

MPC address bus timer times out. It may be cleared by
writing it to a 1; writing it to a 0 has no effect. When the

2-32

R/CRR/CRR/C

0000000

R/C

R/C

R/C

0

Registers

MA T OM bit in the MEREN regi ster is set, the asser tion of
this bit will assert MCHK to the master designated by the
MID field in the MERAT register. When the MATOI bit
in the MEREN register is set, the assertion of this bit will
assert an interrupt through the MPIC interrupt controller.

PERR PCI Parity Error . This bit is set when the PCI PERR* pin

is asserted. It may be cleared by writing it to a 1; writing
it to a 0 has no effect. When the PERRM bit in the
MEREN register is set , the as serti on of this bit will as se rt
MCHK to the master designated by the DFLT bit in the
MERAT register. When the PERRI bit in the MEREN
register is set, the assertion of this bit will assert an
interrupt through the MPIC interrupt controller.

SERR PCI System Error. This bit is set when the PCI SERR*

pin is asserted. It may be cleared by writing it to a 1;
writing it to a 0 ha s no eff ect. When t he SERRM bit in the
MEREN register is set , the as serti on of this bit will as se rt
MCHK to the master designated by the DFLT bit in the
MERAT register. When the SERRI bit in the MEREN
register is set, the assertion of this bit will assert an
interrupt through the MPIC interrupt controller.

2

SMA PCI Master Signalled Master Abort. This bit is set

when the PCI master signals master abort to terminate a
PCI transaction. It may be cleared by writing it to a 1;
writing it to a 0 has no ef fect . When t he SMAM bi t in t he
MEREN register is set , the asser tion of t his b it wi ll as sert
MCHK to the master designated by the MID field in the
MERAT register. When the SMAI bit in the MEREN
register is set, the assertion of this bit will assert an
interrupt through the MPIC interrupt controller.

RT A PCI Master Received Target Abort. This bit is set when

the PCI master receives target abort to terminate a PCI
transaction. It may be cl eared by writin g it to a 1; writi ng
it to a 0 has no effect. When the RT AM bit in the MEREN
register is set, the assertion of this bit will assert MCHK
to the master designated by the MID field in the MERAT

2-33