Motorola MVME166D2, MVME166IG-D2, MVME166IG User Manual 2

MVME166

Single Board Computer

Installation Guide

(MVME166IG/D2)

Notice

While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motor ola reserves the right to r evise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.

No part of this material may be reproduced or copied in any tangible medium, or stored in a retrieval system, or transmitted in any form, or by any means, radio, electronic, mechanical, photocopying, recording or facsimile, or otherwise, without the prior written permission of Motorola, Inc.

It is possible that this publication may contain reference to, or information about Motorola products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that Motorola intends to announce such Motorola products, programming, or services in your country.

Restricted Right Legend

If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc.

Use, duplication, or disclosure by the Governm ent is subject to r estrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013.

Motorola, Inc.

Computer Group

2900 South Diablo Way

Tempe, Arizona 85282

Preface

This manual provides general board level hardware description, hardware preparation and installation instructions, debugger general information, and using the debugger; for the MVME166 Single Board Computer.

This manual is intended for anyone who wants to provide OEM systems, supply additional capability to an existing compatible system, or work in a lab environment for experimental purposes.

A basic knowledge of computers, and digital logic is assumed. After using this manual, you may wish to become familiar with the publications listed

in the Related Documentation section in Chapter 1 of this manual. This installation guide is based on these other documents.

The computer programs stored in the Read Only Memory of this device contain material copyrighted by Motorola Inc., first published 1990, and may be used on ly under a license such as the License for Computer Programs (Article 14) contained in Motorola’s Terms and Conditions of Sale, Rev. 1/79.

This equipment generates, uses, and can radiate radio

WARNING

Motorola and the Motorola symbol are registered trademarks of Motorola, Inc. Delta Series, VMEmodule, and VMEsystem are trademarks of Motorola, Inc. Timekeeper and Zeropower are trademarks of Thompson Components. All other products mentioned in this document are trademarks or registered

trademarks of their respective holders.

frequency energy and if not installed and used in accordance with the documentation for this product, may cause interference to radio communications. It has been tested and found to comply with the limits for a Class A Computing Device pursuant to Subpart J of Part 15 of FCC rules, which are designed to provide reasonable protection against such interference when operated in a commercial environment. Operation of this equipment in a residential area is likely to cause interference in w hich ca se the user, at

the user’s own expense, will be required to take whatever measures necessary to correct the interference.

©Copyright Motorola 1993, 1994

Printed in the United States of America

April 1994

Safety Summary

Safety Depends On You

The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design, manufacture, and intended use of the equipment. Motorola, Inc. assumes no liability for the customer’s failure to comply with these requirements.

The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.

Ground the Instrument.

T o minimize sho ck hazard, the equipment chassis and enclosure must be connected to an electrical ground. The equipment is supplied with a three-conductor AC power cable. The power cable must either be plugged into an approved three-contact electrical outlet or used with a three-contact to two-contact adapter, with the grounding wire (green) firmly connected to an electrical ground (safety ground) at the power outlet. The power jack and mating plug of the power cable meet International Electrotechnical Commission (IEC) safety sta ndards.

Do Not Operate in an Explosive Atmosphere.

Do not operate the equipment in the presence of flammable gases or fumes. Operation of any electrical equipment in such an environment constitutes a definite safety hazard.

Keep Away From Live Circuits.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other qualified maintenance personnel may remove equipment covers for internal subassembly or component replacem ent or any internal adjustment. Do not replace components with power cable connected. Under certain conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, always disconnect power and discharge circuits before touching them.

Do Not Service or Adjust Alone.

Do not attempt internal service or adjustment unless another person, capable of rendering first aid and resuscitation, is present.

Use Caution When Exposing or Handling the CRT.

Breakage of the Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent CRT implosion, avoid rough handling or jarring of the equipment. Handling of the CRT should be done only by qualified maintenance personnel using approved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.

Because of the danger of intr oducing additional hazard s, do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local Motorola representative for service and repair to ensure that safety features are maintained.

Dangerous Procedure Warnings.

Warnings, such as the example below, precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed. Y ou should also employ all other safety precautions which yo u deem necessary for the operation of the equipment in your operating environment.

Dangerous voltages, capable of causing death, a re present in

WARNING

this equipment. Use extreme caution when handling, testing, and adjusting.

Contents

CHAPTER 1 BOARD LEVEL HARDWARE DESCRIPTION

Introduction.............................................................................................................1-1

Overview...........................................................................................................1-1

Related Documentation ..................................................................................1-2

Requirements....................................................................................................1-5

Features .............................................................................................................1-5

Specifications....................................................................................................1-6

Manual Terminology .......................................................................................1-6

Block Diagram.........................................................................................................1-8

Functional Description...........................................................................................1-9

Front Panel Switches and Indicators.............................................................1-9

Data Bus Structure.........................................................................................1-10

MC68040 MPU ...............................................................................................1-10

Flash Memory and Download EPROM......................................................1-10

SRAM...............................................................................................................1-11

Onboard DRAM.............................................................................................1-12

Battery Backed Up RAM and Clock............................................................1-13

VMEbus Interface ..........................................................................................1-13

VME Subsystem Bus (VSB) Interface..........................................................1-13

I/O Interfaces .................................................................................................1-13

Serial Port Interface................................................................................1-13

MC68230 Parallel Interface/Timer.......................................................1-14

Parallel Port Interface.............................................................................1-15

Ethernet Interface.............................. ..... ...... ........................................ ...1-15

SCSI Interface..........................................................................................1-16

SCSI Termination....................................................................................1-16

Local Resources..............................................................................................1-16

Programmable Tick Timers...................................................................1-17

Watchdog Timer .....................................................................................1-17

Software-Programmable Hardware Interrupts..................................1-17

Local Bus Timeout..................................................................................1-17

Connectors ......................................................................................................1-17

Memory Maps .......................................................................................................1-18

Local Bus Memory Map................................................................................1-18

Normal Address Range .........................................................................1-18

VMEbus Memory Map..................................................................................1-22

vii

VMEbus Accesses to the Local Bus......................................................1-22

VMEbus Short I/O Memory Map............................................................1-22

VSB Memory Map................................. ...... ....................................... ...............1-22

CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION

Introduction.................................................................................................................2-1

Unpacking Instructions..............................................................................................2-1

Hardware Preparation ...............................................................................................2-1

SCSI Terminator Enable Header J2 ...................................................................2-2

General Purpose Readable Jumpers on Header J3 .........................................2-4

System Controller Header J6..............................................................................2-4

SRAM Backup Power Source Select Header J7...............................................2-5

Installation Instructions.............................................................................................2-6

MVME166 Module Installation.........................................................................2-6

System Considerations .......................................................................................2-8

CHAPTER 3 DEBUGGER GENERAL INFORMATION

Overview of M68000 Firmware................................................................................3-1

Description of 166Bug................................................................................................3-1

166Bug Implementation.............................................................................................3-3

Installation and Startup .............................................................................................3-3

BOOTBUG ...................................................................................................................3-7

166BBug Implementation...................................................................................3-7

Execute User Program ........................................................................................3-8

Setup System Parameters...................................................................................3-8

Autoboot ......................................................................................................................3-9

ROMboot....................................................................................................................3-10

Network Boot............................................................................................................3-10

Restarting the System............................................................................................ ...3-11

Reset .................................. ..... ........................................ .....................................3-11

Abort............................................. ..... ........................................ ..........................3-12

Break....................................... ........................................ .....................................3-12

SYSFAIL* Assertion/Negation........................................................................3-12

MPU Clock Speed Calculation ........................................................................3-13

Memory Requirements ............................................................................................3-13

Terminal Input/Output Control.............................................................................3-14

Disk I/O Support......................................................................................................3-15

Blocks Versus Sectors ........................................................................................3-15

viii

Device Probe Function .....................................................................................3-16

Disk I/O via 166Bug Commands................................................................... 3-16

IOI (Input/Output Inquiry).....................................................................3 -16

IOP (Physical I/O to Disk) ..................................................... ...... ............3-16

IOT (I/O Teach).........................................................................................3 -16

IOC (I/O Control)...................................................................................... 3-17

BO (Bootstrap Operating System)........................................................... 3-17

BH (Bootstrap and Halt)...........................................................................3-17

Disk I/O via 166Bug System Calls.................................................................3-17

Default 166Bug Controller and Device Parameters.....................................3-18

Disk I/O Error Codes.......................................................................................3-19

Network I/O Support ............................................................................................. 3-19

Intel 82596 LAN Coprocessor Ethernet Driver.............................................3-19

UDP/IP Protocol Modules..............................................................................3-19

RARP/ARP Protocol Modules........................................................................3-20

BOOTP Protocol Module.................................................................................3-20

TFTP Protocol Module......................................................................................3-20

Network Boot Control Module.......................................................................3-20

Network I/O Error Codes...............................................................................3-20

Multiprocessor Support .......................................................................................... 3-21

Multiprocessor Control Register (MPCR) Method ......................................3-21

GCSR Method.................................................................................................... 3-23

Diagnostic Facilities.................................................................................................3-23

CHAPTER 4 USING THE 166Bug DEBUGGER

Entering Debugger Command Lines ......................................................................4-1

Syntactic Variables .............................................................................................. 4-2

Expression as a Parameter.......................................................................... 4-3

Address as a Parameter .............................................................................. 4-4

Address Formats..........................................................................................4-4

Offset Registers ............................................................................................4-6

Port Numbers ..................................... ...... ....................................... ....................4-8

Entering and Debugging Programs......................................................................... 4-9

Calling System Utilities from User Programs........................................................ 4-9

Preserving the Debugger Operating Environment...............................................4-9

166Bug Vector Table and Workspace.............................................................. 4-10

Hardware Functions.........................................................................................4-10

Exception Vectors Used by 166Bug ................................................................ 4-11

Using 166Bug Target Vector Table.......................................................... 4-12

Creating a New Vector Table...................................................................4-13

166Bug Generalized Exception Handler.................................................4-15

Floating Point Support............................................ ...... ........................................ ...4-17

Single Precision Real......................................................... ................................4-18

Double Precision Real.......................................................................................4-18

Extended Precision Real...................................................................................4-18

Packed Decimal Real.........................................................................................4-19

Scientific Notation.............................................................................................4-19

The 166Bug Debugger Command Set....................................................................4-20

APPENDIX A CONFIGURE AND ENVIRONMENT COMMANDS

Configure Board Information Block........................................................................A-1

Set Environment to Bug/Operating System..........................................................A-2

APPENDIX B DISK/TAPE CONTROLLER DATA

Disk/Tape Controller Modules Supported............................................................B-1

Disk/Tape Controller Default Configurations......................................................B-2

IOT Command Parameters for Supported Floppy Types....................................B-5

APPENDIX C NETWORK CONTROLLER DATA

Network Controller Modules Supported...............................................................C-1

List of Figures

FIGURES

Figure 1-1. MVME166 Block Diagram..................................................................1-8

Figure 2-1. MVME166 Switches, Headers, Connectors, Fuses, and LEDs......2-3

xii

List of T ables

TABLES

Table 1-1. MVME166 Specifications......................................................................1-6

Table 1-2. Local Bus Memory Map .....................................................................1-19

Table 1-3. Local I/O Devices Memory Map ......................................................1-20

Table 4-1. Debugger Address Parameter Formats..............................................4-5

Table 4-2. Exception Vectors Used by 166Bug...................................................4-11

Table 4-3. Debugger Commands.........................................................................4-20

Table A-1. ENV Command Parameters ..............................................................A-3

xiii

xiv

BOARD LEVEL

Introduction

This chapter describes the board level hardware features of the MVME166 Single Board Computers. The chapter is organized with a board level overview and features list in this introduction, followed by a more detailed hardware functional description. Front panel switches and indicators are included in the detailed hardware functional description. The chapter closes with some general memory maps.

All programmable registers in the MVME166 that reside in ASICs are covered in the MVME166/MVME167/MVME187 Single Board Computers Programmer’s Reference Guide.

Overview

The MVME166 is based on the MC68040 microprocessor. The MVME166 has 4/8/16/32/64/128/2 56 MB o f ECC-protected D RAM, 1 MB of Flash mem ory with download EPROM, 128KB of static RAM (with battery backup), 8KB of static RAM and time of day clock (with battery backup), Ethernet transceiver interface, four serial ports with TTL inter face, four tick timers, watchdog timer, SCSI bus interface with DMA, Centronics printer port, A16/A24/A32/D8/D16/D32/D64 VMEbus master/slave interface, VMEbus system controller, and a VSB interface.

HARDWARE DESCRIPTION

The I/O connection for the MVME166 is provided by two high density shielded front panel I/O connectors. The SCSI bus is connected through a 68 pin connector. The printer, four serial ports and Ethernet interface are connected through a 100 pin con n ecto r. The MVME712-10 transition mo dul e and the MVME712-06/07/09 I/O distribution board set were designed to support the MVME166 boards. These transition boards provide configuration headers, serial port drivers and industry standard connectors for the I/O devices.

The VMEbus interface is provided by an ASIC called the VMEchip2. The VMEchip2 includes two tick timers, a watchdog timer, programmable map decoders for the master and slave interfaces, and a VME bus to/from local bus DMA controller, a VMEbus to/from local bus non-DMA programmed access interface, a VMEbus interrupter, a VMEbus system controller, a VMEbus interrupt handler, and a VMEbus requester.

MVME166IG/D21-1

Board Level Hardware Description

Processor-to-VMEbus transfers can be D8, D16, or D32. VMEchip2 DMA transfers to the VMEbus, however, can be D16, D32, D16/BLT, D32/BLT, or D64/MBLT.

The VSBchip2 provides the VSB interface on the MVME166. The VSBchip2 includes programmable map decoders for the master and slave interfaces, a VSB master interface, a VSB slave interface, a VSB interrupter, a VSB interrupt handler, a VSB serial requester, a VSB serial arbiter, and a VSB parallel requester. The VSB is connected to the P2 connector rows A and C on the MVME166.

The PCCchip2 ASIC provides two tick timers and the interface to the LAN chip, SCSI chip, serial port chip, printer port, BBRAM, and do wnload EPROM for Flash memory.

The MCECC memory controller ASIC provides the programmable interface for the ECC-protected DRAM mezzanine board.

Requirements

These boards are designed to conform to the requirements of the following documents:

❏ VMEbus Specification (IEEE 1014-87) ❏ EIA-232-D Serial Interface Specification, EIA ❏ SCSI Specification, ANSI ❏ VSB Specification (IEEE 1096-1988)

Features

Features of the MVME166 are listed below.

❏ MC68040 Microprocessor ❏ 4/8/16/32/64/128/256MB of 32-bit DRAM with ECC protect io n ❏ 1 MB of Flash memory and a download EPROM ❏ 128KB SRAM (with battery backup) ❏ Status LEDs for FAIL, STAT, RUN, SCON, LAN, RPWR, SCSI, VME, TPWR and VSB ❏ 8K by 8 RAM and time of day clock with battery backup ❏ RESET and ABORT switches ❏ Four 32-bit tick timers for periodic interrupts ❏ Watchd og timer ❏ Eight software interrupts ❏ I/O

– SCSI Bus interface with DM A – Four serial ports with TTL buff e rs – Centronics printer p ort – Ethernet transceiver interface with DMA

❏ VMEbus interface

– VMEbus system controlle r fun c t ion s – VMEbus to local bus int e rface (A24/A32,

D8/D16/D32 (D8/D 16/D32/D64BLT) (BLT = Bl oc k Tr an sfe r)) – Local bus to VMEbus interf ac e (A 16 /A24/A32, D8/D16/D32) –VMEbus interrupter – VMEbus interrupt handler – Global CSR for interp rocessor communica ti on s – DMA for fast local memor y - VME b us t ran sfers (A16/A24/A32,

D16/D32 (D16/D32/D64BLT))

❏ VSB interface

– Local bus to VSB interface (A 16/A24/A32, D8/D16/D 32) – VSB to local bus interfac e ( A 16/A24/A32, D8/D16 /D32) – Control and Status Register se t s (Board CSRs accessible from bot h

local bus and VSB; local CSRs acc essible from loca l bus)

(Includes Global CSR for IPC (General Purpose Register s 1 an d 2)) – Local bus interrupter – VSB interrupter and VSB interrupt handler – Bidirectional write posting - local bus to VSB and VSB to local bus – EVSB compatible

Introduction

MVME166IG/D2 1-5

Board Level Hardware Description

Specifications

General specifications for the MVME166 are listed in Table 1-1.

Table 1-1. MVME166 Specifications

Characteristics Specifications

Power requirements

(excluding external LAN transceiver)

(at 33 MHz with 32 MB ECC memory)

Operating temperature 0° to 55° C at point of entry of forced air

Storage temperature -40° to +85° C Relative humidity 5% to 90% (non-condensing) Physical dimensions

PC board with mezzanine

module only

Height Depth Thickness

PC boards with connectors

and front panel

Height Depth Thickness

+5 Vdc (± 5%), 5.0 A (typical), 6.5 A (max.)

(includes transition modules)

+12 Vdc (± 5%), 100 mA (max.) (1.0 A

(max.) with offboard LAN transceiver)

-12 Vdc (± 5%), 100 mA (max.)

(approximately 490 LFM)

Double-high VMEboard

9.187 inches (233.35 mm)

6.299 inches (160.00 mm)

0.662 inches (16.77 mm)

10.309 inches ( 261.85 mm)

7.4 inches (188 mm)

0.80 inches (20.32 mm)

Manual Terminology

Throughout this manual, a convention is used which precedes data and address parameters by a character identifying the numeric format as follows:

$ dollar specifies a hexadecimal character % percent specifies a binary number & ampersand specifies a decimal number

For example, "12" is the decimal number twelve, and "$12" is the decimal number eighteen.

Unless otherwise specified, all address references are in hexadecimal. An asterisk (*) following the signal name for signals which are level significant

denotes that the signal is true or valid when the signal is low.

1-6 MVME166 Single Board Computer Installation Guide

Introduction

An asterisk (*) following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transition.

In this manual, assertion and negation are used to specify forcing a signal to a particular state. In particular, assertion and assert refer to a signal that is active or true; negation and negate indicate a signal that is inactive or false. These terms are used independently of the voltage level (high or low) that they represent.

Data and address sizes are defined as follows: ❏ A byte is eight bits, numbered 0 through 7, with bit 0 being the least

significant.

❏ A two-byte is 16 bits, numbered 0 through 15, with bit 0 being the least

significant. For the MVME166 and other CISC modules, this is called a word.

❏ A four-byte is 32 bits, numbered 0 through 31, with bit 0 being the least

significant. For the MVME166 and other CISC modules, this is called a longword.

The terms control bit and status bit are used extensively in this document. The term control bit is used to describe a bit in a register that can be set and cleared under software control. The term true is used to indicate that a bit is in the state that enables the function it controls. The term false is used to indicate that the bit is in the state that disables the function it controls. In all tables, the terms 0 and 1 are used to describe the actual value that should be written to the bit, or the value that it yields when read. The term status bit is used to describe a bit in a register that reflects a specific condition. The sta tus bit can be read by software to determine operational or exception conditions.

MVME166IG/D2 1-7

Board Level Hardware Description

Block Diagram

Figure 1-1 is a general block diagram of the MVME166.

MC68040

DRAM

82596CA

LAN

ETHERNET

VMEchip2

53C710

SCSI

FLASH

MK48T08

BBRAM

& CLOCK

CD2401

SCC

SERIAL IO

PCCchip2

VSBchip2

VSBVMEbus

PRINTER

PORT

DOWNLOAD

EPROM

128KB

STATIC

RAM

bd078 9304

Figure 1-1. MVME166 Block Diagram

1-8 MVME166 Single Board Computer Installation Guide

Functional Description

This section contains a functional description of the majo r blocks on the MVME166 Single Board Computers.

Front Panel Switches and Indicators

There are switches and LEDs on the front panel of the MVME166. The switches are RESET and ABORT. The RESET switch resets all onboard devices and drives SYSRESET* if the board is system controller. The RESET switch may be disabled by software. When enabled by software, the ABORT switch generates an interrupt at a userprogrammable level. It is normally used to abort program execution and return to the debugger. There are ten LEDs on the MVME166 front panel: FAIL, STAT, RUN, SCON, LAN, RPWR, SCSI, VME, TPWR and VSB.

The red FAIL LED (part of DS1) lights when the BRDFAIL signal line is active. The MC68040 status lines are decoded, on the MVME166, to drive the yellow STAT (status) LED (part of DS1). In this case, a halt condition from the processor lights the LED. The green RUN LED (part of DS2) lights when the local bus TIP* signal line is low. This indicates one of the local bus masters is executing a local bus cycle. The green SCON LED (part of DS2) lights when the VMEchip2 in the MVME166 is the VMEbus system controller. The green LAN LED (part of DS3) lights when the LAN chip is local bus master. The MVME166 supplies +5V, +12V, and -12V power to the transition board through fuses. There is one fuse for each voltage. The green RPWR (remote power) LED (part of DS3) lights when all three voltages are available to the transition board interface. The green SCSI LED (part of DS4) lights when the SCSI chip is local bus master. The green VME LED (part of DS4) lights when the board is using the VMEbus (VMEbus AS* is asserted by the VMEchip2) or when the board is accessed by the VMEbus (VMEchip2 is the local bus master). The MVME166 supplies +5V to the SCSI bus for terminator power through a fuse. The green TPWR (terminator power) LED (part of DS5) lights when TERMPWR is available to the SCSI bus. SCSI bus TERMPWR may be supplied by other devices on the SCSI bus. The green VSB LED (part of DS5) lights when the MVME166 is using the VSB (VSB PAS* is asserted by the VSBchip2) or when the MVME166 is accessed by the VSB (VSBchip2 is the local bus master).

Functional Description

MVME166IG/D2 1-9

Board Level Hardware Description

Data Bus Structure

The local data bus on the MVME166 is a 32-bit synchronous bus that is based on the MC68040 bus, and supports burst transfers and snooping. Th e various local bus master and slave devices use the local bus to communicate. The local bus is arbitrated by priority type arbiter and the priority of the local bus masters from highest to lowest is: 82596CA LAN, CD2401 serial (through the PCCchip2), 53C710 SCSI, VSB, VMEbus, and MPU. In the general case, any master can access any slave; however, not all combinations pass the common sense test. Refer to the MVME166/MVME167/MVME187 Single Board Computers Programmer’s Reference Guide and to the user’s guide for each device to determine its port size, data bus connection, and any restrictions that apply when accessing the device.

MC68040 MPU

The MC68040 processor is u sed o n t h e MVME1 66. The MC68040 has on-chip instruction and data caches and a floating point processor. Refer to the M68040 user’s manual for more information.

Flash Memory and Download EPROM

The MVME166 includes four 28F020 Flash memory devices and a download EPROM. These parts replace the four EPROM sockets used on the MVME167/187. The Flash parts are programmable on the MVME166 board and the programming code is provided in the download EPROM. The Flash devices provide 1 MB of ROM at address $FF800000-$FF8FFFFF. The download EPROM provides 128 KB of ROM at $FFF80000-$FFF9FFFF. The download EPROM is mapped to local bus address 0 following a local bus reset. This allows the MC68040 to access the stack pointer and execution address following a reset. The download EPROM appears at 0 until the DR0 bit is cleared in the PCCchip2 chip. The Flash devices are controlled by the VMEchip2 and the download EPROM is controlled by the PCCchip2. The PC0 bit in the MC68230 PI/T chip must be low to enable writes to Flash.

The EPROM contains the BootBug product (166BBug). Because Flash memory can be electronically erased, the EPROM firmware is a subset of the regular debugger product. It contains enough functionality from the debugger to permit downloading of object code (via VMEbus, serial port, SCSI bus, or the network) and reprogramming of the Flash memory.

A jumper on the MVME166 (J3, pins 7 and 8) controls the operation of the BootBug. If the jumper is in place, the BootBug (which always executes at power-up and reset) passes execution to the full debugger contained in Flash memory. If the jumper is removed, execution continues (with diminished functionality) in the BootBug.

1-10 MVME166 Single Board Computer Installation Guide

SRAM

Functional Description

Before you perform any SCSI, VMEbus, or Ethernet I/O with the MVME166, it may be necessary to define some parameters (e.g., SCSI ID, Ethernet address, VMEbus mapping). For details on configuring the MVME166, refer to the setup command description in Chapter 3 in this manual, and in the MVME167Bug Debugging Package User’s Manual .

The boards include 128KB of 32-bit wide static RAM with onboard battery backup that supports 8-, 16-, and 32-bit wide accesses. The SRAM allows the debugger to operate and limited diagnostics to be executed without the DRAM mezzanine. The SRAM is controlled by the VMEchip2, and the a ccess time is programmable. The boards are populated with 100 ns SRAMs.

The SRAM is also battery backed up on the MVME166. The battery backup function is provided by a Dall as DS1210S. The DS12 10S supports primary and secondary power sources. When the main board power fails, th e DS1210S selects the source with the highest voltage. If one source should fail, the DS1210S switches to the redundant source. Each time the board is powered, the DS1210S checks power sources and if the voltage of the backup sources is less than two volts, the second memory cycle is blocked. This allows software to provide an early warning to avoid data loss. Because the DS1210S may block the second access, the software should do at least two accesses before relying on the data.

The MVME166 provides jumpers that allow either power source of the DS1210S to be connected to the VMEbus +5 V STDBY pin or one cell of the onboard battery. For example, the primary system backup source may be a battery connected to the VMEbus +5 V STDBY pin and the secondary source may be the onboard battery. If the system source should fail or the board is removed from the chassis, the onboard battery takes over.

Caution

The onboard power source is a RAYOVAC FB1225 battery which has two BR1225 type lithium cells and is socketed for easy removal and replacement. A small capacitor is provided to allow the battery to be quickly replaced without data loss. The lifetime of the battery is very d ependent on the ambient temperature of the board and the power-on duty cycle. The lithium battery supplied on the MVME166 should p rovide at least two years of backup t i me

MVME166IG/D2 1-11

For proper operation of the SRAM, some jumper

combination must be installed on the Backup Power Source

Select Header. If one of the jumpers is used to select the

battery, the battery must be installed on the MVME166. The

SRAM may malfunction if inputs to the DS1210S are left

unconnected.

Board Level Hardware Description

with the board powered off and the board at 40° C. If the pow er-on duty cycle is 50% (the board is powered on half of the time), the battery lifetime is four years. At lower ambient temperatures the backup time is greatly extended and may approach the shelf life of the battery. When a board is stored, the battery should be disconnected to prolong battery life. This is especially important at high ambient temperatures. The MVME166 is shipped with the batteries disconnected.

The power leads from the battery are exposed on the solder side of the board, therefore the board should not be placed on a conductive surface or stored in a conductive bag unless the battery is removed.

Caution

❏ Do not short circuit. ❏ Do not disassemble, deform, or apply excessive pressure. ❏ Do not heat or incinerate. ❏ Do not apply solder directly. ❏ Do not use different models, or new and old batteries together. ❏ Do not charge. ❏ Always check proper polarity.

Lithium batteries incorporate inflammable materials such as lithium and organic solvents. If lithium batteries are mistreated or handled incorrectly, they may burst open and ignite, possibly resulting in injury and/or fire. When dealing with lithium batteries, carefully follow the precautions listed below in order to prevent accidents.

To remove the battery from the module, carefully pull the battery from the socket.

Before installing a new battery, ensure that the battery pins are clean. Note the battery polarity and press the battery into the socket. When the battery is in the socket, no soldering is required.

Onboard DRAM

The MVME166 onboard DRAM is located on a mezzanine board. The mezzanine boards are available in different sizes and with ECC protection. Mezzanine board sizes are 4, 8, 16, 32, 64, or 128MB, and two mezzanine boards may be stacked to provide 256MB of onboard RAM. The main board and a single mezzanine board together take one slot. The stacked configuration requires two VMEboard slots. The DRAM is four-way interleaved to efficiently support cache burst cycles.

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The DRAM map decoder can be programmed to a ccommo date dif ferent base address(es) and sizes of mezzanine boards. The onboard DRAM is disabled by a local bus reset and must be programmed before the DRAM can be accessed. Refer to the MCECC in the MVME166/MV ME167/ MVME187 S ing le Board Computers Programmer’s Reference Guide for detailed programming information. Most DRAM devices require some number of access cycles before the DRAMs are fully operational. Normally this requirement is met by the onboard refresh circuitry and normal DRAM installation. However, software should insure a minimum of 10 initialization cycles are performed to each bank of RAM.

Battery Backed Up RAM and Clock

The MK48T08 RAM and clock chip is used on the MVME166. This chip provides a time of day clock, oscillator, crystal, power fail detection, memory write protection, 8KB of RAM, and a battery in one 28-pin package. The clock provides seconds, minutes, hours, day, date, month, and year in BCD 24-hour format. Corrections for 28-, 29- (leap year), and 30-day months are automatically made. No interrupts are generated by the clock. The MK48T08 is an 8 bit device; however, the interface provided by the PCCchip2 supports 8-, 16-, and 32-bit accesses to the MK48T08. Refer to the MK48T08 data sheet for detailed programming information.

VMEbus Inte rface

Functional Description

The local bus to VMEbus interface, the VMEbus to local bus interface, and the local-VMEbus DMA controller functions on the MVME166 are provided by the VMEchip2. The VMEchip2 can also provide the VMEbus system controller functions.

VME Subsystem Bus (VSB) Interface

The local bus to VSB interface and the VSB to local bus interface are pro vided by the VSBchip2, only on the MVME166 board. The VSB uses the P2 connector of the MVME166.

I/O Interfaces

The MVME166 provides onboard I/O for many system applications. The I/O functions include serial ports, printer port, Ethernet transceiver interface, and SCSI mass storage interface.

Serial Port Interface

The CD2401 serial controller chip (SCC) is used to implement the four serial ports. The serial ports support the standard baud rates (110 to 38.4K baud). The four serial ports on the MVME166 are functionally the same. All serial ports are full function asynchronous or synchronous ports. They can operate

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Board Level Hardware Description

at synchronous bit rates up to 64 k bits per second. They use RXD, CTS, DCD, TXD, RTS, DTR, and DSR. They also interface to the synchronous clock signal lines. Additional control signals are provided for each serial port by the MC68230. These include local loopback control, self test control, and ring indicator. The ring indicator signal can be programmed to generate a local bus interrupt. Refer t o th e MC68230 section for addit i o nal i n fo rmat io n. Note that the usable functionality of the serial ports depends on the transition module used.

All four serial ports on the MVME166 use a TTL interface to the transition board. This allows the interface specific drivers to be located on the transition board. This allows more flexibility in configuring the serial ports for different interfaces like EIA-232-D or V.35. An external I/O transition module such as the MVME712-10 should be used to provide configuration headers, interface drivers, and industry-standard connectors.

The interface provided by the PCCchip2 allows the 16-bit CD2401 to appear at contiguous addresses; however, accesses to the CD2401 must be 8 or 16 bits. 32-bit accesses are not permitted. Refer to the CD2401 data sheet for detailed programming information.

The CD2401 supports DMA operations to local memory. Because the CD2401 does not support a retry operation necessary to break VMEbus or VSB dual port lockup conditions, the CD2401 DMA controllers should not be programmed to access the VMEbus or VSB. The hardware does not restrict the CD2401 to onboard DRAM.

MC68230 Parallel Interface/Timer

The MVME166 provides an MC68230 parallel interface/timer (PI/T) chip. When the MVME166 is used with the MVME712-10 transition module or the MVME712-06/07/09 I/O distribution board set, the MC68230 is used to provide additional control lines for the serial ports. These include local loopback, self test, and ring indicator. The ring indicator signals can be programmed to generate local bus interrupts. Refer to the MVME712-10 transition module manual for more information.

The base address of the MC68230 is $FFF45E00, and because it is an 8-bit device it appears only at odd addresses. Space for the MC68230 was created by dividing the area occupied by redundant copies of the CD2401 registers into eight segments. The CD2401 is still addressed at $FFF45000 to $FFF451FF. Addresses $FFF45200 to $FFF45BFF are reserved, and if accessed on an MVME166 cause a local bus timeout error, if the local bus timer is enabled. The address range from $FFF45C00 to $FFF45DFF always returns a local bus timeout error if the local bus timer is enabled. The CD2401 appears redundantly from $FFF45200 to $FFF45FFF on the MVME167/187.

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The presence of the MC68230 can be determined by reading address $FFF45C00. If a timeout error occurs, then the board is an MVME166 and and the MC68230 is present. If a timeout does not occur, then the board is an MVME167/187 and the MC68230 is not present. The local bus timeout timer in the VMEchip2 must be enabled for this test.

The MC68230 may be used for general purpose I/O when the MVME166 is not used with the MVME712 family of transition modules. Because the outputs are unbuffered and unprotected, these signals should be used with caution. The port A signal lines PA<7..0> are connected to the front panel connector J9. The port A signal lines can be programmed as inputs or outputs. The port B signal lines PB<3..0> are connected to the port H signal lines H<4..1> and the front panel connector J9. This allows these four lines to be inputs or outputs or receive interrupts. The port B signal line PB<7> is also connected to the front panel connector J9. When used with the MVME712 family of transition modules, the PB<7> signal line is used to read the configuration of the serial ports. Timer interrupts from the MC68230 are not supported on the MVME166. The MC68230 is conn ected t o a 1 0 MHz cl ock . The P C0 bi t in the MC68230 PI/T chip must be low to enable writes to Flash memory.

Parallel Port Interface

The PCCchip2 provides an 8-bit bidirectional parallel port. All eight bits of the port must be either inputs or outputs (no individual selection). In addition to the 8 bits of data, there are two control pins and five status pins. Each of the status pins can generate an interrupt to the MPU in any of the following programmable conditions: high level, low level, high-to-low transition, or low-to-high transition. This port may be used as a Centronics-compatible parallel printer port or as a general parallel I/O port.

Functional Description

When used as a parallel printer port, the five status pins function as: Printer Acknowledge (ACK), Printer Fault (FAULT*), Printer Busy (BSY), Printer Select (SELECT), and Printer Paper Error (PE); while the control pins act as Printer Strobe (STROBE*), and Input Prime (INP*).

The PCCchip2 provides an auto-strobe feature similar to that of the MVME147 PCC. In auto-strobe mode, after a write to the Printer Data Register, the PCCchip2 automatically asserts the STROBE* pin for a selected time specified by the Printer Fast Strobe control bit. In manual mode, the Printer Strobe control bit directly controls the state of the STROBE* pin.

Ethernet Interface

The 82596CA is used to implement the Ethernet transceiver interface. The 82596CA accesses local RAM using DMA operations to perform its norm al functions. Because the 82596CA has small internal buffers and the VMEbus has an undefined latency period, buffer overrun may occur if the DMA is programmed to access the VMEbus. Therefore, the 82596CA should not be programmed to access the VMEbus or VSB.

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Board Level Hardware Description

Every MVME166 is assigned an Ethernet Station Address. The address is $08003E2XXXXX where XXXXX is the unique 5-nibble number assigned to the board (i.e., every MVME166 has a different value for XXXXX).

Each module has an Ethernet Station Address displayed on a label attached to the VMEbus P2 connector. In addition, the six bytes including the Ethernet address are stored in the configuration area of the BBRAM. That is, 08003E2XXXXX is stored in the BBRAM. At an address of $FFFC1F2C, the upper four bytes (08003E2X) can be read. At an address of $FFFC1F30, the lower two bytes (XXXX) can be read. The MVME166 debugger has the capability to retrieve or set the Ethernet address. So does the MVME166 BootBug.

If the data in the BBRAM is lost, the user should use the number on the VMEbus P2 connector label to restore it.

The Ethernet transceiver interface is located on the MVME166 main module, and the industry standard connector is located on the MVME712X transition module.

Support functions for the 82596CA are provided by the PCCchip2. Refer to the 82596CA user’s guide for detailed programming information.

SCSI Interface

The MVME166 provides for mass storage subsystems through the industrystandard SCSI bus. These subsystems may include hard and floppy disk drives, streaming tape drives, and other mass storage devices. The SCSI interface is implemented using the NCR 53C710 SCSI I/O controller.

Support functions for the 53C710 are provided by the PCCchip2. Refer to the 53C710 user’s guide for detailed programming information.

SCSI Termination

The individual configuring the system must ensure that the SCSI bus is properly terminated at both ends. On the MVME166, the SCSI bus termination is provided on the main board. The terminators are enabled/disabled by a jumper. If the SCSI bus ends at the MVME166, the SCSI terminators must be enabled by installing the jumper. Refer to the jumper configuration tables in Chapter 2.

Local Resources

The MVME166 includes many resources for the local processor. These include tick timers, software programmable hardware interrupts, watchdog timer, and local bus timeout.

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