Motorola MTY16N80E Datasheet
1
Motorola TMOS Power MOSFET Transistor Device Data
N–Channel Enhancement–Mode Silicon Gate
This high voltage MOSFET uses an advanced t ermination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. Designed f or high voltage, high speed
switching applications in power supplies, converters and PWM
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Diode is Characterized for Use in Bridge Circuits
• I
DSS
and V
DS(on)
Specified at Elevated Temperature
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–to–Source Voltage V
DSS
800 Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
DGR
800 Vdc
Gate–to–Source Voltage — Continuous
— Non–Repetitive (tp ≤ 10 ms)
V
GS
V
GSM
±20
±40
Vdc
Vpk
Drain Current — Continuous
— Continuous @ TC = 100°C
— Single Pulse (tp ≤ 10 µs)
I
D
I
D
I
DM
16
11
55
Adc
Apk
Total Power Dissipation
Derate above 25°C
P
D
300
2.4
Watts
W/°C
Operating and Storage Temperature Range TJ, T
stg
–55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 16 Apk, L = 10 mH, RG = 25 Ω )
E
AS
1280
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
R
θJC
R
θJA
0.42
30
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
L
260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics— are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
Order this document
by MTY16N80E/D
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
TMOS POWER FET
16 AMPERES
800 VOLTS
R
DS(on)
= 0.50 OHM
CASE 340G–02, STYLE 1
TO–264
Motorola Preferred Device
D
S
G
MTY16N80E
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
800
—
—
570
—
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 800 Vdc, VGS = 0 Vdc)
(VDS = 800 Vdc, VGS = 0 Vdc, TJ = 125°C)
I
DSS
—
—
—
—
10
100
µAdc
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) I
GSS
— — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
V
GS(th)
2.0
—
3.0
9.0
4.0
—
Vdc
mV/°C
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 8.0 Adc) R
DS(on)
— 0.42 0.5 Ohm
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 16 Adc)
(VGS = 10 Vdc, ID = 8.0 Adc, TJ = 125°C)
V
DS(on)
—
—
7.3
—
9.4
8.4
Vdc
Forward Transconductance (VDS ≥ 15 Vdc, ID = 8.0 Adc) g
FS
10 15 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 7220 10110 pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
C
oss
— 508 710
Reverse Transfer Capacitance
f = 1.0 MHz)
C
rss
— 65 130
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
d(on)
— 52 100 ns
Rise Time
t
r
— 112 200
Turn–Off Delay Time
VGS = 10 Vdc,
RG = 4.7 Ω)
t
d(off)
— 122 240
Fall Time
G
= 4.7 Ω)
t
f
— 100 200
Q
T
— 146 200 nC
(See Figure 8)
DS
= 400 Vdc, ID = 16 Adc,
Q
1
— 39 —
(VDS = 400 Vdc, ID = 16 Adc,
VGS = 10 Vdc)
Q
2
— 48 —
Q
3
— 53 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 16 Adc, VGS = 0 Vdc)
(IS = 16 Adc, VGS = 0 Vdc, TJ = 125°C)
V
SD
—
—
0.9
0.79
1.2
—
Vdc
t
rr
— 995 —
(See Figure 14)
S
= 16 Adc, VGS = 0 Vdc,
t
a
— 428 —
(IS = 16 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
t
b
— 567 —
Reverse Recovery Stored Charge Q
RR
— 20 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
D
— 4.5 —
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
— 13 —
nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
Gate Charge
Reverse Recovery Time
(VDD = 400 Vdc, ID = 16 Adc,
(V
(I
ns
MTY16N80E
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
100000
10000
1000
100
10
1
0 100 200 300 400 500 600 700 800
100°C
25°C
2.5
2.0
1.5
1.0
0.5
0
–50 –25 0 25 50 75 100 125 150
VGS = 10 V
ID = 8 A
0.6
0.5
0.4
324 8 12 16 2420
ID, DRAIN CURRENT (AMPS)
15 V
0.9
0.6
0
0 8 16
25°C
0.3
24
32
24
16
8
0
0 2 4 6 8 10 12 14 16 18 20
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
I
D
, DRAIN CURRENT (AMPS)
I
D
, DRAIN CURRENT (AMPS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance Variation with
Temperature
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
I
DSS
, LEAKAGE (nA)
16
12
8
4
0
2 3 4 5 6
TJ = 25°C
VGS = 10 V
VDS ≥ 10 V
VGS = 10 V
TJ = 100°C
–55°C
TJ = 25°C
VGS = 10 V
VGS = 0 V
TJ = 125°C
6 V
5 V
8 V
100°C
25°C
TJ = –55°C
32 28
4 V
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