Motorola MTY14N100E Datasheet
1
Motorola TMOS Power MOSFET Transistor Device Data
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS power FET is designed to withstand high
energy in the avalanche and commutation modes. This new energy
efficient design also o ffers a drain–to–source diode with f ast
recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters, PWM motor controls, and
other inductive loads. The avalanche energy capability is specified to
eliminate the g uesswork in designs where inductive loads are
switched and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Diode is Characterized for Use in Bridge Circuits
• I
DSS
and V
DS(on)
Specified at Elevated Temperature
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–to–Source Voltage V
DSS
1000 Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
DGR
1000 Vdc
Gate–to–Source Voltage — Continuous
— Single Pulse (tp ≤ 50 µs)
V
GS
V
GSM
±20
±40
Vdc
Vpk
Drain Current — Continuous
— Continuous @ TC = 100°C
— Single Pulse (tp ≤ 10 µs)
I
D
I
D
I
DM
14
8.7
49
Adc
Apk
Total Power Dissipation
Derate above 25°C
P
D
300
2.4
Watts
W/°C
Operating and Storage Temperature Range TJ, T
stg
–55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 14 Apk, L = 10 mH, RG = 25 Ω )
E
AS
980 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
R
θJC
R
θJA
0.42
30
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
L
260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics— are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
Order this document
by MTY14N100E/D
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1996
TMOS POWER FET
14 AMPERES
1000 VOLTS
R
DS(on)
= 0.80 OHM
CASE 340G–02, STYLE 1
TO–264
Motorola Preferred Device
D
S
G
MTY14N100E
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0, ID = 0.250 mAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
1000
—
—
1.0
—
—
Vdc
V/°C
Zero Gate Voltage Drain Current
(VDS = 1000 Vdc, VGS = 0 Vdc)
(VDS = 1000 Vdc, VGS = 0 Vdc, TJ = 125°C)
I
DSS
—
—
—
—
10
100
µAdc
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) I
GSS
— — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 0.250 mAdc)
Threshold Temperature Coefficient (Negative)
V
GS(th)
2.0
—
3.3
9.0
4.0
—
Vdc
mV/°C
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 7.0 Adc) R
DS(on)
— 0.67 0.8 Ohm
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 14 Adc)
(VGS = 10 Vdc, ID = 7.0 Adc, TJ = 125°C)
V
DS(on)
—
—
12.3
—
13.4
11.8
Vdc
Forward Transconductance (VDS ≥ 15 Vdc, ID = 7.0 Adc) g
FS
10 12 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 7230 pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
C
oss
— 462
Reverse Transfer Capacitance
f = 1.0 MHz)
C
rss
— 61
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
d(on)
— 49 ns
Rise Time
t
r
— 98
Turn–Off Delay Time
VGS = 10 Vdc,
RG = 9.1 Ω)
t
d(off)
— 132
Fall Time
G
= 9.1 Ω)
t
f
— 83
Q
T
— 142 nC
(See Figure 8)
DS
= 500 Vdc, ID = 14 Adc,
Q
1
— 34 —
(VDS = 500 Vdc, ID = 14 Adc,
VGS = 10 Vdc)
Q
2
— 46 —
Q
3
— 56 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 14 Adc, VGS = 0 Vdc)
(IS = 14 Adc, VGS = 0 Vdc, TJ = 125°C)
V
SD
—
—
1.36
1.26
1.5
—
Vdc
t
rr
— 831 —
(See Figure 14)
S
= 14 Adc, VGS = 0 Vdc,
t
a
— 364 —
(IS = 14 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
t
b
— 467 —
Reverse Recovery Stored Charge Q
RR
— 15.3 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
D
— 4.5 —
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
— 13 —
nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
Gate Charge
Reverse Recovery Time
(VDD = 500 Vdc, ID = 14 Adc,
(V
(I
ns
MTY14N100E
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
100000
10000
1000
100
10
1
0 100 200 300 400 500 600 700 800 900 1000
100°C
25°C
2.5
2.0
1.5
1.0
0.5
0
–50 –25 0 25 50 75 100 125 150
VGS = 10 V
ID = 7 A
0.85
0.8
0.75
0.7
0.65
0.6
0 4 8 12 16 2420
ID, DRAIN CURRENT (AMPS)
15 V
1.6
1.2
0.8
0
0 4 8 12 16 20
25°C
0.4
24
20
18
16
14
12
10
8
6
4
2
0
0 2 4 6 8 10 12 14 16 18 20
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
I
D
, DRAIN CURRENT (AMPS)
I
D
, DRAIN CURRENT (AMPS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance Variation with
Temperature
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
I
DSS
, LEAKAGE (nA)
30
25
20
15
10
5
0
2 3 4 5 6
TJ = 25°C
VGS = 10 V
VDS ≥ 10 V
VGS = 10 V
TJ = 100°C
–55°C
TJ = 25°C
VGS = 10 V
VGS = 0 V
TJ = 125°C
6 V
5 V
8 V
100°C
25°C
TJ = –55°C
28 28
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