Motorola MTY100N10E Datasheet
1
Motorola TMOS Power MOSFET Transistor Device Data
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS power FET is designed to withstand high
energy in the avalanche and commutation modes. This new energy
efficient design also o ffers a drain–to–source diode with f ast
recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters, PWM motor controls,
and other inductive loads. The avalanche energy capability is
specified to eliminate the guesswork in designs where inductive
loads are switched and o ffer additional safety margin against
unexpected voltage transients.
• Avalanche Energy Specified
• Diode is Characterized for Use in Bridge Circuits
• I
DSS
and V
DS(on)
Specified at Elevated Temperature
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–Source Voltage V
DSS
100 Vdc
Drain–Gate Voltage (RGS = 1 MΩ) V
DGR
100 Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
V
GS
V
GSM
±20
±40
Vdc
Vpk
Drain Current — Continuous @ TC = 25°C
Drain Current — Single Pulse (tp ≤ 10 µs)
I
D
I
DM
100
300
Adc
Apk
Total Power Dissipation
Derate above 25°C
P
D
300
2.38
Watts
W/°C
Operating and Storage Temperature Range TJ, T
stg
–55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 100 Apk, L = 0.1 mH, RG = 25 Ω )
E
AS
250 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
R
θJC
R
θJA
0.42
40
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
L
260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics— are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
Order this document
by MTY100N10E/D
SEMICONDUCTOR TECHNICAL DATA
TMOS POWER FET
100 AMPERES
100 VOLTS
R
DS(on)
= 0.011 OHM
CASE 340G–02, STYLE 1
TO–264
Motorola Preferred Device
D
S
G
Motorola, Inc. 1995
MTY100N10E
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0, ID = 250 µA)
Temperature Coefficient (Positive)
V
(BR)DSS
100
—
—
115
—
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125°C)
I
DSS
—
—
—
—
10
200
µAdc
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0) I
GSS
— — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
V
GS(th)
2.0
—
—
7
4
—
Vdc
mV/°C
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 50 Adc) R
DS(on)
— — 0.011 Ohm
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 100 Adc)
(ID = 50 Adc, TJ = 125°C)
V
DS(on)
—
—
1.0
—
1.2
1.0
Vdc
Forward Transconductance (VDS = 6 Vdc, ID = 50 Adc) g
FS
30 49 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 7600 10640 pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1 MHz)
C
oss
— 3300 4620
Reverse Transfer Capacitance
f = 1 MHz)
C
rss
— 1200 2400
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
d(on)
— 48 96 ns
Rise Time
t
r
— 490 980
Turn–Off Delay Time
VGS = 10 Vdc,
RG = 9.1 Ω)
t
d(off)
— 186 372
Fall Time
G
= 9.1 Ω)
t
f
— 384 768
Q
T
— 270 378 nC
(See Figure 8)
DS
= 80 Vdc, ID = 100 Adc,
Q
1
— 50 —
(VDS = 80 Vdc, ID = 100 Adc,
VGS = 10 Vdc)
Q
2
— 150 —
Q
3
— 118 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 100 Adc, VGS = 0 Vdc)
(IS = 100 Adc, VGS = 0 Vdc, TJ = 125°C)
V
SD
—
—
1
0.9
1.2
—
Vdc
t
rr
— 145 —
(See Figure 14)
S
= 100 Adc, VGS = 0 Vdc,
t
a
— 90 —
(IS = 100 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
t
b
— 55 —
Reverse Recovery Stored Charge Q
RR
— 2.34 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
D
— 4.5 — nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
— 13 — nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
Gate Charge
Reverse Recovery Time
(VDD = 50 Vdc, ID = 100 Adc,
(V
(I
ns
MTY100N10E
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
1000000
100000
1000
100
1
0 40 80 100 120
1.8
1.6
1.4
1.2
0.8
0.6
–50 –25 0 25 50 75 100 125 150
0.011
0.0105
0.01
0.0095
0.009
0.008
ID, DRAIN CURRENT (AMPS)
15 V
0.018
0.016
0.014
0.012
0.006
0 100 200
25°C
15050
200
0
0 2 4 6 8 10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
I
D
, DRAIN CURRENT (AMPS)
I
D
, DRAIN CURRENT (AMPS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance Variation with
Temperature
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
I
DSS
, LEAKAGE (nA)
0
VGS = 10 V
VDS ≥ 10 V
VGS = 10 V
TJ = 100°C
–55°C
VGS = 10 V
VGS = 0 V
160
120
120
80
60
2 3 4 5 6 10
0 100 20015050
TJ = 125°C
0.01
0.008
20
100
40
20
7 8 9
0.0085
1
10
60
TJ = 25°C
80
40
9 V
8 V
7 V
6 V
5 V
TJ = 25°C
100°C
25°C
TJ = –55°C
25°C
100°C
VGS = 10 V
ID = 50 A
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