Motorola MTW6N100E Datasheet
SEMICONDUCTOR TECHNICAL DATA
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N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
6.0 AMPERES
1000 VOL TS
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
R
DS(on)
= 1.5 OHM
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
D
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I
DSS
and V
Specified at Elevated Temperature
DS(on)
G
S
CASE 340K–01, Style 1
TO–247AE
• Isolated Mounting Hole Reduces Mounting Hardware
MAXIMUM RATINGS
Drain–Source Voltage V
Drain–Gate Voltage (RGS = 1.0 MΩ) V
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation
Derate above 25°C
Operating and Storage Temperature Range TJ, T
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 27.77 mH, RG = 25 Ω)
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
(TC = 25°C unless otherwise noted)
Rating Symbol Value Unit
V
V
I
E
R
R
DSS
DGR
GS
GSM
I
D
I
D
DM
P
D
stg
AS
θJC
θJA
L
1000 Vdc
1000 Vdc
± 20
± 40
6.0
4.2
18
180
1.43
–55 to 150 °C
720 mJ
0.70
40
260 °C
Vdc
Vpk
Adc
Apk
Watts
W/°C
°C/W
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 3
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1996
1
MTW6N100E
f = 1.0 MHz)
V
10 Vd
G
9)
V
)
(
S
,
GS
,
ELECTRICAL CHARACTERISTICS
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
T emperature Coef ficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 1000 Vdc, VGS = 0 Vdc)
(VDS = 1000 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) I
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
T emperature Coef ficient (Negative)
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 3.0 Adc) R
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 6.0 Adc)
(ID = 3.0 Adc, TJ = 125°C)
Forward Transconductance (VDS = 10 Vdc, ID = 3.0 Adc) g
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
Reverse Recovery Time
(See Figure 14)
Reverse Recovery Stored Charge Q
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(TJ = 25°C unless otherwise noted)
(VDS = 25 Vdc, VGS = 0 Vdc,
(VDD = 500 Vdc, ID = 6.0 Adc,
(VDS = 800 Vdc, ID = 6.0 Adc,
(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125°C)
f = 1.0 MHz
c,
=
GS
RG = 9.1 Ω)
= 10 Vdc
GS
(IS = 6.0 Adc, VGS = 0 Vdc)
(IS = 6.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
V
(BR)DSS
I
DSS
GSS
V
GS(th)
DS(on)
V
DS(on)
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
Q
Q
Q
V
SD
t
rr
t
a
t
b
RR
L
D
L
S
1000
—
—
—
— — 100 nAdc
2.0
—
— 1.28 1.5 Ohm
—
—
4.0 7.2 — mhos
— 3000 4210 pF
— 219 440
— 43 90
— 27 45 ns
— 29 65
— 93 170
— 43 95
T
1
2
3
— 66 100 nC
— 12.5 —
— 25.9 —
— 26 —
—
—
— 735 —
— 188 —
— 547 —
— 4.7 — µC
— 4.5 — nH
— 13 — nH
—
1,270
—
—
3.0
7.0
8.0
—
0.808
0.64
—
—
10
100
4.0
—
14.4
12.6
1.0
—
Vdc
mV/°C
µAdc
Vdc
mV/°C
Vdc
Vdc
ns
2
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
MTW6N100E
12
TJ = 25°C
10
8
6
4
, DRAIN CURRENT (AMPS)
D
I
2
0
048121620
2 6 10 14 18
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)
VGS = 10 V
6 V
5 V
4 V
Figure 1. On–Region Characteristics
2.9
VGS = 10 V
2.5
2.1
1.7
1.3
0.9
, DRAIN–TO–SOURCE RESIST ANCE (OHMS)
0.5
DS(on)
R
02 68
ID, DRAIN CURRENT (AMPS)
T
= 100°C
J
25°C
–55°C
41012
12
VDS ≥ 10 V
10
8
6
4
, DRAIN CURRENT (AMPS)
D
I
2
0
2.0 2.8 3.6 4.4 5.22.4 3.2 4.0 4.8
VGS, GATE–T O–SOURCE VOLTAGE (VOLTS)
25°C
100°C
TJ = –55°C
Figure 2. Transfer Characteristics
1.56
TJ = 25°C
1.52
1.48
1.44
1.40
1.36
1.32
, DRAIN–TO–SOURCE RESIST ANCE (OHMS)
1.28
1.24
DS(on)
R
02 8 1117912
VGS = 10 V
15 V
3546 10
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and T emperature
2.8
VGS = 10 V
2.4
2.0
1.6
(NORMALIZED)
1.2
, DRAIN–TO–SOURCE RESIST ANCE
0.8
DS(on)
R
0.4
ID = 3 A
–50
–25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance Variation with
Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
100000
V
= 0 V
GS
10000
1000
100
, LEAKAGE (nA)
DSS
I
10
1
0 300 700
200 500 1000
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)
TJ = 125°C
100°C
400 600 800100
Figure 6. Drain–T o–Source Leakage
Current versus Voltage
25°C
900
Motorola TMOS Power MOSFET Transistor Device Data
3
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