Motorola MTV16N50E Datasheet
1
Motorola TMOS Power MOSFET Transistor Device Data
$ " !!"
# #"
N–Channel Enhancement–Mode Silicon Gate
This h igh v oltage M OSFET u ses a n advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
speed switching applications in power supplies, converters, PWM
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I
DSS
and V
DS(on)
Specified at Elevated Temperature
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–to–Source Voltage V
DSS
500 Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
DGR
500 Vdc
Gate–to–Source Voltage — Continuous V
GS
±20 Vdc
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
I
D
I
D
I
DM
16
9.0
60
Adc
Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
P
D
180
1.4
2.0
Watts
W/°C
Watts
Operating and Storage Temperature Range TJ, T
stg
–55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc, Peak IL = 16 Apk, L = 6.7 mH, RG = 25 Ω )
E
AS
860
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
R
θJC
R
θJA
R
θJA
0.7
62.5
35
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
L
260 °C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Order this document
by MTV16N50E/D
SEMICONDUCTOR TECHNICAL DATA
CASE 433–01, Style 2
D3PAK Surface Mount
TMOS POWER FET
16 AMPERES
500 VOLTS
R
DS(on)
= 0.40 OHM
D
S
G
N–Channel
Motorola, Inc. 1996
MTV16N50E
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
500
—
—
520
—
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125°C)
I
DSS
—
—
—
—
250
1000
µAdc
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0) I
GSS
— — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
V
GS(th)
2.0
—
3.2
7.0
4.0
—
Vdc
mV/°C
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 8.0 Adc) R
DS(on)
— 0.32 0.40 Ohm
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 16 Adc)
(VGS = 10 Vdc, ID = 8.0 Adc, TJ = 125°C)
V
DS(on)
—
—
—
—
6.7
5.6
Vdc
Forward Transconductance (VDS = 15 Vdc, ID = 8.0 Adc) g
FS
5.0 — — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 3200 4480 pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
C
oss
— 400 560
Transfer Capacitance
f = 1.0 MHz)
C
rss
— 320 448
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
d(on)
— 28 60 ns
Rise Time
t
r
— 80 160
Turn–Off Delay Time
VGS = 10 Vdc,
RG = 4.7 Ω)
t
d(off)
— 80 160
Fall Time
G
= 4.7 Ω)
t
f
— 60 120
Q
T
— 65 — nC
(See Figure 8)
DS
= 400 Vdc, ID = 16 Adc,
Q
1
— 17 —
(VDS = 400 Vdc, ID = 16 Adc,
VGS = 10 Vdc)
Q
2
— 47 —
Q
3
— 34 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 16 Adc, VGS = 0 Vdc)
(IS = 16 Adc, VGS = 0 Vdc, TJ = 125°C)
V
SD
—
—
1.0
0.9
1.6
—
Vdc
t
rr
— 390 —
S
= 16 Adc, VGS = 0 Vdc,
t
a
— 245 —
(IS = 16 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
t
b
— 145 —
Reverse Recovery Stored Charge Q
RR
— 5.35 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
D
— 5.0 —
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
— 13 —
nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
Gate Charge
Reverse Recovery Time
(VDD = 250 Vdc, ID = 16 Adc,
(V
(I
ns
MTV16N50E
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
0 2 4 6 8 10
0
4
8
12
20
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
I
D
, DRAIN CURRENT (AMPS)
I
D
, DRAIN CURRENT (AMPS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0 5 10 15 20
0.2
0.6
0.8
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
0 5 10 15 20
0.15
0.3
0.4
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
ID, DRAIN CURRENT (AMPS)
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
–50
0
0.5
1.0
1.5
2.0
0 100 200 300 400 500
10
100
1000
10000
100000
TJ, JUNCTION TEMPERATURE (
°
C)
Figure 5. On–Resistance Variation with
Temperature
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
I
DSS
, LEAKAGE (nA)
0 50 10025 150
TJ = 25
°C
VDS ≥ 10 V
TJ = –55
°C
25
°C
100
°C
TJ = 100
°C
25
°C
–55
°C
TJ = 25
°C
VGS = 0 V
VGS = 10 V
VGS = 10 V
VGS = 10 V
ID = 8 A
1 3 5 7 9
2
6
10
14
9 V
6 V
5 V
4 V
7 V
0.4
0.0
25 30 35
0.35
25 30 35
VGS = 10 V
15 V
TJ = 125
°C
100
°C
25
°C
16
18
0 2 4 6 8 10
0
4
8
12
20
1 3 5 7 9
2
6
10
14
16
18
0.2
0.25
2.5
0.1
0.5
0.7
0.3
–25 75 125
Loading...