Motorola MTSF1P02HDR2 Datasheet
1
Motorola TMOS Power MOSFET Transistor Device Data
Medium Power Surface Mount Products
Micro8 devices are an advanced series of power MOSFETs
which utilize Motorola’s High Cell Density HDTMOS process to
achieve lowest possible on–resistance per silicon area. They are
capable of withstanding high energy in the avalanche and commutation modes and the drain–to–source diode has a very low reverse
recovery time. Micro8 devices are designed for use in low voltage,
high speed switching applications where power efficiency is important.
Typical applications are dc–dc converters, and power management in
portable and battery powered products such as computers, printers,
cellular and cordless phones. They can also be used for low voltage
motor controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the guesswork
in designs where inductive loads are switched and offer additional
safety margin against unexpected voltage transients.
• Miniature Micro8 Surface Mount Package — Saves Board Space
• Extremely Low Profile (<1.1mm) for thin applications such as
PCMCIA cards
• Ultra Low R
DS(on)
Provides Higher Efficiency and Extends Battery Life
• Logic Level Gate Drive — Can Be Driven by Logic ICs
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, With Soft Recovery
• I
DSS
Specified at Elevated Temperature
• Avalanche Energy Specified
• Mounting Information for Micro8 Package Provided
MAXIMUM RATINGS
(TJ = 25°C unless otherwise noted) *
Rating
Symbol Value Unit
Drain–to–Source Voltage V
DSS
20 Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
DGR
20 Vdc
Gate–to–Source Voltage — Continuous V
GS
± 8.0 Vdc
Drain Current — Continuous @ TA = 25°C (2)
Drain Current — Continuous @ TA = 70°C (2)
Drain Current — Pulsed Drain Current (3)
I
D
I
D
I
DM
1.8
1.6
14.4
Adc
Apk
Total Power Dissipation @ TA = 25°C (1)
Linear Derating Factor (1)
P
D
1.8
14.3
Watts
mW/°C
Total Power Dissipation @ TA = 25°C (2)
Linear Derating Factor (2)
P
D
0.78
6.25
Watts
mW/°C
Operating and Storage Temperature Range TJ, T
stg
– 55 to 150 °C
THERMAL RESISTANCE
Rating Symbol Typ. Max. Unit
Thermal Resistance — Junction to Ambient, PCB Mount (1)
Thermal Resistance — Junction to Ambient, PCB Mount (2)
R
θJA
R
θJA
55
125
70
160
°C/W
* Negative signs for P–Channel device omitted for clarity.
(1) When mounted on 1 inch square FR–4 or G–10 board (VGS = 4.5 V, @ Steady State)
(2) When mounted on minimum recommended FR–4 or G–10 board (VGS = 4.5 V, @ Steady State)
(3) Repetitive rating; pulse width limited by maximum junction temperature.
DEVICE MARKING ORDERING INFORMATION
Device Reel Size Tape Width Quantity
AB
MTSF1P02HDR2 13″ 12 mm embossed tape 4000 units
This document contains information on a new product. Specifications and information are subject to change without notice.
Preferred devices are Motorola recommended choices for future use and best overall value.
HDTMOS is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Micro8 is a registered trademark of International
Rectifier. Thermal Clad is a trademark of the Berquist Company.
REV 1
Order this document
by MTSF1P02HD/D
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1996
D
S
G
SINGLE TMOS
POWER FET
1.8 AMPERES
20 VOLTS
R
DS(on)
= 0.16 OHM
Motorola Preferred Device
Source
1
2
3
4
8
7
6
5
Top View
Source
Source
Gate
Drain
Drain
Drain
Drain
CASE 846A–02, Style 1
Micro8
MTSF1P02HD
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TC = 25°C unless otherwise noted)
(1)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage (Cpk ≥ 2.0) (1) (3)
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
20
—
—
12.8
—
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 16 Vdc, VGS = 0 Vdc)
(VDS = 16 Vdc, VGS = 0 Vdc, TJ = 125°C)
I
DSS
—
—
—
—
1.0
10
µAdc
Gate–Body Leakage Current (VGS = ± 8.0 Vdc, VDS = 0 Vdc) I
GSS
— — 100 nAdc
ON CHARACTERISTICS
(2)
Gate Threshold Voltage (Cpk ≥ 2.0) (3)
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
V
GS(th)
0.6
—
0.8
2.5
—
—
Vdc
mV/°C
Static Drain–to–Source On–Resistance (3)
(VGS = 4.5 Vdc, ID = 1.8 Adc)
(VGS = 2.7 Vdc, ID = 0.9 Adc)
R
DS(on)
—
—
120
160
160
190
mΩ
Forward Transconductance (VDS = 10 Vdc, ID = 0.9 Adc) (1) g
FS
2.0 4.0 — Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 440 — pF
Output Capacitance
(VDS = 10 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
C
oss
— 300 —
Transfer Capacitance
f = 1.0 MHz)
C
rss
— 150 —
SWITCHING CHARACTERISTICS
(3)
Turn–On Delay Time
t
d(on)
— 15 —
ns
Rise Time
(V
DS
= 10 Vdc, ID = 1.8 Adc,
t
r
— 35 —
Turn–Off Delay Time
(VDS = 10 Vdc, ID = 1.8 Adc,
VGS = 4.5 Vdc, RG = 6.0 Ω) (1)
t
d(off)
— 55 —
Fall Time t
f
— 75 —
Turn–On Delay Time
t
d(on)
— 20 —
Rise Time
(V
DD
= 10 Vdc, ID = 0.9 Adc,
t
r
— 93 —
Turn–Off Delay Time
(VDD = 10 Vdc, ID = 0.9 Adc,
VGS = 2.7 Vdc, RG = 6.0 Ω) (1)
t
d(off)
— 50 —
Fall Time t
f
— 75 —
Gate Charge
Q
T
— 11 22 nC
(V
DS
= 10 Vdc, ID = 1.8 Adc,
Q
1
— 0.7 —
(VDS = 10 Vdc, ID = 1.8 Adc,
VGS = 4.5 Vdc)
Q
2
— 5.5 —
Q
3
— 3.8 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 1.8 Adc, VGS = 0 Vdc) (1)
(IS = 1.8 Adc, VGS = 0 Vdc, TJ = 125°C)
V
SD
—
—
1.24
0.9
2.0
—
Vdc
Reverse Recovery Time
t
rr
— 120 —
ns
(I
S
= 1.8 Adc, VGS = 0 Vdc,
t
a
— 33 —
(IS = 1.8 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs) (1)
t
b
— 87 —
Reverse Recovery Stored Charge Q
RR
— 0.223 — µC
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Cpk =
Max limit – Typ
3 x SIGMA
MTSF1P02HD
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
0
1.2
1.6
0.4
2
0.8
0 0.4 0.8 2
0
1.2
1.6
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
I
D
, DRAIN CURRENT (AMPS)
0.4 0.8 1.2 1.6 2
I
D
, DRAIN CURRENT (AMPS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0 2 4
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
0 0.5 1 1.5 2
0.1
0.16
0.18
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 3. On–Resistance versus
Gate–To–Source Voltage
ID, DRAIN CURRENT (AMPS)
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
0
2.0
1
100
1000
TJ, JUNCTION TEMPERATURE (
°
C)
Figure 5. On–Resistance Variation with
Temperature
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
I
DSS
, LEAKAGE (nA)
TJ = 25°C
VDS ≥ 10 V
TJ = 100°C
25°C
–55°C
TJ = 25°C
VGS = 0 V
VGS = 4.5 V
ID = 1.8 A
TJ = 25
°
C
4.5 V
VGS = 2.7 V
ID = 1.8 A
1.2
2.7 V
2 V
1.8 V
1.6 V
0.4
1.6
6 8
2.7 V
–50 –25 0 25 50 75 100 125 150
TJ = 125°C
2
0.14
0.5
0.8
1.0
1.5
0 4 8 12 20
1.7 V
0.6
0.5
0.4
0.3
0.2
0.1
0
0.12
10
100°C
1.9 V
1.5 V
1.4 V
25°C
16
MTSF1P02HD
4
Motorola TMOS Power MOSFET Transistor Device Data
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
G(AV)
) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, V
SGP
. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – V
GSP
)
tf = Q2 x RG/V
GSP
where
VGG = the gate drive voltage, which varies from zero to V
GG
RG = the gate drive resistance
and Q2 and V
GSP
are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= RG C
iss
In [VGG/(VGG – V
GSP
)]
t
d(off)
= RG C
iss
In (VGG/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating t
d(on)
and is read at a voltage corresponding to the
on–state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The M OSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
VDS, DRAIN–TO–SOURCE VOLTAGE (Volts)
C, CAPACITANCE (pF)
1500
2000
Figure 7. Capacitance Variation
10 0 10 15 20
V
GS
V
DS
5 5
TJ = 25°C
C
iss
C
oss
C
rss
1000
500
VDS = 0 V VGS = 0 V
C
iss
C
rss
0
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