Motorola MTP9N25E Datasheet
1
Motorola TMOS Power MOSFET Transistor Device Data
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in p ower supplies, converters and P WM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I
DSS
and V
DS(on)
Specified at Elevated Temperature
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–to–Source Voltage V
DSS
250 Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
DGR
250 Vdc
Gate–to–Source Voltage — Continuous
— Non–Repetitive (tp ≤ 10 ms)
V
GS
V
GSM
± 20
± 40
Vdc
Vpk
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (tp ≤ 10 µs)
I
D
I
D
I
DM
9.0
5.7
32
Adc
Apk
Total Power Dissipation
Derate above 25°C
P
D
80
0.64
Watts
W/°C
Operating and Storage Temperature Range TJ, T
stg
–55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 3.0 mH, RG = 25 Ω)
E
AS
122
mJ
Thermal Resistance — Junction to Case
— Junction to Ambient
R
θJC
R
θJA
1.56
62.5
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
L
260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
Order this document
by MTP9N25E/D
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
TMOS POWER FET
9.0 AMPERES
250 VOLTS
R
DS(on)
= 0.45 OHM
Motorola Preferred Device
D
S
G
CASE 221A–06, Style 5
TO–220AB
MTP9N25E
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
250
—
—
328
—
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 250 Vdc, VGS = 0 Vdc)
(VDS = 250 Vdc, VGS = 0 Vdc, TJ = 125°C)
I
DSS
—
—
—
—
10
100
µAdc
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) I
GSS
— — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
V
GS(th)
2.0
—
3.0
7.0
4.0
—
Vdc
mV/°C
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 4.5 Adc) R
DS(on)
— 0.37 0.45 Ohm
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 9.0 Adc)
(VGS = 10 Vdc, ID = 4.5 Adc, TJ = 125°C)
V
DS(on)
—
—
3.5
—
5.4
4.7
Vdc
Forward Transconductance (VDS = 15 Vdc, ID = 4.5 Adc) g
FS
3.0 5.2 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 783 1100 pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
C
oss
— 144 200
Reverse Transfer Capacitance
f = 1.0 MHz)
C
rss
— 32 65
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
d(on)
— 10 20 ns
Rise Time
t
r
— 36 70
Turn–Off Delay Time
VGS = 10 Vdc,
RG = 9.1 Ω)
t
d(off)
— 27 55
Fall Time
G
= 9.1 Ω)
t
f
— 26 50
Q
T
— 26 40 nC
(See Figure 8)
DS
= 200 Vdc, ID = 9.0 Adc,
Q
1
— 4.8 —
(VDS = 200 Vdc, ID = 9.0 Adc,
VGS = 10 Vdc)
Q
2
— 12.7 —
Q
3
— 9.2 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 9.0 Adc, VGS = 0 Vdc)
(IS = 9.0 Adc, VGS = 0 Vdc, TJ = 125°C)
V
SD
—
—
0.9
0.81
1.5
—
Vdc
t
rr
— 191 —
(See Figure 14)
S
= 9.0 Adc, VGS = 0 Vdc,
t
a
— 126 —
(IS = 9.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
t
b
— 65 —
Reverse Recovery Stored Charge Q
RR
— 1.387 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
L
D
—
—
3.5
4.5
—
—
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
— 7.5 —
nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
Gate Charge
Reverse Recovery Time
(VDD = 125 Vdc, ID = 9.0 Adc,
(V
(I
ns
MTP9N25E
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
0 2 4 6 8 10
9
15
18
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
I
D
, DRAIN CURRENT (AMPS)
I
D
, DRAIN CURRENT (AMPS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0 3 6 9 12 15
0
0.2
0.4
0.8
1.2
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
ID, DRAIN CURRENT (AMPS)
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
–50
0
0.5
1.0
1.5
2.0
0 100 200
1
10
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance Variation with
Temperature
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
I
DSS
, LEAKAGE (nA)
–25 0 25 50 75 100 125 150
TJ = 25°C
VDS ≥ 10 V
TJ = –55°C
100°C
TJ = 100°C
25°C
–55°C
TJ = 25°C
VGS = 0 V
VGS = 10 V
6
12
3
5 V
6 V
7 V
VGS = 10 V
2 3 4 5 6 7
1.0
0.6
50 150 250
TJ = 125°C
0
9
15
18
6
12
3
0
18
0.3
0.4
0.5
0.6
0 3 6 9 12 15 18
15 V
25°C
25°C
100°C
VGS = 10 V
ID = 4.5 A
VGS = 10 V
8 V
12
9 V
8
2.5
1000
0.1
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