Motorola MTP52N06V Datasheet
SEMICONDUCTOR TECHNICAL DATA
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resistance area product about one–half that of standard MOSFET s. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low R
• Faster Switching than E–FET Predecessors
DS(on)
Technology
G
Order this document
by MTP52N06V/D
Motorola Preferred Device
TMOS POWER FET
52 AMPERES
60 VOLTS
R
TM
D
DS(on)
= 0.022 OHM
Features Common to TMOS V and TMOS E–FETS
• Avalanche Energy Specified
• I
DSS
and V
Specified at Elevated Temperature
DS(on)
• Static Parameters are the Same for both TMOS V and TMOS E–FET
MAXIMUM RATINGS
Drain–Source Voltage V
Drain–Gate Voltage (RGS = 1.0 MΩ) V
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation
Derate above 25°C
Operating and Storage Temperature Range TJ, T
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 52 Apk, L = 0.3 mH, RG = 25 Ω)
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
(TC = 25°C unless otherwise noted)
Rating Symbol Value Unit
S
CASE 221A–06, Style 5
TO–220AB
60 Vdc
60 Vdc
± 20
± 25
52
41
182
188
1.25
–55 to 175 °C
406 mJ
0.8
62.5
260 °C
Vdc
Vpk
Adc
Apk
Watts
W/°C
°C/W
V
V
I
E
R
R
DSS
DGR
GS
GSM
I
D
I
D
DM
P
D
stg
AS
θJC
θJA
L
REV 3
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1996
1
MTP52N06V
)
f = 1.0 MHz)
V
G
)
(
DS
,
D
,
(
S
,
GS
,
ELECTRICAL CHARACTERISTICS
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage (Cpk ≥ 2.0) (3)
(VGS = 0 Vdc, ID = 0.25 mAdc)
T emperature Coef ficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) I
ON CHARACTERISTICS (1)
Gate Threshold Voltage (Cpk ≥ 2.0) (3)
(VDS = VGS, ID = 250 µAdc)
T emperature Coef ficient (Negative)
Static Drain–Source On–Resistance (Cpk ≥ 2.0) (3)
(VGS = 10 Vdc, ID = 26 Adc)
Drain–Source On–Voltage
(VGS = 10 Vdc, ID = 52 Adc)
(VGS = 10 Vdc, ID = 26 Adc, TJ = 150°C)
Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc) g
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
Reverse Recovery Time
(See Figure 14)
Reverse Recovery Stored Charge Q
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Cpk =
(T
= 25°C unless otherwise noted)
J
Characteristic
(VDS = 25 Vdc, VGS = 0 Vdc,
(IS = 52 Adc, VGS = 0 Vdc, TJ = 150°C)
Max limit – Typ
3 x SIGMA
f = 1.0 MHz
(VDD = 30 Vdc, ID = 52 Adc,
(VDS = 48 Vdc, ID = 52 Adc,
(IS = 52 Adc, VGS = 0 Vdc)
(IS = 52 Adc, VGS = 0 Vdc,
= 10 Vdc,
GS
RG = 9.1 Ω)
VGS = 10 Vdc)
dIS/dt = 100 A/µs)
Symbol Min Typ Max Unit
V
(BR)DSS
I
DSS
GSS
V
GS(th)
R
DS(on)
V
DS(on)
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
V
SD
t
rr
t
a
t
b
RR
L
D
L
S
60
—
—
—
— — 100 nAdc
2.0
—
— 0.019 0.022
—
—
17 24 — mhos
— 1900 2660 pF
— 580 810
— 150 300
— 12 20 ns
— 298 600
— 70 140
— 110 220
— 125 175 nC
— 10 —
— 30 —
— 40 —
—
—
— 100 —
— 80 —
— 20 —
— 0.341 — µC
—
—
— 7.5 —
—
66
—
—
2.7
6.4
—
—
1.0
0.98
3.5
4.5
—
—
10
100
4.0
—
1.4
1.2
1.5
—
—
—
mV/°C
mV/°C
Vdc
µAdc
Vdc
Ohm
Vdc
Vdc
ns
nH
nH
2
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
MTP52N06V
110
100
90
80
70
60
50
40
, DRAIN CURRENT (AMPS)
30
D
I
20
10
0
0.035
0.03
0.025
0.02
0.015
0.01
, DRAIN–TO–SOURCE RESIST ANCE (OHMS)
0.005
0
DS(on)
R
VGS = 10 V
9 V
13579
20 7.57532.5
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)
8 V
46810
TJ = 25°C
7 V
6 V
5 V
Figure 1. On–Region Characteristics
VGS = 10 V
TJ = 100°C
25°C
–55°C
200
40 60 80 100
3010 50 70 90 110
ID, DRAIN CURRENT (AMPS)
110
VDS ≥ 10 V
100
90
80
70
60
50
40
, DRAIN CURRENT (AMPS)
30
D
I
20
10
0
2468
3.5 4.5 5.5 6.5
VGS, GATE–T O–SOURCE VOLTAGE (VOLTS)
TJ = –55°C
100°C
25°C
Figure 2. Transfer Characteristics
0.023
0.022
0.021
0.020
0.019
0.018
0.017
, DRAIN–TO–SOURCE RESIST ANCE (OHMS)
0.016
0.015
DS(on)
R
TJ = 25°C
VGS = 10 V
15 V
15 35 55 75 95
5
25 45 65 85 105
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and T emperature
2
VGS = 10 V
1.75
ID = 26 A
1.5
1.25
1
(NORMALIZED)
0.75
, DRAIN–TO–SOURCE RESIST ANCE
0.5
DS(on)
R
0.25
–50 –25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance Variation with
Temperature
175
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
100
VGS = 0 V
10
, LEAKAGE (nA)
DSS
I
1
0102030405060
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)
TJ = 125°C
100°C
Figure 6. Drain–T o–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
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