Motorola MTP50P03HDL Datasheet
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTP50P03HDL/D
Motorola Preferred Device
P–Channel Enhancement–Mode Silicon Gate
This advanced high–cell density HDTMOS power FET is
designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a Dis-
crete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I
MAXIMUM RATINGS
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
and V
DSS
Drain–Source Voltage V
Drain–Gate Voltage (RGS = 1.0 MΩ) V
Gate–Source Voltage — Continuous
— Non–Repetitive (tp ≤ 10 ms)
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation
Derate above 25°C
Operating and Storage Temperature Range TJ, T
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 50 Apk, L = 1.0 mH, RG = 25 Ω)
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
Specified at Elevated Temperature
DS(on)
(TC = 25°C unless otherwise noted)
D
G
S
Rating
TMOS POWER FET
LOGIC LEVEL
50 AMPERES
30 VOLTS
R
CASE 221A–06, Style 5
Symbol Value Unit
DSS
DGR
V
GS
V
GSM
I
D
I
D
I
DM
P
D
E
AS
R
θJC
R
θJA
L
= 0.025 OHM
DS(on)
TO–220AB
± 15
± 20
150
125
–55 to 150 °C
stg
1250 mJ
62.5
260 °C
30 Vdc
30 Vdc
Vdc
Vpk
50
31
1.0
1.0
Adc
Apk
Watts
W/°C
°C/W
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1997
1
MTP50P03HDL
)
f = 1.0 MHz)
V
RG 2.3 Ω)
(
DS
,
D
,
(
S
,
GS
,
ELECTRICAL CHARACTERISTICS
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (3)
(VGS = 0 Vdc, ID = 250 µAdc)
T emperature Coef ficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current
(VGS = ± 15 Vdc, VDS = 0 Vdc)
ON CHARACTERISTICS (1)
Gate Threshold Voltage (Cpk ≥ 3.0) (3)
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
Static Drain–to–Source On–Resistance (Cpk ≥ 3.0) (3)
(VGS = 5.0 Vdc, ID = 25 Adc)
Drain–to–Source On–Voltage (VGS = 10 Vdc)
(ID = 50 Adc)
(ID = 25 Adc, TJ = 125°C)
Forward Transconductance
(VDS = 5.0 Vdc, ID = 25 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
Reverse Recovery Time
(See Figure 15)
Reverse Recovery Stored Charge Q
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Cpk =
(TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
(VDS = 25 Vdc, VGS = 0 Vdc,
(IS = 50 Adc, VGS = 0 Vdc, TJ = 125°C)
Max limit – Typ
3 x SIGMA
f = 1.0 MHz
(VDD = 15 Vdc, ID = 50 Adc,
(VDS = 24 Vdc, ID = 50 Adc,
(IS =50 Adc, VGS = 0 Vdc)
(IS = 50 Adc, VGS = 0 Vdc,
= 5.0 Vdc,
GS
RG = 2.3 Ω)
VGS = 5.0 Vdc)
dIS/dt = 100 A/µs)
V
(BR)DSS
I
DSS
I
GSS
V
GS(th)
R
DS(on)
V
DS(on)
g
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
Q
Q
Q
V
SD
t
rr
t
a
t
b
RR
L
D
L
S
30
—
—
—
— — 100
1.0
—
— 0.020 0.025
—
—
15 20 —
— 3500 4900 pF
— 1550 2170
— 550 770
— 22 30 ns
— 340 466
— 90 117
— 218 300
T
1
2
3
— 74 100 nC
— 13.6 —
— 44.8 —
— 35 —
—
—
— 106 —
— 58 —
— 48 —
— 0.246 — µ C
—
—
— 7.5 —
—
26
—
—
1.5
4.0
0.83
—
2.39
1.84
3.5
4.5
—
—
1.0
10
2.0
—
1.5
1.3
3.0
—
—
—
Vdc
mV/°C
µAdc
nAdc
Vdc
mV/°C
Ohm
Vdc
mhos
Vdc
ns
nH
nH
2
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
MTP50P03HDL
100
TJ = 25°C
80
60
40
, DRAIN CURRENT (AMPS)
D
I
20
0
0 0.4 0.8 1.2 1.6 2.00.2 0.6 1.0 1.4 1.8
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS) VGS, GATE–T O–SOURCE VOLT AGE (VOLTS)
VGS = 10 V
8 V
6 V
Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics
0.029
V
= 5.0 V
GS
0.027
0.025
0.023
0.021
TJ = 100°C
25°C
5 V
4.5 V
4 V
3.5 V
3 V
2.5 V
100
VDS ≥ 10 V
80
60
40
, DRAIN CURRENT (AMPS)
D
I
20
0
1.5 1.9 2.3 2.7 3.5 4.33.1 3.9
0.022
TJ = 25°C
0.021
0.020
0.019
0.018
VGS = 5 V
TJ = – 55°C
25°C
100°C
0.019
, DRAIN–TO–SOURCE RESIST ANCE (OHMS)
0.017
DS(on)
0.015
R
020406080100
ID, DRAIN CURRENT (AMPS)
–55°C
Figure 3. On–Resistance versus Drain Current
and T emperature
1.35
VGS = 5 V
ID = 25 A
1.25
1.15
1.05
(NORMALIZED)
, DRAIN–TO–SOURCE RESIST ANCE
0.95
DS(on)
R
0.85
– 50 – 25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (
°
C)
0.017
, DRAIN–TO–SOURCE RESIST ANCE (OHMS)
0.016
0.015
DS(on)
R
020406080100
ID, DRAIN CURRENT (AMPS)
10 V
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
1000
VGS = 0 V
TJ = 125°C
100
, LEAKAGE (nA)
DSS
I
100°C
10
0 5 10 20 25 30
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)
15
Figure 5. On–Resistance Variation with
Temperature
Motorola TMOS Power MOSFET Transistor Device Data
Figure 6. Drain–T o–Source Leakage
Current versus Voltage
3
Loading...