Motorola MTP50N06EL Datasheet
1
Motorola TMOS Power MOSFET Transistor Device Data
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in p ower supplies, converters and P WM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I
DSS
and V
DS(on)
Specified at Elevated Temperature
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–Source Voltage V
DSS
60 Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ) V
DGR
60 Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
V
GS
V
GSM
±15
±30
Vdc
Vpk
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (tp ≤ 10 µs)
I
D
I
D
I
DM
50
38
160
Adc
Apk
Total Power Dissipation @ TC = 25°C
Derate above 25°C
P
D
150
1.0
Watts
W/°C
Operating and Storage Temperature Range TJ, T
stg
–55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 50 Apk, L = 0.32 mH, RG = 25 Ω)
E
AS
400 mJ
Thermal Resistance — Junction to Case
— Junction to Ambient
R
θJC
R
θJA
1.0
62.5
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
L
260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics—are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
Order this document
by MTP50N06EL/D
SEMICONDUCTOR TECHNICAL DATA
TMOS POWER FET
50 AMPERES
60 VOLTS
R
DS(on)
= 0.028 OHM
Motorola Preferred Device
D
S
G
CASE 221A–06, Style 5
TO–220AB
Motorola, Inc. 1995
MTP50N06EL
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
60
—
—
64
—
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125°C)
I
DSS
—
—
—
—
10
100
µAdc
Gate–Body Leakage Current (VGS = ±15 Vdc, VDS = 0) I
GSS
— — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
V
GS(th)
2.0
—
—
7.0
4.0
—
Vdc
mV/°C
Static Drain–Source On–Resistance
(VGS = 5.0 Vdc, ID = 25 Adc)
(VGS = 5.0 Vdc, ID = 25 Adc)
R
DS(on)
—
—
0.018—0.028
0.39
Ohm
Drain–Source On–Voltage (VGS = 5.0 Vdc)
(ID = 50 Adc)
(ID = 25 Adc, TJ = 125°C)
V
DS(on)
—
—
0.7
—
1.68
1.4
Vdc
Forward Transconductance (VDS = 6.25 Vdc, ID = 20 Adc) g
FS
8.0 11 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 1643 4340 pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
C
oss
— 464 1491
Reverse Transfer Capacitance
f = 1.0 MHz)
C
rss
— 112 520
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
d(on)
— 28 42 ns
Rise Time
t
r
— 370 730
Turn–Off Delay Time
VGS = 5.0 Vdc,
RG = 9.1 Ω)
t
d(off)
— 94 110
Fall Time
G
= 9.1 Ω)
t
f
— 176 300
Q
T
— 50 73 nC
(See Figure 8)
DS
= 48 Vdc, ID = 50 Adc,
Q
1
— 10 —
(VDS = 48 Vdc, ID = 50 Adc,
VGS = 5.0 Vdc)
Q
2
— 30 —
Q
3
— 20 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1) (IS = 50 Adc, VGS = 0 Vdc)
(IS = 50 Adc, VGS = 0 Vdc, TJ = 125°C)
V
SD
—
—
3.15
1.016
—
—
Vdc
t
rr
— 76 —
(See Figure 14)
S
= 50 Adc, VGS = 0 Vdc,
t
a
— 48 —
(IS = 50 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
t
b
— 28 —
Reverse Recovery Stored Charge Q
RR
— 0.211 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
L
D
—
—
3.5
4.5
—
—
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
— 7.5 — nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
Gate Charge
Reverse Recovery Time
(VDD = 30 Vdc, ID = 50 Adc,
(V
(I
ns
MTP50N06EL
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
0 0.4 0.8 1.2 1.6
0
40
60
80
100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
I
D
, DRAIN CURRENT (AMPS)
2 2.5 3 3.5 4 4.5
I
D
, DRAIN CURRENT (AMPS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0 20 40 60 80 100
0.01
0.015
0.02
0.025
0.03
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
0 20 40 60 80 100
0.012
0.016
0.018
0.02
0.022
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
ID, DRAIN CURRENT (AMPS)
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
–50
0.6
0.7
1.3
1.4
1.6
0 10 20 30 40 60
1
10
100
1000
TJ, JUNCTION TEMPERATURE (
°
C)
Figure 5. On–Resistance Variation with
Temperature
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
I
DSS
, LEAKAGE (nA)
–25 0 25 50 75 100 125 150
TJ = 25
°C
VDS ≥ 10 V
TJ = 25
°C
VGS = 0 V
VGS = 5 V
VGS = 5 V
ID = 25 A
20
VGS = 10 V
8 V
5 V
4.5 V
4 V
3.5 V
3 V
0
40
60
80
100
20
TJ = –55°C
25°C
100°C
TJ = 100°C
25°C
–55°C
0.014
VGS = 5 V
10 V
0.8
0.9
1
1.1
1.2
1.5
50
TJ = 125°C
100°C
25°C
6 V
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