Motorola MTP4N50E Datasheet
1
Motorola TMOS Power MOSFET Transistor Device Data
N–Channel Enhancement–Mode Silicon Gate
This a dvanced h igh voltage TMOS E–FET is designed to
withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a drain–to–source diode
with fast recovery time. Designed for high voltage, high s peed
switching applications such a s power supplies, P WM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional s afety margin against
unexpected voltage transients.
• Avalanche Energy Capability Specified at Elevated
Temperature
• Low Stored Gate Charge for Efficient Switching
• Internal Source–to–Drain Diode Designed to Replace External
Zener Transient Suppressor — Absorbs High Energy in the
Avalanche Mode
• Source–to–Drain Diode Recovery Time Comparable to Discrete
Fast Recovery Diode
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–Source Voltage V
DSS
500 Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ) V
DGR
500 Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–repetitive
V
GS
V
GSM
±20
±40
Vdc
Vpk
Drain Current — Continuous
Drain Current — Pulsed
I
D
I
DM
4.0
10
Adc
Total Power Dissipation @ TC = 25°C
Derate above 25°C
P
D
75
0.6
Watts
W/°C
Operating and Storage Temperature Range TJ, T
stg
–55 to 150 °C
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (T
J
< 150°C)
Single Pulse Drain–to–Source Avalanche Energy — TJ = 25°C
Single Pulse Drain–to–Source Avalanche Energy — TJ = 100°C
Repetitive Pulse Drain–to–Source Avalanche Energy
W
DSR
(1)
W
DSR
(2)
280
44
7.4
mJ
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient°
R
θJC
R
θJA
1.67
62.5
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
L
260 °C
(1) VDD = 50 V, ID = 4.0 A
(2) Pulse Width and frequency is limited by TJ(max) and thermal response
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics— are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
Order this document
by MTP4N50E/D
SEMICONDUCTOR TECHNICAL DATA
TMOS POWER FET
4.0 AMPERES
500 VOLTS
R
DS(on)
= 1.5 OHMS
D
S
G
CASE 221A–06, Style 5
TO–220AB
Motorola Preferred Device
Motorola, Inc. 1996
MTP4N50E
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0, ID = 250 µAdc)
V
(BR)DSS
500 — — Vdc
Zero Gate Voltage Drain Current
(VDS = 500 V, VGS = 0)
(VDS = 400 V, VGS = 0, TJ = 125°C)
I
DSS
—
—
—
—
0.25
1.0
mAdc
Gate–Body Leakage Current, Forward (V
GSF
= 20 Vdc, VDS = 0) I
GSSF
— — 100 nAdc
Gate–Body Leakage Current, Reverse (V
GSR
= 20 Vdc, VDS = 0) I
GSSR
— — 100 nAdc
ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
(TJ = 125°C)
V
GS(th)
2.0
1.5
—
—
4.0
3.5
Vdc
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 2.0 A) R
DS(on)
— 1.3 1.5 Ohm
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 4.0 Adc)
(ID = 2.0 A, TJ = 100°C)
V
DS(on)
—
—
—
—
7.5
6.0
Vdc
Forward Transconductance (VDS = 15 Vdc, ID = 2.0 A) g
FS
1.5 — — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 775 — pF
Output Capacitance
(VDS = 25 V, VGS = 0,
f = 1.0 MHz)
C
oss
— 84 —
Transfer Capacitance
f = 1.0 MHz)
C
rss
— 19 —
SWITCHING CHARACTERISTICS*
Turn–On Delay Time
t
d(on)
— 24 — ns
Rise Time
≈ 4.0 A,
t
r
— 34 —
Turn–Off Delay Time
RG = 12 Ω, RL = 62 Ω,
V
GS(on)
= 10 V)
t
d(off)
— 60 —
Fall Time
GS(on)
= 10 V)
t
f
— 36 —
Total Gate Charge
Q
g
— 27 32 nC
Gate–Source Charge
(VDS = 400 V, ID = 4.0 A,
V
= 10 V)
Q
gs
— 3.5 —
Gate–Drain Charge
VGS = 10 V)
Q
gd
— 14 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
V
SD
— — 1.4 Vdc
Forward Turn–On Time
µs)
t
on
— ** —
Reverse Recovery Time t
rr
— — 760
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
L
d
—
—
3.5
4.5
—
—
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
s
— 7.5 —
*Indicates Pulse Test: Pulse Width = 300 µs Max, Duty Cycle ≤ 2.0%.
**Limited by circuit inductance.
(IS = 4.0 A, di/dt = 100 A/
(VDD = 250 V, ID
ns
nH
MTP4N50E
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
TJ, JUNCTION TEMPERATURE (°C)
Figure 2. Gate–To–Source Threshold Voltage
Variation With Temperature
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 3. Transfer Characteristics
TJ, JUNCTION TEMPERATURE (°C)
Figure 4. Breakdown Voltage Variation
With Temperature
ID, DRAIN CURRENT (AMPS)
Figure 5. On–Resistance versus Drain Current
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. On–Resistance Variation
With Temperature
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
I
D
, DRAIN CURRENT (AMPS)
V
GS(th)
, GATE THRESHOLD VOLTAGE (NORMALIZED)
V
BR(DSS)
, DRAIN–TO–SOURCE BREAKDOWN
VOLTAGE (NORMALIZED)
8
6
4
2
201612840
1.2
1.1
1
0.9
0.8
–50 –25 0 25 50 75 100 125 150
8
6
4
2
0
86420
1.2
1.1
1
0.9
0.8
–50 0 50 100 150
2.8
2.4
1.2
0
1086420
2.5
0
TJ = 25°C
7 V
6 V
5 V
VDS = V
GS
ID = 0.25 mA
TJ = 100°C
–55°C
25°C
VGS = 0
ID = 0.25 mA
TJ = 100°C
25°C
–55°C
VGS = 10 V
VGS = 10 V
ID = 2 A
I
D
, DRAIN CURRENT (AMPS)
VGS = 10 V
VDS ≥ 10 V
10
–50 0 50 100 200
4 V
0
200
0.8
0.4
2
1.5
1
0.5
150
8 V
2
1.6
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