Motorola MTP2N50E Datasheet
1
Motorola TMOS Power MOSFET Transistor Device Data
N–Channel Enhancement–Mode Silicon Gate
This high voltage MOSFET uses an advanced t ermination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I
DSS
and V
DS(on)
Specified at Elevated Temperature
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–Source Voltage V
DSS
500 Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ) V
DGR
500 Vdc
Gate–Source Voltage — Continuous
— Non–Repetitive (tp ≤ 10 ms)
V
GS
V
GSM
±20
±40
Vdc
Vpk
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (tp ≤ 10 µs)
I
D
I
D
I
DM
2.0
1.6
6.0
Adc
Apk
Total Power Dissipation
Derate above 25°C
P
D
75
0.6
Watts
W/°C
Operating and Storage Temperature Range TJ, T
stg
–55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, IL = 3.5 Apk, L = 10 mH, RG = 25 Ω)
E
AS
61 mJ
Thermal Resistance — Junction to Case
— Junction to Ambient
R
θJC
R
θJA
1.67
62.5
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
L
260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics— are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
Order this document
by MTP2N50E/D
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
TMOS POWER FET
2.0 AMPERES
500 VOLTS
R
DS(on)
= 3.6 OHM
Motorola Preferred Device
D
S
G
CASE 221A–06, Style 5
TO–220AB
MTP2N50E
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
500
—
—
689
—
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125°C)
I
DSS
—
—
—
—
10
100
µAdc
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0) I
GSS
— — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
V
GS(th)
2.0
—
3.0
7.1
4.0
—
Vdc
mV/°C
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 1.0 Adc) R
DS(on)
— 2.7 4.0 Ohm
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 2.0 Adc)
(ID = 1.0 Adc, TJ = 125°C)
V
DS(on)
—
—
5.9
—
9.6
8.4
Vdc
Forward Transconductance (VDS = 15 Vdc, ID = 1.0 Adc) g
FS
1.0 1.6 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 323 450 pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
C
oss
— 45 60
Reverse Transfer Capacitance
f = 1.0 MHz)
C
rss
— 9.0 20
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
d(on)
— 8.0 16 ns
Rise Time
t
r
— 6.0 12
Turn–Off Delay Time
VGS = 10 Vdc,
RG = 9.1 Ω)
t
d(off)
— 16 32
Fall Time
G
= 9.1 Ω)
t
f
— 10 20
Q
T
— 11 15 nC
(See Figure 8)
DS
= 400 Vdc, ID = 2.0 Adc,
Q
1
— 2.0 —
(VDS = 400 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)
Q
2
— 5.4 —
Q
3
— 5.1 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 2.0 Adc, VGS = 0 Vdc)
(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C)
V
SD
—
—
0.82
0.69
1.6
—
Vdc
t
rr
— 334 —
(See Figure 14)
S
= 2.0 Adc, VGS = 0 Vdc,
t
a
— 62 —
(IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
t
b
— 272 —
Reverse Recovery Stored Charge Q
RR
— 0.985 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
D
— 4.5 — nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
— 7.5 — nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
Gate Charge
Reverse Recovery Time
(VDD = 250 Vdc, ID = 2.0 Adc,
(V
(I
ns
MTP2N50E
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
, DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
0 2 4 6 8 20
0
1
2
3
4
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
I
D
, DRAIN CURRENT (AMPS)
2 3 4 5 6 7
0
1
2
3
4
I
D
, DRAIN CURRENT (AMPS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0 0.8 1.6 2.4 3.2 4
0
2
4
6
8
0 0.8 1.6 2.4 3.2 4
2.6
3
3.4
3.8
4.2
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
ID, DRAIN CURRENT (AMPS)
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
0.4
0.8
1.2
1.6
2
1
10
100
1000
TJ, JUNCTION TEMPERATURE (
°
C)
Figure 5. On–Resistance Variation with
Temperature
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
I
DSS
, LEAKAGE (nA)
TJ = 25°C VDS ≥ 10 V TJ = –55°C
25°C
100°C
TJ = 100°C
TJ = 25°C
VGS = 0 V
VGS = 10 V
VGS = 10 V
VGS = 10 V
ID = 2 A
10 12 14 16 18
6 V
5 V
3.5
2.5
1.5
0.5
2.5 3.5 4.5 5.5 6.5
1
3
5
7
3.62.821.20.4
25°C
–55°C
VGS = 10 V
15 V
–50 –25 0 25 50 75 100 125 150 0 10050 150 200 250 500300 350 400 450
TJ = 125°C
100°C
25°C
0.4 1.2 2 2.8 3.6
8 V
7 V
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
DS(on)
R
DS(on)
R
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