Motorola MTP12N10E Datasheet
1
Motorola TMOS Power MOSFET Transistor Device Data
N–Channel Enhancement–Mode Silicon Gate
This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in p ower supplies, converters and P WM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Designed to Eliminate the Need for External Zener Transient
Suppressor — Absorbs High Energy in the Avalanche Mode
• Commutating Safe Operating Area (CSOA) Specified for Use
in Half and Full Bridge Circuits
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I
DSS
and V
DS(on)
Specified at Elevated Temperature
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–Source Voltage V
DSS
100 Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ) V
DGR
100 Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Single Pulse (tp ≤ 50 µs)
V
GS
±20
±40
Vdc
Drain Current — Continuous
Drain Current — Single Pulse (tp ≤ 10 µs)
I
D
I
DM
12
30
Adc
Total Power Dissipation @ TC = 25°C
Derate above 25°C
P
D
79
0.53
Watts
W/°C
Operating and Storage Temperature Range TJ, T
stg
–55 to 175 °C
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (T
J
≤ 175°C)
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 V, VGS = 10 V, L = 4.03 mH, RG = 25 Ω, Peak IL = 12 A)
(See Figures 15, 16 and 17)
E
AS
290 mJ
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient°
R
θJC
R
θJA
1.9
62.5
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
L
260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics—are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
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by MTP12N10E/D
SEMICONDUCTOR TECHNICAL DATA
TMOS POWER FET
12 AMPERES
100 VOLTS
R
DS(on)
= 0.16 OHM
Motorola Preferred Device
D
S
G
CASE 221A–06, Style 5
TO–220AB
Motorola, Inc. 1996
MTP12N10E
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0, ID = 250 µAdc)
Temperature Coefficient (positive)
V
(BR)DSS
100
—
—
110
—
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 100 V, VGS = 0)°
(VDS = 100 V, VGS = 0, TJ = 150°C)
I
DSS
—
—
—
—
10
100
µA
Gate–Body Leakage Current, Forward (V
GSF
= 20 Vdc, VDS = 0) I
GSSF
— — 100 nAdc
Gate–Body Leakage Current, Reverse (V
GSR
= 20 Vdc, VDS = 0) I
GSSR
— — 100 nAdc
ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (negative)µ
V
GS(th)
2.0
—
3.0
6.0
4.0
—
Vdc
mV/°C
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 6.0 Adc) R
DS(on)
— 0.125 0.16 Ohm
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 12 Adc)
°
(ID = 6.0 Adc, TJ = 150°C)
V
DS(on)
—
—
1.5
1.4
2.4
1.92
Vdc
Forward Transconductance (VDS ≥ 15 V, ID = 6.0 A)
g
FS
4.0 5.0 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 600 — pF
Reverse Transfer Capacitance
(VDS = 25 V, VGS = 0,
f = 1.0 MHz)
C
rss
— 70 —
Output Capacitance
See Figure 14
C
oss
— 230 —
SWITCHING CHARACTERISTICS (TJ = 100°C)
Turn–On Delay Time
t
d(on)
— 10 — ns
Rise Time
t
r
— 64 —
Turn–Off Delay Time
VGS = 10 V, RG = 12 Ω)
See Figure 7
t
d(off)
— 21 —
Fall Time t
f
— 30 —
Gate Charge
Q
T
— 18 26 nC
Q
1
— 4.0 —
VGS = 10 Vdc)
See Figures 5 and 6
Q
2
— 10 —
Q
3
— 8.0 —
SOURCE–DRAIN DIODE CHARACTERISTICS*
Forward On–Voltage
S
= 12 A, VGS = 0)
V
SD
— 1.0 2.5 Vdc
(IS = 12 A, VGS = 0)
(IS = 12 A, VGS = 0, TJ = 150°C)
— 0.83 —
Reverse Recovery Time (IS = 12 A, VGS = 0,
dIS/dt = 100 A/µs, VR = 50 V)
t
rr
— 110 — ns
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)″
(Measured from the drain lead 0.25″ from package to center of die)
L
d
—
—
3.5
4.5
—
—
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
s
— 7.5 —
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.
(VDD = 50 V, ID = 12 A,
(VDS = 80 V, ID = 12 A,
(I
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