Motorola MTD6N10E Datasheet

1

Motorola TMOS Power MOSFET Transistor Device Data

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N–Channel Enhancement–Mode Silicon Gate

This advanced TMOS E–FET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in p ower supplies, c onverters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

• Avalanche Energy Specified

• Source–to–Drain Diode Recovery Time Comparable to a Discrete

Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

• I

DSS

and V

DS(on)

Specified at Elevated Temperature

• Surface Mount Package Available in 16 mm, 13–inch/2500

Unit Tape & Reel, Add T4 Suffix to Part Number

• Replaces MTD5N10

MAXIMUM RATINGS

(TC = 25°C unless otherwise noted)

Rating

Symbol Value Unit

Drain–Source Voltage V

DSS

100 Vdc

Drain–Gate Voltage (RGS = 1.0 MΩ) V

DGR

100 Vdc

Gate–Source Voltage — Continuous

Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)

V

GS

V

GSM

± 20
± 40

Vdc
Vpk

Drain Current — Continuous

Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)

I

D

I

D

I

DM

6.0

4.5
18

Adc

Apk

Total Power Dissipation

Derate above 25°C

Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size

P

D

40

0.32

1.75

Watts

W/°C

Watts

Operating and Storage Temperature Range TJ, T

stg

–55 to 150 °C

Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 3.0 mH, RG =25 Ω)

E

AS

50 mJ

Thermal Resistance — Junction to Case

Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted to minimum recommended pad size

R

θJC

R

θJA

R

θJA

3.13
100

71.4

°C/W

Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T

L

260 °C

Designer’s Data for “Worst Case” Conditions —The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves —representing boundaries on device characteristics —are given to facilitate “worst case” design.

E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

Order this document

by MTD6N10E/D



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995



TMOS POWER FET

6.0 AMPERES
100 VOLTS

R

DS(on)

= 0.400 OHM

Motorola Preferred Device



D

S

G

CASE 369A–13, Style 2

DPAK

MTD6N10E

2

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS

(T

J

= 25°C unless otherwise noted)

Characteristic

Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain–Source Breakdown Voltage

(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)

V

(BR)DSS

100

—

—

124

—
—

Vdc

mV/°C

Zero Gate Voltage Drain Current

(VDS = 100 Vdc, VGS = 0 Vdc)
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = 125°C)

I

DSS

—
—

—
—

10

100

µAdc

Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) I

GSS

— — 100 nAdc

ON CHARACTERISTICS (1)

Gate Threshold Voltage

(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)

V

GS(th)

2.0
—

3.2

4.0

4.0
—

Vdc

mV/°C

Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 3.0 Adc) R

DS(on)

— 0.29 0.4 Ohm

Drain–Source On–Voltage (VGS = 10 Vdc)

(ID = 6.0 Adc)
(ID = 3.0 Adc, TJ = 125°C)

V

DS(on)

—
—

1.75
—

2.9

2.5

Vdc

Forward Transconductance (VDS = 13 Vdc, ID = 3.0 Adc) g

FS

1.5 2.4 — mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

C

iss

— 310 420 pF

Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

C

oss

— 120 210

Reverse Transfer Capacitance

f = 1.0 MHz)

C

rss

— 25 50

SWITCHING CHARACTERISTICS (2)

Turn–On Delay Time

t

d(on)

— 8.0 15 ns

Rise Time

t

r

— 31 49

Turn–Off Delay Time

VGS = 10 Vdc,

RG = 9.1 Ω)

t

d(off)

— 13 31

Fall Time

G

= 9.1 Ω)

t

f

— 12 27

Q

T

— 10 14 nC

(See Figure 8)

DS

= 80 Vdc, ID = 6.0 Adc,

Q

1

— 3.3 —

(VDS = 80 Vdc, ID = 6.0 Adc,

VGS = 10 Vdc)

Q

2

— 4.3 —

Q

3

— 5.5 —

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage (1)

(IS = 6.0 Adc, VGS = 0 Vdc)

(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125°C)

V

SD

—
—

0.98

0.9

2.0
—

Vdc

t

rr

— 86.7 —

(See Figure 14)

S

= 6.0 Adc, VGS = 0 Vdc,

t

a

— 64 —

(IS = 6.0 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/µs)

t

b

— 22.7 —

Reverse Recovery Stored Charge Q

RR

— 0.327 — µC

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the drain lead 0.25″ from package to center of die)

L

D

— 4.5 — nH

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

L

S

— 7.5 — nH

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.

Gate Charge

Reverse Recovery Time

(VDD = 50 Vdc, ID = 6.0 Adc,

(V

(I

ns

MTD6N10E

3

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE (OHMS)

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE

(NORMALIZED)

R

DS(on)

, DRAIN–TO–SOURCE RESISTANCE (OHMS)

0 2 4 6 8

0

4

8

10

12

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics

I

D

, DRAIN CURRENT (AMPS)

2 4 6 8 10

0

4

8

12

I

D

, DRAIN CURRENT (AMPS)

VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

0 4 8 12 14

0.15

0.35

0.55

0.65

0 4 8 12 16

0.20

0.30

0.40

0.45

ID, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Drain Current

and Temperature

ID, DRAIN CURRENT (AMPS)

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

– 50

0.6

1.0

1.4

1.8

0 20 60 100 120

1

10

100

TJ, JUNCTION TEMPERATURE (

°

C)

Figure 5. On–Resistance Variation with

Temperature

VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 6. Drain–To–Source Leakage

Current versus Voltage

I

DSS

, LEAKAGE (nA)

– 25 0 25 50 75 100 125 150

VDS ≥ 10 V

100°C

25°C

TJ = –55°C

TJ = 100°C

25°C

–55°C

TJ = 25°C

VGS = 0 V

VGS = 10 V

VGS = 10 V

VGS = 10 V

VGS = 10 V
ID = 3 A

9 V

8 V

7 V

6 V

5 V

15 V

2

6

0.25

0.45

0.8

1.2

1.6

2

6

10

0.25

0.35

1 3 5 7 3 5 7 9

2 6 10 2 6 10 14

40 80

TJ = 125°C

100°C

25°C

TJ = 25°C