Motorola MTD20N06HDL Datasheet
1
Motorola TMOS Power MOSFET Transistor Device Data
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N–Channel Enhancement–Mode Silicon Gate
This advanced high–cell density HDTMOS E–FET is designed to
withstand high energy in the avalanche and commutation modes.
The new energy efficient design also offers a drain–to–source
diode w ith a f ast r ecovery t ime. Designed for l ow–voltage,
high–speed switching applications in power supplies, converters
and PWM motor controls, these devices are particularly well suited
for bridge circuits, and inductive l oads. The avalanche energy
capability is specified to eliminate the guesswork in designs where
inductive loads are switched, and to offer additional safety margin
against unexpected voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I
DSS
and V
DS(on)
Specified at Elevated Temperature
• Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
• Available in Insertion Mount, Add –1 or 1 to Part Number
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–Source Voltage V
DSS
60 Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ) V
DGR
60 Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
V
GS
V
GSM
± 15
± 20
Vdc
Vpk
Drain Current — Continuous @ 25°C
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
I
D
I
D
I
DM
20
12
60
Adc
Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TC = 25°C (1)
P
D
40
0.32
1.75
Watts
W/°C
Watts
Operating and Storage Temperature Range TJ, T
stg
–55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 20 Apk, L = 1.0 mH, RG = 25 Ω)
E
AS
200
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
R
θJC
R
θJA
R
θJA
3.13
100
71.4
°C/W
Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
L
260 °C
(1) When surface mounted to an FR–4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
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SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1996
D
S
G
TMOS POWER FET
LOGIC LEVEL
20 AMPERES
60 VOLTS
R
DS(on)
= 0.045 OHM
Motorola Preferred Device
CASE 369A–13, Style 2
DPAK
MTD20N06HDL
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TC = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
60
—
—
25
—
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125°C)
I
DSS
—
—
—
—
10
100
µAdc
Gate–Body Leakage Current (VGS = ±15 Vdc, VDS = 0) I
GSS
— — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
V
GS(th)
1.0
—
1.5
6.0
2.0
—
Vdc
mV/°C
Static Drain–Source On–Resistance
(VGS = 4.0 Vdc, ID = 10 Adc)
(VGS = 5.0 Vdc, ID = 10 Adc)
R
DS(on)
—
—
0.045
0.037
0.070
0.045
Ohm
Drain–Source On–Voltage (VGS = 5.0 Vdc)
(ID = 20 Adc)
(ID = 10 Adc, TJ = 125°C)
V
DS(on)
—
—
0.76
—
1.2
1.1
Vdc
Forward Transconductance (VDS = 4.0 Vdc, ID = 10 Adc) g
FS
6.0 12 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 863 1232 pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
C
oss
— 216 300
Reverse Transfer Capacitance
f = 1.0 MHz)
C
rss
— 53 73
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
d(on)
— 11 15 ns
Rise Time
t
r
— 151 190
Turn–Off Delay Time
VGS = 5.0 Vdc,
RG = 9.1 Ω)
t
d(off)
— 34 35
Fall Time
G
= 9.1 Ω)
t
f
— 75 98
Q
T
— 14.6 22 nC
DS
= 48 Vdc, ID = 20 Adc,
Q
1
— 3.25 —
(VDS = 48 Vdc, ID = 20 Adc,
VGS = 5.0 Vdc)
Q
2
— 7.75 —
Q
3
— 7.0 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 20 Adc, VGS = 0 Vdc)
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C)
V
SD
—
—
0.95
0.88
1.1
—
Vdc
t
rr
— 22 —
S
= 20 Adc,
t
a
— 12 —
(IS = 20 Adc,
dIS/dt = 100 A/µs)
t
b
— 34 —
Reverse Recovery Stored Charge Q
RR
— 0.049 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
D
— 4.5 —
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
— 7.5 —
nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
Gate Charge
Reverse Recovery Time
(VDS = 30 Vdc, ID = 20 Adc,
(V
(I
ns
MTD20N06HDL
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
TJ, JUNCTION TEMPERATURE (°C)
ID, DRAIN CURRENT (Amps) ID, DRAIN CURRENT (Amps)
VGS, GATE–TO–SOURCE VOLTAGE (Volts)
I
D
, DRAIN CURRENT (AMPS)
Figure 1. On–Region Characteristics
0
10
20
30
40
Figure 2. Transfer Characteristics
0 10 20 30 40
0
0.02
0.04
0.06
0.07
0.025
0.03
0.04
0.05
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
0.6
0.8
1.0
1.2
1.6
Figure 5. On–Resistance Variation with
Temperature
1.5 2 2.5 3 43.5 4.5
VDS ≥ 10 V
100°C
25°C
0.05
0.03
0.01
VGS = 5 V
– 55°C
25°C
0 10 20 30 40
0.045
0.035
– 50 – 25 0 25 50 75 100 125 150
1.4
TJ = – 55°C
TJ = 100°C
TJ = 25°C
VGS = 10 V
5 V
VGS = 5 V
ID = 10 A
0 0.4 0.8 1.2 1.6 2.0
0
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
I
D
, DRAIN CURRENT (AMPS)
20
10
TJ = 25°C
2.5 V
0.2 0.6
1.81.41.0
30
3 V
3.5 V
4 V
4.5 V
5 V
6 V
VGS = 10 V
40
8 V
Figure 6. Drain–to–Source Leakage
Current versus Voltage
I
DSS
, LEAKAGE (nA)
10
1000
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
100
0 10 3020
VGS = 0 V
TJ = 125°C
100°C
1
40 6050
25°C
MTD20N06HDL
4
Motorola TMOS Power MOSFET Transistor Device Data
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
G(AV)
) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, V
SGP
. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – V
GSP
)
tf = Q2 x RG/V
GSP
where
VGG = the gate drive voltage, which varies from zero to V
GG
RG = the gate drive resistance
and Q2 and V
GSP
are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= RG C
iss
In [VGG/(VGG – V
GSP
)]
t
d(off)
= RG C
iss
In (VGG/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating t
d(on)
and is read at a voltage corresponding to the
on–state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The M OSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 8) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (Volts)
C, CAPACITANCE (pF)
Figure 7. Capacitance Variation
10 0 10 15 20 25
3000
2000
1000
500
0
V
GS
V
DS
1500
5 5
2500
VDS = 0 V
C
iss
C
rss
VGS = 0 V
TJ = 25°C
C
iss
C
oss
C
rss
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