Motorola MTD20N03HDL Datasheet
1
Motorola TMOS Power MOSFET Transistor Device Data
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N–Channel Enhancement–Mode Silicon Gate
This advanced HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in p ower supplies, converters and PWM m otor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a Dis-
crete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I
DSS
and V
DS(on)
Specified at Elevated Temperature
• Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–Source Voltage V
DSS
30 Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ) V
DGR
30 Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
V
GS
V
GSM
±15
± 20
Vdc
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
I
D
I
D
I
DM
20
16
60
Adc
Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TC = 25°C, when mounted with the minimum recommended pad size
P
D
74
0.6
1.75
Watts
W/°C
Operating and Storage Temperature Range TJ, T
stg
–55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 Ω)
E
AS
200 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
R
θJC
R
θJA
R
θJA
1.67
100
71.4
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
L
260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s, E–FET, and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
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by MTD20N03HDL/D
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
TMOS POWER FET
LOGIC LEVEL
20 AMPERES
30 VOLTS
R
DS(on)
= 0.035 OHM
Motorola Preferred Device
D
S
G
CASE 369A–13, Style 2
DPAK
MTD20N03HDL
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (3)
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
30
—
—
43
—
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C)
I
DSS
—
—
—
—
10
100
µAdc
Gate–Body Leakage Current
(VGS = ±15 Vdc, VDS = 0 Vdc)
I
GSS
— — 100
nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage (Cpk ≥ 2.0) (3)
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
V
GS(th)
1.0
—
1.5
5.0
2.0
—
Vdc
mV/°C
Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (3)
(VGS = 4.0 Vdc, ID = 10 Adc)
(VGS = 5.0 Vdc, ID = 10 Adc)
R
DS(on)
— 0.034
0.030
0.040
0.035
Ohm
Drain–to–Source On–Voltage (VGS = 5.0 Vdc)
(ID = 20 Adc)
(ID = 10 Adc, TJ = 125°C)
V
DS(on)
—
—
0.55
—
0.8
0.7
Vdc
Forward Transconductance
(VDS = 5.0 Vdc, ID = 10 Adc)
g
FS
10 13 —
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 880 1260 pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
C
oss
— 300 420
Transfer Capacitance
f = 1.0 MHz)
C
rss
— 80 112
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
d(on)
— 13 15.8 ns
Rise Time
t
r
— 212 238
Turn–Off Delay Time
VGS = 5.0 Vdc,
RG = 9.1 Ω)
t
d(off)
— 37 30
Fall Time
G
= 9.1 Ω)
t
f
— 84 96
Q
T
— 13.4 18.9 nC
(See Figure 8)
DS
= 24 Vdc, ID = 20 Adc,
Q
1
— 3.0 —
(VDS = 24 Vdc, ID = 20 Adc,
VGS = 5.0 Vdc)
Q
2
— 7.3 —
Q
3
— 6.0 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(Cpk ≥ 2.0) (3)
(IS = 20 Adc, VGS = 0 Vdc)
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C)
V
SD
—
—
0.95
0.87
1.1
—
Vdc
t
rr
— 33 —
(See Figure 15)
S
= 20 Adc, VGS = 0 Vdc,
t
a
— 23 —
(IS = 20 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
t
b
— 10 —
Reverse Recovery Stored Charge Q
RR
— 33 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
D
— 4.5 —
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
— 7.5 —
nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values. Cpk = Absolute Value of Spec (Spec–AVG/3.516 µA).
Gate Charge
Reverse Recovery Time
(VDD = 15 Vdc, ID = 20 Adc,
(V
(I
ns
MTD20N03HDL
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
I
DSS
, LEAKAGE (nA)
VDS, DRAIN–TO–SOURCE VOLTAGE (Volts)TJ, JUNCTION TEMPERATURE (°C)
ID, DRAIN CURRENT (Amps) ID, DRAIN CURRENT (Amps)
VDS, DRAIN–TO–SOURCE VOLTAGE (Volts) VGS, GATE–TO–SOURCE VOLTAGE (Volts)
I
D
, DRAIN CURRENT (AMPS)
I
D
, DRAIN CURRENT (AMPS)
0 0.4 0.8 1.2 1.6 2.00.2 0.6 1.0 1.4 1.8
0
10
20
40
Figure 1. On–Region Characteristics
0
10
20
30
40
Figure 2. Transfer Characteristics
0 16 32 40
0.020
0.028
0.036
0.044
0.052
0.020
0.028
0.036
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
0.6
0.8
1.0
1.2
1.8
1
1000
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
30
VGS = 10 V
8 V
6 V
2.5 V
3 V
TJ = 25°C
4 V
1.0 1.8 2.6 3.4 4.64.2 5.0
VDS ≥ 10 V
100°C
25°C
VGS = 5 V
– 55°C
25°C
0 16 24 32 40
0.032
0.024
– 50 – 25 0 25 50 75 100 125 150
1.4
0 6 12 24 3018
VGS = 0 V
TJ = 125°C
TJ = – 55°C
TJ = 100°C
TJ = 25°C
VGS = 5 V
10 V
VGS = 5 V
ID = 10 A
1.4 2.2 3.0 3.8
100
10
100°C
25°C
3.5 V
4.5 V
5 V
1.6
8 24 8
MTD20N03HDL
4
Motorola TMOS Power MOSFET Transistor Device Data
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
G(AV)
) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, V
SGP
. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – V
GSP
)
tf = Q2 x RG/V
GSP
where
VGG = the gate drive voltage, which varies from zero to V
GG
RG = the gate drive resistance
and Q2 and V
GSP
are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= RG C
iss
In [VGG/(VGG – V
GSP
)]
t
d(off)
= RG C
iss
In (VGG/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating t
d(on)
and is read at a voltage corresponding to the
on–state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The M OSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (Volts)
C, CAPACITANCE (pF)
Figure 7. Capacitance Variation
10 0 10 15 20 25
2800
2000
1200
400
0
V
GS
V
DS
1600
800
5 5
2400
VDS = 0 V
C
iss
C
rss
VGS = 0 V
C
iss
C
oss
C
rss
TJ = 25°C
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