1
Motorola TMOS Power MOSFET Transistor Device Data
P–Channel Enhancement–Mode Silicon Gate
This a dvanced h igh voltage TMOS E–FET is designed to
withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a drain–to–source diode
with fast recovery time. Designed for high voltage, high s peed
switching applications such a s power supplies, P WM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional s afety margin against
unexpected voltage transients.
• Avalanche Energy Capability Specified at Elevated
Temperature
• Low Stored Gate Charge for Efficient Switching
• Internal Source–to–Drain Diode Designed to Replace External
Zener Transient Suppressor–Absorbs High Energy in the
Avalanche Mode
• Source–to–Drain Diode Recovery Time Comparable to Discrete
Fast Recovery Diode
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–to–Source Voltage V
DSS
500 Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
DGR
500 Vdc
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage — Single Pulse (tp ≤ 50 µs)
V
GS
V
GSM
±20
±40
Vdc
Drain Current — Continuous @ TC = 25°C
Drain Current — Continuous @ TC = 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
I
D
I
D
I
DM
1.0
0.8
4.0
Adc
Apk
Total Power Dissipation @ TC = 25°C
Derate above 25°C
Total Power Dissipation @ TC = 25°C, when mounted to minimum recommended pad size
P
D
50
0.4
1.75
Watts
W/°C
Watts
Operating and Storage Temperature Range TJ, T
stg
–55 to 150 °C
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (T
J
< 150°C)
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 3.0 Apk, L = 10 mH, RG = 25 Ω)
E
AS
45 mJ
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
R
θJC
R
θJA
R
θJA
2.5
100
71.4
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 5 seconds T
L
260 °C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
Order this document
by MTD1P50E/D
SEMICONDUCTOR TECHNICAL DATA
CASE 369A–13, Style 2
DPAK Surface Mount
TMOS POWER FET
1.0 AMPERES
500 VOLTS
15 Ω
Motorola Preferred Device
D
S
G
Motorola, Inc. 1996
MTD1P50E
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(T
C
= 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
500
—
—
TBD
—
—
Vdc
V/°C
Zero Gate Voltage Drain Current
(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125°C)
I
DSS
—
—
—
—
10
100
µAdc
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0) I
GSS
— — 100 nAdc
ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 0.25 mAdc)
Threshold Temperature Coefficient (Negative)
V
GS(th)
2.0
—
3.1
TBD
4.0
—
Vdc
mV/°C
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 0.5 Adc) R
DS(on)
— 12 15 Ohms
Drain–to–Source On–Voltage (VGS = 10 Vdc)
(ID = 1.0 Adc)
(ID = 0.5 Adc, TJ = 125°C)
V
DS(on)
—
—
—
—
18
15.8
Vdc
Forward Transconductance (VDS = 15 Vdc, ID = 0.5 Adc) g
FS
0.4 0.6 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— TBD TBD pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
C
oss
— TBD TBD
Transfer Capacitance
f = 1.0 MHz)
C
rss
— TBD TBD
SWITCHING CHARACTERISTICS*
Turn–On Delay Time
t
d(on)
— TBD TBD ns
Rise Time
t
r
— TBD TBD
Turn–Off Delay Time
VGS = 10 Vdc,
RG = 9.1 Ω)
t
d(off)
— TBD TBD
Fall Time
G
= 9.1 Ω)
t
f
— TBD TBD
Gate Charge
Q
T
— TBD TBD nC
DS
= 400 Vdc, ID = 1.0 Adc,
Q
1
— TBD —
(VDS = 400 Vdc, ID = 1.0 Adc,
VGS = 10 Vdc)
Q
2
— TBD —
Q
3
— TBD —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 1.0 Adc, VGS = 0 Vdc)
(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125°C)
V
SD
—
—
2.0
TBD
3.5
—
Vdc
t
rr
— TBD —
S
= 1.0 Adc,
t
a
— TBD —
(IS = 1.0 Adc,
dIS/dt = 100 A/µs)
t
b
— TBD —
Reverse Recovery Stored Charge Q
RR
— TBD — µC
*Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
Reverse Recovery Time
(VDS = 250 Vdc, ID = 1.0 Adc,
(V
(I
ns
MTD1P50E
3
Motorola TMOS Power MOSFET Transistor Device Data
PACKAGE DIMENSIONS
CASE 369A–13
ISSUE W
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
D
A
K
B
R
V
S
F
L
G
2 PL
M
0.13 (0.005) T
E
C
U
J
H
–T–
SEATING
PLANE
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.235 0.250 5.97 6.35
B 0.250 0.265 6.35 6.73
C 0.086 0.094 2.19 2.38
D 0.027 0.035 0.69 0.88
E 0.033 0.040 0.84 1.01
F 0.037 0.047 0.94 1.19
G 0.180 BSC 4.58 BSC
H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.102 0.114 2.60 2.89
L 0.090 BSC 2.29 BSC
R 0.175 0.215 4.45 5.46
S 0.020 0.050 0.51 1.27
U 0.020 ––– 0.51 –––
V 0.030 0.050 0.77 1.27
Z 0.138 ––– 3.51 –––
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
MTD1P50E
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Motorola TMOS Power MOSFET Transistor Device Data
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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MTD1P50E/D
*MTD1P50E/D*
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