Motorola MTD15N06VL Datasheet
SEMICONDUCTOR TECHNICAL DATA
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by MTD15N06VL/D
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resistance area product about one–half that of standard MOSFET s. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low R
DS(on)
Technology
• Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETS
• Avalanche Energy Specified
• I
DSS
and V
Specified at Elevated Temperature
DS(on)
• Static Parameters are the Same for both TMOS V and TMOS E–FET
• Surface Mount Package Available in 16 mm 13–inch/2500 Unit Tape & Reel,
Add T4 Suffix to Part Number
G
TMOS POWER FET
15 AMPERES
60 VOLTS
R
TM
D
CASE 369A–13, Style 2
DPAK Surface Mount
S
DS(on)
= 0.085 OHM
MAXIMUM RATINGS
Drain–to–Source Voltage V
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage — Non–repetitive (tp ≤ 10 ms)
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ 25°C
Operating and Storage Temperature Range TJ, T
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 1.0 mH, RG = 25 Ω)
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves —representing boundaries on device characteristics —are given to facilitate “worst case” design.
E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
(TC = 25°C unless otherwise noted)
Rating
(1)
(1)
Symbol Value Unit
60 Vdc
60 Vdc
± 15
± 25
15
12
53
60
0.4
2.1
–55 to 175 °C
113 mJ
2.5
100
71.4
260 °C
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C/W
V
V
I
E
R
R
R
DSS
DGR
GS
GSM
I
D
I
D
DM
P
D
stg
AS
θJC
θJA
θJA
L
REV 2
Motorola TMOS Power MOSFET Transistor Device Data
Motorola, Inc. 1997
1
MTD15N06VL
)
f = 1.0 MHz)
V
G
)
(
DS
,
D
,
(
S
,
GS
,
ELECTRICAL CHARACTERISTICS
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (3)
(VGS = 0 Vdc, ID = 0.25 mAdc)
T emperature Coef ficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
Gate–Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) I
ON CHARACTERISTICS (1)
Gate Threshold Voltage (Cpk ≥ 2.0) (3)
(VDS = VGS, ID = 250 µAdc)
T emperature Coef ficient (Negative)
Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (3)
(VGS = 5.0 Vdc, ID = 7.5 Adc)
Drain–to–Source On–Voltage
(VGS = 5.0 Vdc, ID = 15 Adc)
(VGS = 5.0 Vdc, ID = 7.5 Adc, TJ = 150°C)
Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc) g
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
Reverse Recovery Time
Reverse Recovery Stored Charge Q
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Cpk =
(T
= 25°C unless otherwise noted)
J
Characteristic
(VDS = 25 Vdc, VGS = 0 Vdc,
(IS = 15 Adc, VGS = 0 Vdc, TJ = 150°C)
Max limit – Typ
3 x SIGMA
f = 1.0 MHz
(VDD = 30 Vdc, ID = 15 Adc,
(VDS = 48 Vdc, ID = 15 Adc,
(IS = 15 Adc, VGS = 0 Vdc)
(IS = 15 Adc, VGS = 0 Vdc,
= 5.0 Vdc,
GS
RG = 9.1 Ω)
VGS = 5.0 Vdc)
dIS/dt = 100 A/µs)
Symbol Min Typ Max Unit
V
(BR)DSS
I
DSS
GSS
V
GS(th)
R
DS(on)
V
DS(on)
FS
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
V
SD
t
rr
t
a
t
b
RR
L
D
L
S
60
—
—
—
— — 100 nAdc
1.0
—
— 0.075 0.085
—
—
8.0 10 — mhos
— 570 880 pF
— 180 380
— 45 110
— 11 50 ns
— 150 210
— 27 160
— 70 140
— 12 20 nC
— 3.0 —
— 7.0 —
— 11 —
—
—
— 63 —
— 42 —
— 21 —
— 0.140 — µC
—
—
— 7.5 —
—
68
—
—
1.5
4.0
—
—
0.96
0.85
3.5
4.5
—
—
10
100
2.0
—
1.5
1.3
1.6
—
—
—
mV/°C
mV/°C
Vdc
µAdc
Vdc
Ohm
Vdc
Vdc
ns
nH
nH
2
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
MTD15N06VL
50
TJ = 25
45
40
35
30
25
20
15
, DRAIN CURRENT (AMPS)
D
I
10
5
0
°C
024 6810
13 579
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)
VGS = 10V
9 V
8 V
7 V
6 V
5 V
Figure 1. On–Region Characteristics
VGS = 5 V
0.14
TJ = 100
0.12
0.1
0.08
0.06
0.04
, DRAIN–TO–SOURCE RESIST ANCE (OHMS)
0.02
DS(on)
0
R
01020305
°C
25
°C
–55
°C
15 25
ID, DRAIN CURRENT (AMPS)
35
50
VDS ≥ 5 V
45
40
35
30
25
20
15
, DRAIN CURRENT (AMPS)
D
I
10
5
0
10
VGS, GATE–T O–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0.16
TJ = 25
0.14
0.12
0.1
0.08
0.06
0.04
, DRAIN–TO–SOURCE RESIST ANCE (OHMS)
0.02
DS(on)
0
R
01020304035
°C
VGS = 5 V
10 V
5
15 25
ID, DRAIN CURRENT (AMPS)
TJ = –55
°C
100
567
25
°C
°C
9234 8
45 50
Figure 3. On–Resistance versus Drain Current
and T emperature
2.0
VGS = 5 V
1.8
ID = 7.5 A
1.6
1.4
1.2
1
(NORMALIZED)
0.8
, DRAIN–TO–SOURCE RESIST ANCE
0.6
0.4
DS(on)
R
0.2
–50
–25 0 25 50 75 100 150
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance Variation with
Temperature
125
175
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
100
VGS = 0 V
TJ = 125°C
10
, LEAKAGE (nA)
DSS
I
0
010203040
5
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)
100°C
15 25 45
35
Figure 6. Drain–T o–Source Leakage
Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
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