Motorola MTD1302 Datasheet

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SEMICONDUCTOR TECHNICAL DATA

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N–Channel Enhancement Mode Silicon Gate

This advanced HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters, and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.

• Avalanche Energy Specified

• Source–to–Drain Diode Recovery Time Comparable to a

Discrete Fast Recovery Diode

• Diode Is Characterized for Use In Bridge Circuits

• I

DSS

and V

Specified at Elevated Temperature

DS(on)

• Surface Mount Package Available in 16 mm, 13″ / 2500 Unit

Tape & Reel, Add “T4” Suffix to Part Number

MAXIMUM RATINGS

Drain–to–Source Voltage V
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
Gate–to–Source Voltage — Continuous

Drain Current — Continuous

Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)

Total Power Dissipation

Derate above 25°C

Total Power Dissipation @ TC = 25°C
Operating and Storage Temperature Range TJ, T
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C

(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 20 Apk, L = 1.0 mH, RG = 25 Ω)

Thermal Resistance

Junction to Case
Junction–to–Ambient
Junction–to–Ambient

Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 5.0 seconds T

(1) When surface mounted to an FR4 board using the minimum recommended pad size.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

HDTMOS is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.

(TC = 25°C unless otherwise noted)

Rating

— Non–Repetitive (tp ≤ 10 ms)

(1)

(1)



Symbol Value Unit

DSS

DGR

V

V

GSM

I
I

I

DM
P

E

R

θJC

R

θJA

R

θJA

TMOS POWER FET

20 AMPERES

30 VOLTS

R

DS(on)

CASE 369A–13, Style 2

GS

D
D

D

stg

AS

L

= 0.022 OHM

30 Vdc
30 Vdc

± 20
± 20

20
16
60

74

0.592

1.75

– 55 to 150 °C

200 mJ

1.67
100

71.4
260 °C

Vdc
Vpk

Adc

Apk

Watts

W/°C

Watts

°C/W

 Motorola, Inc. 1997

Motorola TMOS Power MOSFET Transistor Device Data

1

MTD1302

)

f = 1.0 MHz)

V

10 Vd

G

)

(

DS

,

D

,

(

DS

,

D

,

(

S

,

GS

,

ELECTRICAL CHARACTERISTICS

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage

(VGS = 0 Vdc, ID = 0.25 mAdc)

Zero Gate Voltage Drain Current

(VDS = 30 Vdc, VGS = 0 Vdc)
(VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C)

Gate–Body Leakage Current

(VGS = ± 20 Vdc, VDS = 0 Vdc)

ON CHARACTERISTICS

Gate Threshold Voltage

(VDS = VGS, ID = 250 µAdc)

Static Drain–to–Source On–Resistance

(VGS = 10 Vdc, ID = 10 Adc)
(VGS = 4.5 Vdc, ID = 5.0 Adc)

Drain–to–Source On–Voltage

(VGS = 10 Vdc, ID = 20 Adc)
(VGS = 10 Vdc, ID = 10 Adc, TJ = 150°C)

Forward Transconductance

(VDS = 10 Vdc, ID = 10 Adc)

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance
Transfer Capacitance

SWITCHING CHARACTERISTICS

Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge

Gate Charge

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage

Reverse Recovery Time

Reverse Recovery Stored Charge Q

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.

(1)

(TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

(VDS = 25 Vdc, VGS = 0 Vdc,

(2)

(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C)

f = 1.0 MHz

(VDD = 15 Vdc, ID = 20 Adc,

GS

RG = 9.1 Ω)

(VDS = 24 Vdc, ID = 20 Adc,

VGS = 5.0 Vdc)

(VDS = 24 Vdc, ID = 20 Adc,

VGS = 10 Vdc)

(IS = 20 Adc, VGS = 0 Vdc)

(IS = 20 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/µs)

=

c,

V

(BR)DSS

I

DSS

I

GSS

V

GS(th)

R

DS(on)

V

DS(on)

g

FS

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

t

f

Q
Q
Q
Q
Q
Q
Q
Q

V

SD

t

rr

t

a

t

b

RR

30 — —

—
—

— — 100

1.0 1.5 2.0

—
—

—
—

10 16 —

— 755 1162 pF
— 370 518
— 102 204

— 7.2 15
— 52 104
— 45 90
— 73 146

T
1
2
3
T
1
2
3

— 14.5 21.8
— 2.2 —
— 8.8 —
— 6.8 —
— 27 40.5
— 2.2 —
— 10 —
— 7.2 —

—
—

— 38 —
— 19 —
— 20 —
— 36 — µC

—
—

0.019

0.026

0.38
—

0.83

0.79

10

100

0.022

0.029

0.5

0.33

1.1
—

Vdc

µAdc

nAdc

Vdc

Ohms

Vdc

Mhos

ns

nC

nC

Vdc

ns

2

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

MTD1302

40
35
30
25
20
15

, DRAIN CURRENT (AMPS)R

10

D

I

5.0
0

0.4 0.8 1.2

0.2 0.6 1.81.6 2.01.4
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

5.0 V10 V

4.0 V

TJ = 25°C

VGS = 3.0 V

1.00

30

25

20

15

10

, DRAIN CURRENT (AMPS)

D

I

5.0

0

VDS ≥ 10 V

TJ = 125°C

1.5 2.0 5.0
VGS, GATE–T O–SOURCE VOLTAGE (VOLTS)

2.51.0

–55°C

25°C

4.0

4.53.0 3.5

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

0.03
VGS = 10 V

TJ = 100°C

0.04

0.035

0.03

0.025

TJ = 25°C

VGS = 4.5 V

0.02

, DRAIN–TO–SOURCE ON–RESISTANCE (OHMS)

0.01

10 20 30

DS(on)

15 25 35

ID, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus

Drain Current and Temperature

3.0
ID = 10 A

2.0

VGS = 10 V

1.0

25°C

–55°C

, DRAIN–TO–SOURCE ON–RESISTANCE (OHMS)

40

R

, LEAKAGE (nA)
I

0.02

0.015

0.01

0.005
0

DS(on)

1000

100

10

DSS

1.0

10 V

15 20 30

ID, DRAIN CURRENT (AMPS)

25 35

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

TJ = 125°C

100°C

25°C

4010

, DRAIN–TO–SOURCE RESIST ANCE (NORMALIZED)R

0

DS(on)

–25–50

0

TJ, JUNCTION TEMPERATURE (

5025 10 3015

75 100 150125

°

C)

Figure 5. On–Resistance Variation with

T emperature

Motorola TMOS Power MOSFET Transistor Device Data

0.1

5.0 20
VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

Figure 6. Drain–T o–Source Leakage

Current versus Voltage

25

3

MTD1302

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter­mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat­ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I

) can be made from a rudimentary analysis of

G(A V)

the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a resis­tive load, VGS remains virtually constant at a level known as
the plateau voltage, V

. Therefore, rise and fall times may

SGP

be approximated by the following:
tr = Q2 x RG/(VGG – V
tf = Q2 x RG/V

GSP

GSP

)

where
VGG = the gate drive voltage, which varies from zero to V

GG

RG = the gate drive resistance
and Q2 and V

are read from the gate charge curve.

GSP

During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val­ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

t

d(off)

= RG C

= RG C

In [VGG/(VGG – V

iss

In (VGG/V

iss

GSP

)]

GSP

)

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off–state condition when cal­culating t
on–state when calculating t

and is read at a voltage corresponding to the

d(on)

d(off)

.

At high switching speeds, parasitic circuit elements com­plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func­tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea­sure and, consequently , is not specified.

The resistive switching time variation versus gate resis­tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op­erated into an inductive load; however, snubbing reduces
switching losses.

2500

C

iss

2000

1500

C

rss

1000

C, CAPACITANCE (pF)

500

V

GS

VGS = 0 V

V

DS

0

VDS = 0 V

–5.0 5.0

–10 0 10 15 20

GATE–T O–SOURCE OR DRAIN–TO–SOURCE VOLT AGE (VOLTS)

Figure 7. Capacitance Variation

C

C

C

iss

oss

rss

25

4

Motorola TMOS Power MOSFET Transistor Device Data