Motorola MTB8N50E Datasheet

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SEMICONDUCTOR TECHNICAL DATA

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N–Channel Enhancement–Mode Silicon Gate

The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower R
MOSFET uses an advanced termination scheme to provide
enhanced voltage–blocking capability without degrading perfor­mance over time. In addition, this advanced TMOS E–FET is
designed to withstand high energy in the avalanche and commuta­tion modes. This new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters, PWM motor controls, these devices are particularly well
suited for bridge circuits where diode speed and commutating safe
operating areas are critical and offer additional safety margin
against unexpected voltage transients.

• Robust High Voltage Termination

• Avalanche Energy Specified

• Source–to–Drain Diode Recovery Time Comparable

to a Discrete Fast Recovery Diode

• Diode is Characterized for Use in Bridge Circuits

• I

DSS

and V

Specified at Elevated Temperature

DS(on)

• Short Heatsink Tab Manufactured – Not Sheared

• Specifically Designed Leadframe for Maximum Power Dissipation

• Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number

MAXIMUM RATINGS

Drain–to–Source Voltage V
Drain–to–Gate Voltage (RGS = 1.0 MW)
Gate–to–Source Voltage – Continuous

Gate–to–Source Voltage – Non–repetitive (tp ≤ 10 ms)

Drain Current — Continuous @ TC = 25°C

Drain Current — Continuous @ TC = 100°C
Drain Current — Single Pulse (tp ≤ 10 ms)

Total Power Dissipation @ TC = 25°C

Derate above 25°C
Operating and Storage Temperature Range TJ, T
Single Pulse Drain–to–Source Avalanche Energy – STAR TING TJ = 25°C

(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 8.0 Apk, L = 16 mH, RG = 25 W)
Thermal Resistance

– Junction–to–Case

– Junction–to–Ambient

– Junction–to–Ambient
Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 5 sec. T

(1) When surface mounted to an FR4 board using the minimum recommended pad size.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

REV 1

(TJ = 25°C unless otherwise noted)

(1)

capabilities. This high voltage

DS(on)

Rating



D

G

S

Symbol Value Unit

DSS

V

DGR

V

GS

V

GSM

I

D

I

D

I

DM
P

D

stg

E

AS

R

q

JC

R

q

JA

R

q

JA
L

TMOS POWER FET

8.0 AMPERES
500 VOL TS

R

CASE 418B–02, Style 2

–55 to 150 °C

= 0.8 OHM

DS(on)

D2PAK

500 Vdc
500 Vdc

±20
±40

8.0

5.0
32

125

1.0

510 mJ

1.0

62.5
50

260 °C

Vdc
Vpk

Adc

Apk

Watts

W/°C

°C/W

Motorola TMOS Power MOSFET Transistor Device Data

 Motorola, Inc. 1996

1

MTB8N50E

)

f = 1.0 MHz)

(R

W

)

(

DS

,

D

,

(

S

,

GS

,

ELECTRICAL CHARACTERISTICS

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage

(VGS = 0 Vdc, ID = 250 µAdc)
T emperature Coef ficient (Positive)

Zero Gate Voltage Drain Current

(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 400 Vdc, VGS = 0 Vdc, TJ = 125°C)

Gate–Body Leakage Current

(VGS = ±20 Vdc, VDS = 0 Vdc)

ON CHARACTERISTICS

Gate Threshold Voltage

(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)

Static Drain–to–Source On–Resistance

(VGS = 10 Vdc, ID = 4.0 Adc)

Drain–to–Source On–Voltage (VGS = 10 Vdc)

(ID = 8.0 Adc)
(ID = 4.0 Adc, TJ = 125°C)

Forward Transconductance

(VDS = 15 Vdc, ID = 4.0 Adc)

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance

Transfer Capacitance

SWITCHING CHARACTERISTICS

Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time t
Gate Charge

(see Figure 8)

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage
(IS = 8.0 Adc, VGS = 0 Vdc) — 1.2 2.0
(IS = 8.0 Adc, VGS = 0 Vdc, TJ = 125°C) — 1.1 —
Reverse Recovery Time

Reverse Recovery Stored Charge Q

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the drain lead 0.25″ from package to center of die)

Internal Source Inductance

(Measured from the source lead 0.25″ from package to source bond pad)

(1) Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2.0%.
(2) Switching characteristics are independent of operating junction temperature.

(1)

(T

C

Characteristic

(VDS = 25 Vdc, VGS = 0 Vdc,

(2)

(VDS = 400 Vdc, ID = 8.0 Adc,

(IS = 8.0 Adc, VGS = 0 Vdc,

= 25°C unless otherwise noted)

f = 1.0 MHz

= 9.1

Gon

VGS = 10 Vdc)

dIS/dt = 100 A/ms)

Symbol Min Typ Max Unit

V

(BR)DSS

I

DSS

I

GSS

V

GS(th)

R

DS(on)

V

DS(on)

g

FS

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

f

Q

T

Q

1

Q

2

Q

3

V

SD

t

rr

t

a

t

b

RR

L

D

L

S

500

—

—
—

— — 100

2.0
—

— 0.6 0.8

—
—

4.0 — —

— 1450 1680 pF
— 190 264
— 45.4 144

— 15 50 ns
— 33 72
— 40 150
— 32 60
— 40 64 nC
— 8.0 —
— 17 —
— 17.3 —

— 320 — ns
— 179 —
— 141 —
— 3.0 —

— 4.5 —

— 7.5 —

—

500

—
—

3.0

6.3

—
—

—
—

10

100

4.0
—

7.2

6.4

Vdc

mV/°C

m

Adc

nAdc

Vdc

mV/°C

Ohms

Vdc

mhos

Vdc

m

C

nH

2

Motorola TMOS Power MOSFET Transistor Device Data