Motorola MTB75N05HD Datasheet
1
Motorola TMOS Power MOSFET Transistor Device Data
$ #
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N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower R
DS(on)
capabilities. This advanced
high–cell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in p ower supplies, converters and PWM m otor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I
DSS
and V
DS(on)
Specified at Elevated Temperature
• Short Heatsink Tab Manufactured — Not Sheared
• Specially Designed Leadframe for Maximum Power Dissipation
• Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain–to–Source Voltage V
DSS
50
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
DGR
50
Gate–to–Source Voltage — Continuous V
GS
± 20
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
I
D
I
D
I
DM
75
65
225
Amps
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C (minimum footprint, FR–4 board)
P
D
125
1.0
2.5
Watts
W/°C
Watts
Operating and Storage Temperature Range TJ, T
stg
– 55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 V, VGS = 10 V, Peak IL = 75 A, L = 0.177 mH, RG = 25 Ω)
E
AS
500 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (minimum footprint, FR–4 board)
R
θJC
R
θJA
R
θJA
1.0
62.5
50
°C/W
Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
L
260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics—are given to facilitate “worst case” design.
Designer’s, E–FET and HDTMOS are trademarks of Motorola Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
Order this document
by MTB75N05HD/D
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
D
S
G
TMOS POWER FET
75 AMPERES
50 VOLTS
R
DS(on)
= 9.5 mΩ
Motorola Preferred Device
CASE 418B–02, Style 2
D2PAK
REV 2
Volts
MTB75N05HD
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2)
(2)
(VGS = 0, ID = 250 µAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
50
—
—
54.9
—
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 50 V, VGS = 0)
(VDS = 50 V, VGS = 0, TJ = 125°C)
I
DSS
—
—
—
—
10
100
µAdc
Gate–Body Leakage Current
(VGS = ± 20 Vdc, VDS = 0)
I
GSS
— — 100
nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage (Cpk ≥ 1.5)
(2)
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
V
GS(th)
2.0
—
—
6.3
4.0
—
Vdc
mV/°C
Static Drain–to–Source On–Resistance
(3)
(Cpk ≥ 3.0)
(2)
(VGS = 10 Vdc, ID = 20 Adc)
R
DS(on)
— 7.0 9.5
mΩ
Drain–to–Source On–Voltage (VGS = 10 Vdc)
(3)
(ID = 75 A)
(ID = 20 Adc, TJ = 125°C)
V
DS(on)
—
—
0.63
—
—
0.34
Vdc
Forward Transconductance (VDS = 10 Vdc, ID = 20 Adc) g
FS
15 — — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(2)
C
iss
— 2600 2900 pF
Output Capacitance
(VDS = 25 V, VGS = 0, (Cpk ≥ 2.0)
(2)
f = 1.0 MHz) (Cpk ≥ 2.0)
(2)
C
oss
— 1000 1100
Transfer Capacitance
pk
≥ 2.0)
(2)
(Cpk ≥ 2.0)
(2)
C
rss
— 230 275
SWITCHING CHARACTERISTICS (4)
Turn–On Delay Time
t
d(on)
— 15 30 ns
Rise Time
t
r
— 170 340
Turn–Off Delay Time
VGS = 10 V,
RG = 9.1 Ω)
t
d(off)
— 70 140
Fall Time
G
= 9.1 Ω)
t
f
— 100 200
Gate Charge
Q
T
— 71 100 nC
DS
= 40 V, ID = 75 A,
Q
1
— 13 —
(VDS = 40 V, ID = 75 A,
VGS = 10 V)
Q
2
— 33 —
Q
3
— 26 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (IS = 75 A, VGS = 0) (Cpk ≥ 10)
(2)
(IS = 20 A, VGS = 0)
(IS = 20 A, VGS = 0, TJ = 125°C)
V
SD
—
—
0.97
0.80
0.68
—
1.00
—
Vdc
t
rr
— 57 —
S
= 37.5 A, VGS = 0,
t
a
— 40 —
(IS = 37.5 A, VGS = 0,
dIS/dt = 100 A/µs)
t
b
— 17 —
Reverse Recovery Stored Charge Q
RR
— 0.17 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from drain lead 0.25″ from package to center of die)
L
D
—
—
3.5
4.5
—
—
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
— 7.5 —
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Reflects Typical Values. Cpk = ABSOLUTE VALUE OF (SPEC – AVG) / 3 * SIGMA).
(3) For accurate measurements, good Kelvin contact required.
(4) Switching characteristics are independent of operating junction temperature.
Reverse Recovery Time
(VDD = 25 V, ID = 75 A,
(V
(I
ns
nH
MTB75N05HD
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
(1)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
I
DSS
, LEAKAGE (nA)
0
160
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
I
D
, DRAIN CURRENT (AMPS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
5 V
TJ = 25°C
100
60
20
0
1 2 3 4 5
160
I
D
, DRAIN CURRENT (AMPS)
120
80
40
20
0
0 1 2 3 5 8
0.014
0.012
0.01
0.006
0.004
0
ID, DRAIN CURRENT (AMPS)
20
TJ = 100°C
25°C
– 55°C
VGS = 10 V
0.009
0.008
0.005
0
ID, DRAIN CURRENT (AMPS)
20 40 60 80 100 120
TJ = 25°C
2
1.5
1
0.5
0
– 50
TJ, JUNCTION TEMPERATURE (
°
C)
– 25 0 25 50 75 100 125 150
VGS = 10 V
ID = 37.5 A
1000
100
0
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
0 15 30 40 50
25°C
100°C
VGS = 10 V
TJ = – 55°C
25°C
100°C
0.008
0.002
0.007
0.006
140 160
10000
10
40
80
120
140
1.5 2.5 3.5 4.50.5
140
100
60
64 7
40 60 80 100 120 140
5 10 20 25 35 45
TJ = 125°C
7 V
6 V
(1)
Pulse Tests: Pulse Width ≤ 250 µs, Duty Cycle ≤ 2%.
VDS ≥ 10 V
15 V
VGS = 10 V
VGS = 0 V
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