Motorola MTB75N03HDL Datasheet
1
Motorola TMOS Power MOSFET Transistor Device Data
"#& %!
! $! $#
N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower R
DS(on)
capabilities. This advanced
high–cell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in p ower supplies, converters and PWM m otor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I
DSS
and V
DS(on)
Specified at Elevated Temperature
• Ultra Low R
DS(on)
, High–Cell Density, HDTMOS
• Short Heatsink Tab Manufactured — Not sheared
• Specially Designed Leadframe for Maximum Power Dissipation
• Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–to–Source Voltage V
DSS
25 Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
DGR
25 Vdc
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
V
GS
V
GSM
± 15
± 20
Vdc
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
I
D
I
D
I
DM
75
59
225
Adc
Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
P
D
125
1.0
2.5
Watts
W/°C
Watts
Operating and Storage Temperature Range – 55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 75 Apk, L = 0.1 mH, RG = 25 Ω)
E
AS
280 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
R
θJC
R
θJA
R
θJA
1.0
62.5
50
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
L
260 °C
(1) When mounted with the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET and HDTMOS are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2
Order this document
by MTB75N03HDL/D
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
D
S
G
TMOS POWER FET
LOGIC LEVEL
75 AMPERES
25 VOLTS
R
DS(on)
= 9 mOHM
Motorola Preferred Device
CASE 418B–02, Style 2
D2PAK
MTB75N03HDL
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage (Cpk ≥ 2.0) (3)
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
25 — —
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 25 Vdc, VGS = 0 Vdc)
(VDS = 25 Vdc, VGS = 0 Vdc, TJ = 125°C)
I
DSS
—
—
—
—
100
500
µAdc
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 V) I
GSS
— — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage (Cpk ≥ 3.0) (3)
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
V
GS(th)
1.0 1.5 2.0
Vdc
mV/°C
Static Drain–Source On–Resistance (Cpk ≥ 2.0) (3)
(VGS = 5.0 Vdc, ID = 37.5 Adc)
R
DS(on)
— 6.0 9.0
mΩ
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 75 Adc)
(ID = 37.5 Adc, TJ = 125°C)
V
DS(on)
—
—
—
—
0.68
0.6
Vdc
Forward Transconductance (VDS = 3 Vdc, ID = 20 Adc) g
FS
15 55 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 4025 5635 pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
C
oss
— 1353 1894
Reverse Transfer Capacitance
f = 1.0 MHz)
C
rss
— 307 430
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
d(on)
— 24 48 ns
Rise Time
t
r
— 493 986
Turn–Off Delay Time
VGS = 5.0 Vdc,
RG = 4.7 Ω)
t
d(off)
— 60 120
Fall Time
G
= 4.7 Ω)
t
f
— 149 300
Gate Charge
Q
T
— 61 122 nC
DS
= 24 Vdc, ID = 75 Adc,
Q
1
— 14 28
(VDS = 24 Vdc, ID = 75 Adc,
VGS = 5.0 Vdc)
Q
2
— 33 66
Q
3
— 27 54
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 75 Adc, VGS = 0 Vdc)
(IS = 75 Adc, VGS = 0 Vdc, TJ = 125°C)
V
SD
—
—
0.97
0.87
1.1
—
Vdc
t
rr
— 58 —
S
= 75 Adc,
t
a
— 27 —
(IS = 75 Adc,
dIS/dt = 100 A/µs)
t
b
— 30 —
Reverse Recovery Stored Charge Q
RR
— 0.088 — µC
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Cpk =
Max limit – Typ
3 x SIGMA
Reverse Recovery Time
(VDS= 15 Vdc, ID = 75 Adc,
(V
(I
ns
MTB75N03HDL
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–to–Source Leakage
Current versus Voltage
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
I
D
, DRAIN CURRENT (AMPS)
I
D
, DRAIN CURRENT (AMPS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)
TJ, JUNCTION TEMPERATURE (
°
C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
I
DSS
, LEAKAGE (nA)
TJ = 25
°C
VDS ≥ 10 V
TJ = 100
°C
25
°C
–55
°C
TJ = 25
°C
VGS = 0 V
VGS = 10 V
VGS = 5 V
VGS = 5 V
VGS = 10 V
ID = 37.5 A
0.4 0.8 1.2 1.6 20 0.2 0.6 1 1.4 1.8
30
60
90
120
150
0
2 2.5 3.5 4 4.51.5
30
60
90
120
150
0
3
30 60 90 120 1500
0.01
0.002
0.008
0.006
0.004
25 50 100 125 1500
0.005
0.006
0.007
0.008
0.009
0.004
75
25 100 150–50 –25 0 50 75 125
0.4
0.8
1.2
1.6
2
0
10 20 300 5 15 25
10
100
1000
10000
1
10 V
100°C
25°C
TJ = 125°C
100°C
25°C
TJ = –55
°C
3.5 V
3 V
4 V
2.5 V
4.5 V
5 V
8 V
6 V
MTB75N03HDL
4
Motorola TMOS Power MOSFET Transistor Device Data
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
G(AV)
) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, V
SGP
. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – V
GSP
)
tf = Q2 x RG/V
GSP
where
VGG = the gate drive voltage, which varies from zero to V
GG
RG = the gate drive resistance
and Q2 and V
GSP
are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= RG C
iss
In [VGG/(VGG – V
GSP
)]
t
d(off)
= RG C
iss
In (VGG/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating t
d(on)
and is read at a voltage corresponding to the
on–state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The M OSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
Figure 7. Capacitance Variation
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
V
GS
V
DS
TJ = 25
°C
VDS = 0 V VGS = 0 V
15000
12000
9000
6000
3000
0
20 2510 150 510 5
C
rss
C
iss
C
oss
C
rss
C
iss
Loading...