Motorola MPC9140SD Datasheet
SEMICONDUCTOR TECHNICAL DATA
1
REV 0.2
Motorola, Inc. 1997
6/97
The MPC9140 is a 1:18 LVCMOS fanout buffer targeted to support
Intel based Pentium II microprocessor chip sets. The device features
18 low skew outputs optimized to drive the clock inputs of standard
unbuffered SDRAM modules. Standard unbuffered SDRAM modules
require four clocks per module allowing for the device to drive up to four
modules. The output buffers have been optimized to drive the load
presented by the SDRAM module.
The MPC9140 provides output shut off capabilities via an I2C serial
port for applications which plan to use fewer than four modules and desire
to minimize the power dissipation of the chip. Every output clock can be
individually enabled/disabled through fields in the I2C control registers.
After power up the default state is all outputs enabled. In applications
where this default state is acceptable the I2C ports need not be exercised.
• Supports Intel Pentium and Pentium II Processor Architectures
• 18 Skew Controlled 3.3V Compatible SDRAM Clocks
• I
2
C Serial Bus Interface
• Extensive Output Enable Control Capability
• Space Efficient 48–Lead SSOP Package
• Operating Temperature Range of 0°C to 70°C
• 3.3V ± 5% Power Supply
481
NCNC
472
NCNC
463
VDDVDD
454
SDRAM15SDRAM0
445
SDRAM14SDRAM1
436
VSSVSS
427
VDDVDD
418
SDRAM13SDRAM2
409
SDRAM12SDRAM3
3910
VSSVSS
3811
OEBUF_IN
3712
VDDVDD2
3613
SDRAM11SDRAM4
3514
SDRAM10SDRAM5
3415
VSS
VSS
3316
VDDVDD
3217
SDRAM9SDRAM6
3118
SDRAM8SDRAM7
3019
VSSVSS
2920
VDDVDD
2821
SDRAM17SDRAM16
2722
VSSVSS
2623
VSS
VDD
2524
SCLOCKSDATA
Figure 1. 48–Lead Pinout (Top View)
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
1:18 LVCMOS
FANOUT BUFFER
SD SUFFIX
48–LEAD PLASTIC SSOP PACKAGE
CASE 1215–01
FUNCTION TABLE
OE V1, V2
0
1
High–Z
1x BUF_IN
MPC9140
MOTOROLA TIMING SOLUTIONS
BR1333 — REV 5
2
Figure 2. Block Diagram
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4:13
SDRAM14
SDRAM15
SDRAM16
SDRAM17
CONFIG
REGISTERS
I2C
INTERFACE
SDATA
SCLOCK
OE
18
10
10
10
BUF_IN
Table 1. Pin Descriptions
Pin Name I/O Function
BUF_IN I 3.3V CMOS clock input
SDRAM0:17 O 3.3V CMOS SDRAM clock outputs
SDATA I/O Serial data for configuration control
SCLK I Serial clock input for configuration control. The state of the SDATA input is clocked into the device on
the rising edge of this clock
OE I A Low forces all outputs into High–Z state
VDD – 3.3V power supply connection
VSS – Ground connection which should be connected directly to the ground plane
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