Motorola MPC9120SD Datasheet
SEMICONDUCTOR TECHNICAL DATA
1
REV 0.2
Motorola, Inc. 1997
12/97
The MPC9120 is a 1:10 LVCMOS fanout buffer targeted to support
Intel based Pentium II microprocessor chip sets. The device features
10 low skew outputs optimized to drive the clock inputs of standard
unbuffered SO–DIMM SDRAM modules. Standard unbuffered SO–DIMM
SDRAM modules require two clocks per module allowing for the device to
drive up to four modules. The output buffers have been optimized to drive
the load presented by the SDRAM module.
The MPC9120 provides output shut off capabilities via an I2C serial
port for applications which plan to use fewer than four modules and desire
to minimize the power dissipation of the chip. Every output clock can be
individually enabled/disabled through fields in the I2C control registers.
After power up the default state is all outputs enabled. In applications
where this default state is acceptable the I2C ports need not be exercised.
• Supports Intel Pentium and Pentium II Processor Architectures
• 10 Skew Controlled 3.3V Compatible SDRAM Clocks
• I
2
C Serial Bus Interface
• Extensive Output Enable Control Capability
• Space Efficient 28–Lead SSOP Package
• Operating Temperature Range of 0°C to 70°C
• 3.3V ± 5% Power Supply
Figure 1. 28–Lead Pinout (Top View)
1
VDD
28
VDD
2
SDRAM0
27
SDRAM9
3
SDRAM1
26
SDRAM8
4
VSSO
25
VSS
5
VDD
24
VDD
6
SDRAM2
23
SDRAM7
7
SDRAM3
22
SDRAM6
8
VSS
21
VSS
9
BUF_IN
20
OE
10
VDD
19
VDD
11
SDRAM4
18
SDRAM5
12
VSS
17
VSS
13
VDDIIC
16
VSSIIC
14
SDATA
15
SCLOCK
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
1:10 LVCMOS
FANOUT BUFFER
SD SUFFIX
28–LEAD PLASTIC SSOP PACKAGE
CASE 940E–02
FUNCTION TABLE
OE V1, V2
0
1
High–Z
1x BUF_IN
MPC9120
MOTOROLA TIMING SOLUTIONS
BR1333 — REV 5
2
Figure 2. Block Diagram
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
CONFIG
REGISTERS
I2C
INTERFACE
SDATA
SCLOCK
OE
10
BUF_IN
SDRAM4
Table 1. Pin Descriptions
Pin Name I/O Function
BUF_IN I 3.3V CMOS clock input
SDRAM0:9 O 3.3V CMOS SDRAM clock outputs
SDATA I/O Serial data for configuration control
SCLK I Serial clock input for configuration control. The state of the SDATA input is clocked into the device on
the rising edge of this clock
OE I A Low forces all outputs into High–Z state
VDD – 3.3V power supply connection
VSS – Ground connection which should be connected directly to the ground plane
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