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Advance Information
MPC866EC/D
Rev. 1.4, 8/2003
MPC866/859
Hardware Specifications
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This document contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for the MPC866/859 family (refer to Table 1 for
a list of devices). The MPC866P is the superset device of the MPC866/859 family.
This document describes pertinent electrical and physical characteristics of the MPC8245. For
functional characteristics of the processor, refer to the
Manual
This document contains the following topics:
(MPC866UM/D).
Topic Page
MPC866 PowerQUICC Family Users
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Section 1, “Overview” 1
Section 2, “Features” 2
Section 3, “Maximum Tolerated Ratings” 7
Section 4, “Thermal Characteristics” 9
Section 5, “Power Dissipation” 10
Section 6, “DC Characteristics” 10
Section 7, “Thermal Calculation and Measurement” 11
Section 8, “Power Supply and Power Sequencing” 14
Section 9, “Layout Practices” 15
Section 10, “Bus Signal Timing” 15
Section 11, “IEEE 1149.1 Electrical Specifications” 44
Section 12, “CPM Electrical Characteristics” 46
Section 13, “UTOPIA AC Electrical Specifications” 70
Section 14, “FEC Electrical Characteristics” 72
Section 15, “Mechanical Data and Ordering Information” 75
Section 16, “Document Revision History” 88
1 Overview
The MPC866/859 is a derivative of Motorola’s MPC860 PowerQUICC™ family of devices.
It is a versatile single-chip integrated microprocessor and peripheral combination that can be
used in a variety of controller applications and communications and networking systems. The
MPC866/859/859DSL provides enhanced ATM functionality over that of other ATM-enabled
members of the MPC860 family.
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1
Features Features
Table 1 shows the functionality supported by the members of the MPC866/859 family.
Part
MPC866P 16 Kbytes 8 Kbytes Up to 4 1 4 2
MPC866T 4 Kbytes 4 Kbytes Up to 4 1 4 2
MPC859P 16 Kbytes 8 Kbytes 1112
MPC859T 4 Kbytes 4 Kbytes 1112
MPC859DSL 4 Kbytes 4 Kbytes 1 1 1
MPC852T
1
On the MPC859DSL, the SCC (SCC1) is for ethernet only. Also, the MPC859DSL does not support the Time Slot
Assigner (TSA).
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2
On the MPC859DSL, the SMC (SMC1) is for UART only.
3
For more details on the MPC852T, please refer to the MPC852T Hardware Specifications.
3
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Instruction Data 10T 10/100
4 KBytes 4 Kbytes 2121
Table 1. MPC866 Family Functionality
Cache Ethernet
SCC SMC
2
1
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2 Features
The following list summarizes the key MPC866/859 features:
• Embedded single-issue, 32-bit PowerPC™ core (implementing the PowerPC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1)
– 16-Kbyte instruction cache (MPC866P and MPC859P) is four-way , set-associativ e with 256
sets; 4-Kbyte instruction cache (MPC866T, MPC859T, and MPC859DSL) is two-way,
set-associative with 128 sets.
– 8-Kbyte data cache (MPC866P and MPC859P) is two-way, set-associative with 256 sets;
4-Kbyte data cache(MPC866T, MPC859T, and MPC859DSL) is two-way, set-associative
with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces and 16 protection groups.
— Advanced on-chip-emulation debug mode
• The MPC866/859 provides enhanced ATM functionality over that of the MPC860SAR. The
MPC866/859 adds major new features available in 'enhanced SAR' (ESAR) mode, including the
following:
— Improved operation, administration, and maintenance (OAM) support
— OAM performance monitoring (PM) support
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MPC866/859 Hardware Specifications
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— Multiple APC priority levels available to support a range of traffic pace requirements
— ATM port-to-port switching capability without the need for RAM-based microcode
— Simultaneous MII (10/100Base-T) and UTOPIA (half-duplex) capability
— Optional statistical cell counters per PHY
— UTOPIA level 2 compliant interface with added FIFO buffering to reduce the total cell
transmission time. (The earlier UTOPIA level 1 specification is also supported.)
– Multi-PHY support on the MPC866, MPC859P, and MPC859T
– Four PHY support on the MPC866/859
— Parameter RAM for both SPI and I
— Supports full-duplex UTOPIA both master (ATM side) and slave (PHY side) operation using a
'split' bus
— AAL2/VBR functionality is ROM-resident.
• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
• Thirty-two address lines
• Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS
— Up to 30 wait states programmable per memory bank
— Glueless interface to page mode/EDO/SDRAM, SRAM, EPROMs, flash EPROMs, and other
memory devices.
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbytes–256 Mbytes)
— Selectable write protection
— On-chip bus arbitration logic
• General-purpose timers
— Four 16-bit timers cascadable to be two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
• Fast Ethernet controller (FEC)
— Simultaneous MII (10/100Base-T) and UTOPIA operation when using the UTOPIA
multiplexed bus
• System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Low-power stop mode
— Clock synthesizer
— Decrementer and time base from the PowerPC architecture
— Reset controller
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lines, four WE lines, and one OE line
2
C can be relocated without RAM-based microcode
to support a DRAM bank
Features
MOTOROLA
MPC866/859 Hardware Specifications
3
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Features Features
• Interrupts
• Communications processor module (CPM)
• Four baud rate generators
• MPC866P and MPC866T have four SCCs (serial communication controller); MPC859P,
• Two SMCs (serial management channels) (MPC859DSL has one SMC (SMC1) for UART.)
— IEEE 1149.1 test access port (JTAG)
— Seven external interrupt request (IRQ) lines
— Twelve port pins with interrupt capability
— The MPC866P and MPC866T have 23 internal interrupt sources; the MPC859P, MPC859T,
— Programmable priority between SCCs (MPC866P and MPC866T)
— Programmable highest priority request
— RISC controller
— Communication-specific commands (for example,
— Supports continuous mode transmission and reception on all serial channels
— Up to 8-Kbytes of dual-port RAM
— MPC866P and MPC866T have 16 serial DMA (SDMA) channels; MPC859P, MPC859T , and
— Three parallel I/O registers with open-drain capability
— Independent (can be connected to any SCC or SMC)
— Allow changes during operation
— Autobaud support option
MPC859T, and MPC859DSL have one SCC; and SCC1 on MPC859DSL supports Ethernet only.
— Serial ATM capability on all SCCs
— Optional UTOPIA port on SCC4
— Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC)
— UART
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division multiplexed (TDM) channels
and MPC859DSL have 20 internal interrupt sources.
MODE
, and
MPC859DSL have 10 serial DMA (SDMA) channels.
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RESTART
TRANSMIT
GRACEFUL
)
STOP
TRANSMIT
,
ENTER
HUNT
4
MPC866/859 Hardware Specifications
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• One serial peripheral interface (SPI)
— Supports master and slave modes
— Supports multiple-master operation on the same bus
• One inter-integrated circuit (I
— Supports master and slave modes
— Multiple-master environment support
• Time slot assigner (TSA) (MPC859DSL does not have TSA.)
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame synchronization, and clocking
— Allows dynamic changes
— On MPC866P and MPC866T , can be internally connected to six serial channels (four SCCs and
two SMCs); on MPC859P and MPC859T, can be connected to three serial channels (one SCC
and two SMCs).
• Parallel interface port (PIP)
— Centronics interface support
— Supports fast connection between compatible ports on MPC866/859 or MC68360
• PCMCIA interface
— Master (socket) interface, compliant with PCI Local Bus Specification (Rev 2.1)
— Supports one or two PCMCIA sockets whether ESAR functionality is enabled
— Eight memory or I/O windows supported
• Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data.
— Supports conditions: =
— Each watchpoint can generate a breakpoint internally
• Normal high and normal low power modes to conserve power
• 1.8 V core and 3.3 V I/O operation with 5-V TTL compatibility; refer to Table 6 for a listing of the
5-V tolerant pins.
• 357-pin plastic ball grid array (PBGA) package
• Operation up to 133 MHz
≠
2
< >
Features
C) port
The MPC866/859 is comprised of three modules that each use a 32-bit internal bus: MPC8xx core, system
integration unit (SIU), and communication processor module (CPM). The MPC866P block diagram is
shown in Figure 1 on page 6. The MPC859P/859T/859DSL block diagram is sho wn in Figure 2 on page 7.
MOTOROLA
MPC866/859 Hardware Specifications
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Features Features
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Instruction
Bus
Embedded
MPC8xx
Processor
Core
Fast Ethernet
Controller
DMAs
FIFOs
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10/100
Base-T
Media Access
Control
MII
Load/Store
Bus
Parallel Interface Port
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16-Kbyte
Instruction Cache
Instruction MMU
32-Entry ITLB
8-Kbyte
Data Cache
Data MMU
32-Entry DTLB
Parallel I/O
4 Baud Rate
Generators
and UTOPIA
SCC1
Figure 1. MPC866P Block Diagram
4
Timers
Timers
SCC3
Time Slot Assigner
Time Slot Assigner
Unified
Bus
Interrupt
Controllers
32-Bit RISC Controller
and Program
ROM
SCC4
Serial Interface
System Interface Unit (SIU)
Internal
Bus Interface
PCMCIA/ATA Interface
8-Kbyte
Dual-Port RAM
Memory Controller
External
Unit
System Functions
Bus Interface
Unit
16 Virtual
Serial
and
2
Independent
DMA
Channels
I2CSPISMC2SMC1SCC2
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6
MPC866/859 Hardware Specifications
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Embedded
MPC8xx
Processor
Core
Fast Ethernet
Controller
DMAs
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Instruction
Bus
Load/Store
Bus
†
4-Kbyte
Instruction Cache
Instruction MMU
32-Entry ITLB
†
4-Kbyte
Data Cache
Data MMU
32-Entry DTLB
Unified
Bus
Maximum Tolerated Ratings
System Interface Unit (SIU)
Memory Controller
Internal
Bus Interface
Unit
System Functions
PCMCIA/ATA Interface
External
Bus Interface
Unit
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FIFOs
10/100
Base-T
Media Access
Control
MII
†
The MPC859P has a 16-Kbyte instruction cache and a 8-Kbyte data cache.
* The MPC859DSL does not contain SMC2 nor the time slot assigner, and provides eight SDMA
controllers.
Parallel I/O
4 Baud Rate
Generators
Parallel Interface Port
and UTOPIA
SCC1
Figure 2. MPC859P/859T/MPC859DSL Block Diagram
4
Timers
Timers
Time Slot Assigner*
Interrupt
Controllers
32-Bit RISC Controller
and Program
Time Slot Assigner
Dual-Port RAM
ROM
Serial Interface
8-Kbyte
10 Virtual
Serial
and
2
Independent
DMA
Channels
I2CSPISMC2*SMC1
3 Maximum T olerated Ratings
This section provides the maximum tolerated voltage and temperature ranges for the MPC866/859. Table 2
shows the maximum tolerated ratings, and Table 3 shows the operating temperatures.
Supply voltage
MOTOROLA
Table 2. Maximum Tolerated Ratings
Rating Symbol Value Unit
1
VDDH – 0.3 to 4.0 V
VDDL – 0.3 to 2.0 V
VDDSYN – 0.3 to 2.0 V
Difference between VDDL to VDDSYN 100 mV
MPC866/859 Hardware Specifications
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Maximum Tolerated Ratings Maximum Tolerated Ratings
Table 2. Maximum Tolerated Ratings (continued)
Rating Symbol Value Unit
Input voltage
Storage temperature range T
1
The power supply of the device must start its ramp from 0.0 V.
2
Functional operating conditions are provided with the DC electrical specifications in Table 6. Absolute maximum
ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may
affect device reliability or cause permanent damage to the device. See page 14.
Caution
power-up and normal operation (that is, if the MPC866/859 is unpowered, a voltage greater than 2.5 V must not be
applied to its inputs).
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Temperature
Temperature (extended) T
1
Minimum temperatures are guaranteed as ambient temperature, T
junction temperature, T
2
: All inputs that tolerate 5 V cannot be more than 2.5 V greater than VDDH. This restriction applies to
Rating Symbol Value Unit
1
(standard)
V
.
j
This device contains circuitry protecting against damage due to high-static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for example, either GND or V
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in
stg
Table 3. Operating Temperatures
T
A(min)
T
j(max)
A(min)
T
j(max)
. Maximum temperatures are guaranteed as
A
GND – 0.3 to VDDH V
–55 to +150 ˚C
0˚C
95 ˚C
–40 ˚C
100 ˚C
).
DD
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8
MPC866/859 Hardware Specifications
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θ
θ
θ
θ
θ
θ
Thermal Characteristics
4 Thermal Characteristics
Table 4 shows the thermal characteristics for the MPC866/859.
Table 4. MPC866/859 Thermal Resistance Data
Rating Environment Symbol Value Unit
R
R
JMA
JMA
JMA
Ψ
Ψ
JA
JT
JT
JB
JC
2
3
3
3
37 °C/W
23
30
19
13
6
2
2
Junction-to-ambient
Junction-to-board
Junction-to-case
Junction-to-package top
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1
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal
resistance.
2
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
3
Per JEDEC JESD51-6 with the board horizontal.
4
Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
5
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate
method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed
pad packages where the pad would be expected to be soldered, junction-to-case thermal resistance is a simulated
value from the junction to the exposed pad without contact resistance.
6
Thermal characterization parameter indicating the temperature difference between package top and junction
temperature per JEDEC JESD51-2.
1
4
5
6
Natural Convection Single-layer board (1s) R
Four-layer board (2s2p) R
Airflow (200 ft/min) Single-layer board (1s) R
Four-layer board (2s2p) R
Natural Convection
Airflow (200 ft/min)
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Power Dissipation Power Dissipation
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5 Power Dissipation
T able 5 shows po wer dissipation information. The modes are 1:1, where CPU and b us speeds are equal, and
2:1 mode, where CPU frequency is twice the bus speed.
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Table 5. Power Dissipation (P
Die Revision Bus Mode
0 1:1 50 MHz 110 140 mW
2:1 66 MHz 140 160 mW
1
Typical power dissipation at VDDL and VDDSYN is at 1.8 V. and VDDH is at 3.3 V.
2
Maximum power dissipation at VDDL and VDDSYN is at 1.9 V, and VDDH is at 3.465 V.
CPU
Frequency
66 MHz 150 180 mW
80 MHz 170 200 mW
100 MHz 210 250 mW
133 MHz 260 320 mW
)
D
Typical
1
Maximum
2
Unit
NOTE
Values in Table 5 represent VDDL based power dissipation and
do not include I/O power dissipation over VDDH. I/O power
dissipation varies widely by application due to buffer current,
depending on external circuitry. The VDDSYN power
dissipation is negligible.
6 DC Characteristics
Table 6 shows the DC electrical characteristics for the MPC866/859.
Table 6. DC Electrical Specifications
Characteristic Symbol Min Max Unit
Operating voltage VDDL (core) 1.7 1.9 V
VDDH (I/O) 3.135 3.465 V
VDDSYN
Difference between
VDDL to VDDSYN
1
1.7 1.9 V
— 100 mV
Input high voltage (all inputs except EXTAL and
EXTCLK)
10
2
MPC866/859 Hardware Specifications
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VIH 2.0 3.465 V
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Thermal Calculation and Measurement
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Table 6. DC Electrical Specifications (continued)
Characteristic Symbol Min Max Unit
Input low voltage VIL GND 0.8 V
EXTAL, EXTCLK input high voltage VIHC 0.7*(VDDH) VDDH V
Input leakage current, Vin = 5.5V (except TMS, TRST,
DSCK and DSDI pins) for 5 Volts Tolerant Pins
Input leakage current, Vin = VDDH (except TMS, TRST
DSCK, and DSDI)
Input leakage current, Vin = 0 V (except TMS, TRST
DSCK and DSDI pins)
Input capacitance
Output high voltage, IOH = – 2.0 mA,
except XTAL, and Open drain pins
Output low voltage
• IOL = 2.0 mA (CLKOUT)
• IOL = 3.2 mA
• IOL = 5.3 mA
• IOL = 7.0 mA (TXD1/PA14, TXD2/PA12)
• IOL = 8.9 mA (TS
1
The difference between VDDL and VDDSYN can not be more than 100 m V.
2
The signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], TDI, TDO, TCK, TRST_B, TMS, MII_TXEN, MII_MDIO are 5 V
tolerant.
3
Input capacitance is periodically sampled.
4
A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IP_B(0:1)/IWP(0:1)/VFLS(0:1),
IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3,
RXD1 /PA15, RXD2/PA13, L1TXDB/PA11, L1RXDB/PA10, L1TXDA/PA9, L1RXDA/PA8,
TIN1/L1RCLKA/BRGO1/CLK1/PA7, BRGCLK1/T
T
OUT2/CLK4/PA4, TIN3/BRGO3/CLK5/PA3, BRGCLK2/L1RCLKB/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/PA1,
L1TCLKB/T
BRGO1/I2CSDA/PB27, BRGO2/I2CSCL/PB26, SMTXD1/PB25, SMRXD1/PB24, SMSYN1
SMSYN2
L1ST2/R
L1ST1/R
TGA
TE1/CD1/PC10, CTS2/PC9, TGATE2/CD2/PC8, CTS3/SDACK2/L1TSYNCB/PC7, CD3/L1RSYNCB/PC6,
CTS4
/SDACK1/L1TSYNCA/PC5, CD4/L1RSYNCA/PC4, PD15/L1TSYNCA, PD14/L1RSYNCA, PD13/L1TSYNCB,
PD12/L1RSYNCB, PD11/RXD3, PD10/TXD3, PD9/RXD4, PD8/TXD4, PD5/REJECT2, PD6/R
PD4/REJECT3, PD3, MII_MDC, MII_TX_ER, MII_EN, MII_MDIO, MII_TXD[0:3].
5
BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6)/CE(1)_B, CS(7)/CE(2)_B, WE0/BS_B0/IORD,
WE1
/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1,
GPL_A
(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A,
ALE_B/DSCK/AT1, OP(0:1), OP2/MODCK1/STS
3
4
5
, TA, TEA, BI, BB, HRESET, SRESET)
OUT4/CLK8/PA0, REJCT1/SPISEL/PB31, SPICLK/PB30, SPIMOSI/PB29, BRGO4/SPIMISO/PB28,
/SDACK2/PB22, SMTXD2/L1CLKOB/PB21, SMRXD2/L1CLKOA/PB20, L1ST1/RTS1/PB19,
TS2/PB18, L1ST3/L1RQB/PB17, L1ST4/L1RQA/PB16, BRGO3/PB15, RSTRT1/PB14,
TS1/DREQ0/PC15, L1ST2/RTS2/DREQ1/PC14, L1ST3/L1RQB/PC13, L1ST4/L1RQA/PC12, CTS1/PC11,
2
OUT1/CLK2/PA6, TIN2/L1TCLKA/BRGO2/CLK3/PA5,
, OP3/MODCK2/DSDO, BADDR(28:30).
I
in
,
I
In
,
I
In
C
in
VOH 2.4 — V
VOL — 0.5 V
— 100 µA
—10µA
—10µA
—20pF
/SDACK1/PB23,
TS4, PD7/RTS3,
7 Thermal Calculation and Measurement
For the following discussions, PD = (VDDL x IDDL) + PI/O, where PI/O is the power dissipation of the I/O
drivers. The VDDSYN power dissipation is negligible.
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Thermal Calculation and Measurement Thermal Calculation and Measurement
7.1 Estimation with Junction-to-Ambient Thermal
Resistance
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
= TA +(R
T
J
where:
T
= ambient temperature (ºC)
A
R
θJA
P
= power dissipation in package
D
The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy
estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated
that errors of a factor of two (in the quantity TJ-TA) are possible.
x PD)
θJA
= package junction-to-ambient thermal resistance (ºC/W)
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7.2 Estimation with Junction-to-Case Thermal Resistance
Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal
resistance and a case-to-ambient thermal resistance:
= R
R
θJA
where:
R
R
R
is device related and cannot be influenced by the user. The user adjusts the thermal environment to
R
θJC
affect the case-to-ambient thermal resistance, R
the device, add a heat sink, change the mounting arrangement on the printed-circuit board, or change the
thermal dissipation on the printed-circuit board surrounding the device. This thermal model is most useful
for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink
to the ambient environment. For most packages, a better model is required.
+ R
θJC
= junction-to-ambient thermal resistance (ºC/W)
θJA
= junction-to-case thermal resistance (ºC/W)
θJC
= case-to-ambient thermal resistance (ºC/W)
θCA
θCA
. For instance, the user can change the airflow around
θCA
7.3 Estimation with Junction-to-Board Thermal Resistance
A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor
model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case
covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the
top of the package. The junction-to-board thermal resistance describes the thermal performance when most
of the heat is conducted to the printed-circuit board. It has been observed that the thermal performance of
most plastic packages and especially PBGA packages is strongly dependent on the board temperature; see
Figure 3.
12 MPC866/859 Hardware Specifications MOTOROLA
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100
90
80
70
60
50
40
30
20
10
Junction Temperature Rise Above
Ambient Divided by Package Power
0
0 2040 6080
nc...
I
Figure 3. Effect of Board Temperature Rise on Thermal Behavior
Board Temperture Rise Above Ambient Divided by Package
Thermal Calculation and Measurement
Power
cale Semiconductor,
Frees
If the board temperature is known, an estimate of the junction temperature in the en vironment can be made
using the following equation:
= TB +(R
T
J
where:
R
T
P
If the board temperature is known and the heat loss from the package case to the air can be ignored,
acceptable predictions of junction temperature can be made. For this method to work, the board and board
mounting must be similar to the test board used to determine the junction-to-board thermal resistance,
namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground
plane.
x PD)
θJB
= junction-to-board thermal resistance (ºC/W)
θJB
= board temperature ºC
B
= power dissipation in package
D
7.4 Estimation Using Simulation
When the board temperature is not known, a thermal simulation of the application is needed. The simple
two-resistor model can be used with the thermal simulation of the application [2], or a more accurate and
complex model of the package can be used in the thermal simulation.
MOTOROLA MPC866/859 Hardware Specifications 13
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Power Supply and Power Sequencing Power Supply and Power Sequencing
7.5 Experimental Determination
To determine the junction temperature of the device in the application after prototypes are available, the
thermal characterization parameter (Ψ
measurement of the temperature at the top center of the package case using the following equation:
= TT +(ΨJT x PD)
T
J
where:
= thermal characterization parameter
Ψ
JT
T
= thermocouple temperature on top of package
T
= power dissipation in package
P
D
The thermal characterization parameter is measured per JESD51-2 specification published by JEDEC using
a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be
positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over
the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
nc...
I
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
) can be used to determine the junction temperature with a
JT
cale Semiconductor,
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7.6 References
Semiconductor Equipment and Materials International (415) 964-5111
805 East Middlefield Rd.
Mountain View, CA 94043
MIL-SPEC and EIA/JESD (JEDEC) specifications 800-854-7179 or
(Available from Global Engineering Documents) 303-397-7956
JEDEC Specifications http://www.jedec.org
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive
Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its
Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
8 Power Supply and Power Sequencing
This section provides design considerations for the MPC866/859 power supply. The MPC866/859 has a
core voltage (VDDL) and PLL voltage (VDDSYN) that operates at a lower voltage than the I/O voltage
VDDH. The I/O section of the MPC866/859 is supplied with 3.3 V across VDDH and V
Signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], TDI, TDO, TCK, TRST_B, TMS, MII_TXEN, and
MII_MDIO are 5-V tolerant. All inputs cannot be more than 2.5 V greater than VDDH. In addition, 5-V
tolerant pins cannot exceed 5.5 V and the remaining input pins cannot exceed 3.465 V. This restriction
applies to power up/down and normal operation.
(GND).
SS
One consequence of multiple power supplies is that when power is initially applied the voltage rails ramp
up at different rates. The rates depend on the nature of the power supply, the type of load on each power
supply, and the manner in which different voltages are derived. The following restrictions apply:
• VDDL must not exceed VDDH during power up and power down.
• VDDL must not exceed 1.9 V and VDDH must not exceed 3.465 V.
14 MPC866/859 Hardware Specifications MOTOROLA
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These cautions are necessary for the long term reliability of the part. If they are violated, the electrostatic
discharge (ESD) protection diodes are forward-biased and excessi v e current can flo w through these diodes.
If the system power supply design does not control the voltage sequencing, the circuit shown in Figure 4
can be added to meet these requirements. The MUR420 Schottky diodes control the maximum potential
difference between the external bus and core power supplies on powerup and the 1N5820 diodes regulate
the maximum potential difference on powerdown.
nc...
I
Layout Practices
VDDH VDDL
MUR420
1N5820
cale Semiconductor,
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Figure 4. Example Voltage Sequencing Circuit
9 Layout Practices
Each VDD pin on the MPC866/859 should be provided with a low-impedance path to the board’s supply.
Furthermore, each GND pin should be provided with a low-impedance path to ground. The power supply
pins drive distinct groups of logic on chip. The V
least four 0.1 µF bypass capacitors located as close as possible to the four sides of the package. Each board
designed should be characterized and additional appropriate decoupling capacitors should be used if
required. The capacitor leads and associated printed-circuit traces connecting to chip V
be kept to less than 1/2” per capacitor lead. At a minimum, a four-layer board employing two inner layers
as V
All output pins on the MPC866/859 have fast rise and fall times. Printed-circuit (PC) trace interconnection
length should be minimized in order to minimize undershoot and reflections caused by these fast output
switching times. This recommendation particularly applies to the address and data buses. Maximum PC
trace lengths of 6” are recommended. Capacitance calculations should consider all device loads as well as
parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes
especially critical in systems with higher capacitive loads because these loads create higher transient
currents in the V
Special care should be taken to minimize the noise levels on the PLL supply pins. For more information,
please refer to Section 14.4.3, Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1), in the MPC866
User’s Manual.
and GND planes should be used.
DD
and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
DD
power supply should be bypassed to ground using at
DD
and GND should
DD
10 Bus Signal Timing
The maximum bus speed supported by the MPC866/859 is 66 MHz. Higher-speed parts must be operated
in half-speed bus mode (for example, an MPC866/859 used at 100 MHz must be configured for a 50-MHz
bus). Table 7 and Table 8 show the frequency ranges for standard part frequencies.
MOTOROLA MPC866/859 Hardware Specifications 15
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Bus Signal Timing Bus Signal Timing
Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)
Part Freq 50 MHz 66 MHz
Min Max Min Max
Core 40 50 40 66.67
Bus 40 50 40 66.67
Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)
nc...
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Part
Freq
Core 40 50 40 66.67 40 100 40 133.34
Bus 20 25 20 33.33 20 50 20 66.67
50 MHz 66 MHz 100 MHz 133 MHz
Min Max Min Max Min Max Min Max
T able 9 shows the timings for the MPC866/859 at 33, 40, 50, and 66 MHz b us operation. The timing for the
MPC866/859 bus shown in this table assumes a 50-pF load for maximum delays and a 0-pF load for
minimum delays. CLKOUT assumes a 100-pF load maximum delay.
Table 9. Bus Operation Timings
33 MHz 40 MHz 50 MHz 66 MHz
Num Characteristic
Min Max Min Max Min Max Min Max
B1 Bus Period (CLKOUT) See Table 7 — — ——————ns
B1a EXTCLK to CLKOUT phase skew – 2 +2 – 2 +2 – 2 +2 – 2 +2 ns
B1b CLKOUT frequency jitter peak-to-peak — 1 —1—1—1ns
B1c Frequency jitter on EXTCLK — 0.50 — 0.50 — 0.50 — 0.50 %
B1d CLKOUT phase jitter peak-to-peak
for OSCLK ≥ 15 MHz
CLKOUT phase jitter peak-to-peak
for OSCLK < 15 MHz
B2 CLKOUT pulse width low (MIN = 0.4 x
B1, MAX = 0.6 x B1)
—4—4—4—4ns
—5—5—5—5ns
12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns
Unit
B3 CLKOUT pulse width high (MIN = 0.4 x
B1, MAX = 0.6 x B1)
B4 CLKOUT rise time — 4.00 — 4.00 — 4.00 — 4.00 ns
B5 CLKOUT fall time
B7 CLKOUT to A(0:31), BADDR(28:30),
RD/WR
, BURST, D(0:31), DP(0:3)
output hold (MIN = 0.25 x B1)
16 MPC866/859 Hardware Specifications MOTOROLA
12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns
— 4.00 — 4.00 — 4.00 — 4.00 ns
7.60 — 6.30 — 5.00 — 3.80 — ns
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Num Characteristic
Bus Signal Timing
Table 9. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
nc...
I
cale Semiconductor,
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B7a CLKOUT to TSIZ(0:1), REG, RSV,
AT(0:3), BDIP
0.25 x B1)
B7b CLKOUT to BR
VF(0:2), IWP(0:2), LWP(0:1), STS
output hold (MIN = 0.25 x B1)
B8 CLKOUT to A(0:31), BADDR(28:30)
RD/WR
valid (MAX = 0.25 x B1 + 6.3)
B8a CLKOUT to TSIZ(0:1), REG
AT(0:3), BDIP
x B1 + 6.3)
B8b CLKOUT to BR
VF(0:2), IWP(0:2), FRZ, LWP(0:1),
STS
valid 4 (MAX = 0.25 x B1 + 6.3)
B9 CLKOUT to A(0:31), BADDR(28:30),
RD/WR
TSIZ(0:1), REG
High-Z (MAX = 0.25 x B1 + 6.3)
B11 CLKOUT to TS
0.25 x B1 + 6.0)
B11a CLKOUT to T
driven by the memory controller or
PCMCIA interface) (MAX = 0.00 x B1 +
1
9.30
B12 CLKOUT to TS, BB negation (MAX =
0.25 x B1 + 4.8)
B12a CLKOUT to T
driven by the memory controller or
PCMCIA interface) (MAX = 0.00 x B1 +
9.00)
B13 CLKOUT to TS
x B1)
, PTR output hold (MIN =
, BG, FRZ, VFLS(0:1),
, BURST, D(0:31), DP(0:3),
, RSV,
, PTR valid (MAX = 0.25
, BG, VFLS(0:1),
, BURST, D(0:31), DP(0:3),
, RSV, AT(0:3), PTR
, BB assertion (MAX =
A, BI assertion (when
)
A, BI negation (when
, BB High-Z (MIN = 0.25
7.60 — 6.30 — 5.00 — 3.80 — ns
7.60 — 6.30 — 5.00 — 3.80 — ns
— 13.80 — 12.50 — 11.30 — 10.00 ns
— 13.80 — 12.50 — 11.30 — 10.00 ns
— 13.80 — 12.50 — 11.30 — 10.00 ns
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
7.60 13.60 6.30 12.30 5.00 11.00 3.80 9.80 ns
2.50 9.30 2.50 9.30 2.50 9.30 2.50 9.80 ns
7.60 12.30 6.30 11.00 5.00 9.80 3.80 8.50 ns
2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns
7.60 21.60 6.30 20.30 5.00 19.00 3.80 14.00 ns
B13a CLKOUT to T
by the memory controller or PCMCIA
interface) (MIN = 0.00 x B1 + 2.5)
B14 CLKOUT to TEA
0.00 x B1 + 9.00)
B15 CLKOUT to TEA
B1 + 2.50)
B16 T
A, BI valid to CLKOUT (setup time)
(MIN = 0.00 x B1 + 6.00)
MOTOROLA MPC866/859 Hardware Specifications 17
A, BI High-Z (when driven
assertion (MAX =
High-Z (MIN = 0.00 x
2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
2.50 9.00 2.50 9.00 2.50 9.00 2.50 9.00 ns
2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns
6.00 — 6.00 — 6.00 — 6.00 — ns
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Bus Signal Timing Bus Signal Timing
Num Characteristic
Freescale Semiconductor, Inc.
Table 9. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz 66 MHz
Min Max Min Max Min Max Min Max
Unit
B16a TEA, KR, RETRY, CR valid to
CLKOUT (setup time) (MIN = 0.00 x B1
+ 4.5)
B16b BB
B17 CLKOUT to TA, TEA, BI, BB, BG, BR
B17a CLKOUT to KR, RETRY, CR valid
B18 D(0:31), DP(0:3) valid to CLKOUT
nc...
I
B19 CLKOUT rising edge to D(0:31),
B20 D(0:31), DP(0:3) valid to CLKOUT
B21 CLKOUT falling edge to D(0:31),
B22 CLKOUT rising edge to CS
B22a CLKOUT falling edge to CS
cale Semiconductor,
B22b CLKOUT falling edge to CS
, BG, BR, valid to CLKOUT (setup
2
time)
(4 MIN = 0.00 x B1 + 0.00 )
valid (hold time) (MIN = 0.00 x B1 +
3
1.00
)
(hold time) (MIN = 0.00 x B1 + 2.00)
rising edge (setup time)
x B1 + 6.00)
DP(0:3) valid (hold time)
x B1 + 1.00
falling edge (setup time)
x B1 + 4.00)
DP(0:3) valid (hold Time)
x B1 + 2.00)
GPCM ACS = 00 (MAX = 0.25 x B1 +
6.3)
GPCM ACS = 10, TRLX = 0 (MAX =
0.00 x B1 + 8.00)
GPCM ACS = 11, TRLX = 0, EBDF = 0
(MAX = 0.25 x B1 + 6.3)
5
)
4
(MIN = 0.00
4
(MIN = 0.00
6
(MIN = 0.00
6
(MIN = 0.00
asserted
asserted
asserted
4.50 — 4.50 — 4.50 — 4.50 — ns
4.00 — 4.00 — 4.00 — 4.00 — ns
1.00 — 1.00 — 1.00 — 2.00 — ns
2.00 — 2.00 — 2.00 — 2.00 — ns
6.00 — 6.00 — 6.00 — 6.00 — ns
1.00 — 1.00 — 1.00 — 2.00 — ns
4.00 — 4.00 — 4.00 — 4.00 — ns
2.00 — 2.00 — 2.00 — 2.00 — ns
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
— 8.00 — 8.00 — 8.00 — 8.00 ns
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
Frees
B22c CLKOUT falling edge to CS
GPCM ACS = 11, TRLX = 0, EBDF = 1
(MAX = 0.375 x B1 + 6.6)
B23 CLKOUT rising edge to CS
GPCM read access, GPCM write
access ACS = 00, TRLX = 0 & CSNT =
0 (MAX = 0.00 x B1 + 8.00)
B24 A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 10, TRLX = 0
(MIN = 0.25 x B1 - 2.00)
18 MPC866/859 Hardware Specifications MOTOROLA
asserted
negated
10.90 18.00 10.90 16.00 7.00 14.10 5.20 12.30 ns
2.00 8.00 2.00 8.00 2.00 8.00 2.00 8.00 ns
5.60 — 4.30 — 3.00 — 1.80 — ns
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Num Characteristic
Bus Signal Timing
Table 9. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
nc...
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B24a A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 11, TRLX = 0
(MIN = 0.50 x B1 - 2.00)
B25 CLKOUT rising edge to OE
asserted (MAX = 0.00 x B1 + 9.00)
B26 CLKOUT rising edge to OE
(MAX = 0.00 x B1 + 9.00)
B27 A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 10, TRLX = 1
(MIN = 1.25 x B1 - 2.00)
B27a A(0:31) and BADDR(28:30) to CS
asserted GPCM ACS = 11, TRLX = 1
(MIN = 1.50 x B1 - 2.00)
B28 CLKOUT rising edge to WE
negated GPCM write access CSNT =
0 (MAX = 0.00 x B1 + 9.00)
B28a CLKOUT falling edge to WE
negated GPCM write access TRLX =
0,1, CSNT = 1, EBDF = 0 (MAX = 0.25
x B1 + 6.80)
B28b CLKOUT falling edge to CS
GPCM write access TRLX = 0,1,
CSNT = 1, ACS = 10 or ACS = 11,
EBDF = 0 (MAX = 0.25 x B1 + 6.80)
B28c CLKOUT falling edge to WE
negated GPCM write access TRLX =
0, CSNT = 1 write access TRLX = 0,1,
CSNT = 1, EBDF = 1 (MAX = 0.375 x
B1 + 6.6)
B28d CLKOUT falling edge to CS
GPCM write access TRLX = 0,1,
CSNT = 1, ACS = 10, or ACS = 11,
EBDF = 1 (MAX = 0.375 x B1 + 6.6)
B29 WE
(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access, CSNT = 0,
EBDF = 0 (MIN = 0.25 x B1 - 2.00)
, WE(0:3)
negated
(0:3)
(0:3)
negated
(0:3)
negated
13.20 — 10.50 — 8.00 — 5.60 — ns
— 9.00 — 9.00 — 9.00 — 9.00 ns
2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.00 ns
35.90 — 29.30 — 23.00 — 16.90 — ns
43.50 — 35.50 — 28.00 — 20.70 — ns
— 9.00 — 9.00 — 9.00 — 9.00 ns
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
— 14.30 — 13.00 — 11.80 — 10.50 ns
10.90 18.00 10.90 18.00 7.00 14.30 5.20 12.30 ns
— 18.00 — 18.00 — 14.30 — 12.30 ns
5.60 — 4.30 — 3.00 — 1.80 — ns
B29a WE
B29b CS
MOTOROLA MPC866/859 Hardware Specifications 19
(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access, TRLX = 0,
CSNT = 1, EBDF = 0 (MIN = 0.50 x B1
– 2.00)
negated to D(0:31), DP(0:3), High
Z GPCM write access, ACS = 00,
TRLX = 0,1 & CSNT = 0 (MIN = 0.25 x
B1– 2.00)
13.20 — 10.50 — 8.00 — 5.60 — ns
5.60 — 4.30 — 3.00 — 1.80 — ns
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Bus Signal Timing Bus Signal Timing
Num Characteristic
Freescale Semiconductor, Inc.
Table 9. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz 66 MHz
Min Max Min Max Min Max Min Max
Unit
nc...
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cale Semiconductor,
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B29c CS negated to D(0:31), DP(0:3)
High-Z GPCM write access, TRLX = 0,
CSNT = 1, ACS = 10, or ACS = 11,
EBDF = 0 (MIN = 0.50 x B1 – 2.00)
B29d WE
B29e CS
B29f WE
B29g CS
B29h WE
B29i CS
B30 CS
B30a WE(0:3) negated to A(0:31),
(0:3) negated to D(0:31), DP(0:3)
High-Z GPCM write access, TRLX = 1,
CSNT = 1, EBDF = 0 (MIN = 1.50 x B1
– 2.00)
negated to D(0:31), DP(0:3)
High-Z GPCM write access, TRLX = 1,
CSNT = 1, ACS = 10, or ACS = 11,
EBDF = 0 (MIN = 1.50 x B1 – 2.00)
(0:3) negated to D(0:31), DP(0:3)
High Z GPCM write access, TRLX = 0,
CSNT = 1, EBDF = 1 (MIN = 0.375 x
B1 – 6.30)
negated to D(0:31), DP(0:3)
High-Z GPCM write access, TRLX = 0,
CSNT = 1 ACS = 10 or ACS = 11,
EBDF = 1 (MIN = 0.375 x B1 – 6.30)
(0:3) negated to D(0:31), DP(0:3)
High Z GPCM write access, TRLX = 1,
CSNT = 1, EBDF = 1 (MIN = 0.375 x
B1 – 3.30)
negated to D(0:31), DP(0:3)
High-Z GPCM write access, TRLX = 1,
CSNT = 1, ACS = 10 or ACS = 11,
EBDF = 1 (MIN = 0.375 x B1 – 3.30)
, WE(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM write
7
access
BADDR(28:30) invalid GPCM, write
access, TRLX = 0, CSNT = 1, CS
negated to A(0:31) invalid GPCM write
access TRLX = 0, CSNT =1 ACS = 10,
or ACS == 11, EBDF = 0 (MIN = 0.50 x
B1 – 2.00)
(MIN = 0.25 x B1 – 2.00)
13.20 — 10.50 — 8.00 — 5.60 — ns
43.50 — 35.50 — 28.00 — 20.70 — ns
43.50 — 35.50 — 28.00 — 20.70 — ns
5.00 — 3.00 — 1.10 — 0.00 — ns
5.00 — 3.00 — 1.10 — 0.00 — ns
38.40 — 31.10 — 24.20 — 17.50 — ns
38.40 — 31.10 — 24.20 — 17.50 — ns
5.60 — 4.30 — 3.00 — 1.80 — ns
13.20 — 10.50 — 8.00 — 5.60 — ns
B30b WE
20 MPC866/859 Hardware Specifications MOTOROLA
(0:3) negated to A(0:31) invalid
GPCM BADDR(28:30) invalid GPCM
write access, TRLX = 1, CSNT = 1. CS
negated to A(0:31) invalid GPCM write
access TRLX = 1, CSNT = 1, ACS =
10, or ACS == 11 EBDF = 0 (MIN =
1.50 x B1 – 2.00)
43.50 — 35.50 — 28.00 — 20.70 — ns
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Num Characteristic
Bus Signal Timing
Table 9. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
nc...
I
cale Semiconductor,
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B30c WE(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM write
access, TRLX = 0, CSNT = 1. CS
negated to A(0:31) invalid GPCM write
access, TRLX = 0, CSNT = 1 ACS =
10, ACS == 11, EBDF = 1 (MIN = 0.375
x B1 – 3.00)
B30d WE
B31 CLKOUT falling edge to CS
B31a CLKOUT falling edge to CS
B31b CLKOUT rising edge to CS
B31c CLKOUT rising edge to CS
B31d CLKOUT falling edge to CS
B32 CLKOUT falling edge to BS
(0:3) negated to A(0:31),
BADDR(28:30) invalid GPCM write
access TRLX = 1, CSNT =1, CS
negated to A(0:31) invalid GPCM write
access TRLX = 1, CSNT = 1, ACS = 10
or 11, EBDF = 1
requested by control bit CST4 in the
corresponding word in the UPM (MAX
= 0.00 X B1 + 6.00)
requested by control bit CST1 in the
corresponding word in the UPM (MAX
= 0.25 x B1 + 6.80)
requested by control bit CST2 in the
corresponding word in the UPM (MAX
= 0.00 x B1 + 8.00)
requested by control bit CST3 in the
corresponding word in the UPM (MAX
= 0.25 x B1 + 6.30)
requested by control bit CST1 in the
corresponding word in the UPM EBDF
= 1 (MAX = 0.375 x B1 + 6.6)
requested by control bit BST4 in the
corresponding word in the UPM (MAX
= 0.00 x B1 + 6.00)
valid, as
valid, as
valid, as
valid, as
valid, as
valid, as
8.40 — 6.40 — 4.50 — 2.70 — ns
38.67 — 31.38 — 24.50 — 17.83 — ns
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
B32a CLKOUT falling edge to BS
requested by control bit BST1 in the
corresponding word in the UPM, EBDF
= 0 (MAX = 0.25 x B1 + 6.80)
B32b CLKOUT rising edge to BS
requested by control bit BST2 in the
corresponding word in the UPM (MAX
= 0.00 x B1 + 8.00)
MOTOROLA MPC866/859 Hardware Specifications 21
valid, as
valid, as
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
1.50 8.00 1.50 8.00 1.50 8.00 1.50 8.00 ns
For More Information On This Product,
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Bus Signal Timing Bus Signal Timing
Num Characteristic
Freescale Semiconductor, Inc.
Table 9. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz 66 MHz
Min Max Min Max Min Max Min Max
Unit
nc...
I
cale Semiconductor,
Frees
B32c CLKOUT rising edge to BS valid, as
requested by control bit BST3 in the
corresponding word in the UPM (MAX
= 0.25 x B1 + 6.80)
B32d CLKOUT falling edge to BS
requested by control bit BST1 in the
corresponding word in the UPM, EBDF
= 1 (MAX = 0.375 x B1 + 6.60)
B33 CLKOUT falling edge to GPL
requested by control bit GxT4 in the
corresponding word in the UPM (MAX
= 0.00 x B1 + 6.00)
B33a CLKOUT rising edge to GPL
requested by control bit GxT3 in the
corresponding word in the UPM (MAX
= 0.25 x B1 + 6.80)
B34 A(0:31), BADDR(28:30), and D(0:31)
to CS
valid, as requested by control bit
CST4 in the corresponding word in the
UPM (MIN = 0.25 x B1 - 2.00)
B34a A(0:31), BADDR(28:30), and D(0:31)
to CS
valid, as requested by control bit
CST1 in the corresponding word in the
UPM (MIN = 0.50 x B1 – 2.00)
B34b A(0:31), BADDR(28:30), and D(0:31)
to CS
valid, as requested by CST2 in
the corresponding word in UPM (MIN =
0.75 x B1 – 2.00)
B35 A(0:31), BADDR(28:30) to CS
requested by control bit BST4 in the
corresponding word in the UPM (MIN =
0.25 x B1 – 2.00)
B35a A(0:31), BADDR(28:30), and D(0:31)
to BS
valid, as Requested by BST1 in
the corresponding word in the UPM
(MIN = 0.50 x B1 – 2.00)
valid- as
valid, as
valid, as
valid, as
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
13.30 18.00 11.30 16.00 9.40 14.10 7.60 12.30 ns
1.50 6.00 1.50 6.00 1.50 6.00 1.50 6.00 ns
7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns
5.60 — 4.30 — 3.00 — 1.80 — ns
13.20 — 10.50 — 8.00 — 5.60 — ns
20.70 — 16.70 — 13.00 — 9.40 — ns
5.60 — 4.30 — 3.00 — 1.80 — ns
13.20 — 10.50 — 8.00 — 5.60 — ns
B35b A(0:31), BADDR(28:30), and D(0:31)
to BS
valid, as requested by control bit
BST2 in the corresponding word in the
UPM (MIN = 0.75 x B1 – 2.00)
B36 A(0:31), BADDR(28:30), and D(0:31)
to GPL
valid as requested by control bit
GxT4 in the corresponding word in the
UPM (MIN = 0.25 x B1 – 2.00)
22 MPC866/859 Hardware Specifications MOTOROLA
20.70 — 16.70 — 13.00 — 9.40 — ns
5.60 — 4.30 — 3.00 — 1.80 — ns
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Num Characteristic
Bus Signal Timing
Table 9. Bus Operation Timings (continued)
33 MHz 40 MHz 50 MHz 66 MHz
Unit
Min Max Min Max Min Max Min Max
B37 UPWAIT valid to CLKOUT falling
B38 CLKOUT falling edge to UPWAIT
B39 AS valid to CLKOUT rising edge 9 (MIN
B40 A(0:31), TSIZ(0:1), RD/WR
B41 TS
nc...
I
cale Semiconductor,
B42 CLKOUT rising edge to TS
B43 AS
1
For part speeds above 50 MHz, use 9.80 ns for B11a.
2
The timing required for BR input is relevant when the MPC866/859 is selected to work with the internal bus arbiter.
The timing for BG
3
For part speeds above 50 MHz, use 2 ns for B17.
4
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of CLKOUT, in which the TA input signal
is asserted.
5
For part speeds above 50 MHz, use 2 ns for B19.
6
The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for
read accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats, where
DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
7
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
8
The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally. The timings specified in B37
and B38 are specified to enable the freeze of the UPM output signals as described in Figure 20.
9
The AS signal is considered asynchronous to CLKOUT. The timing B39 is specified in order to allow the behavior
specified in Figure 23.
8
edge
(MIN = 0.00 x B1 + 6.00)
8
valid
(MIN = 0.00 x B1 + 1.00)
= 0.00 x B1 + 7.00)
, BURST,
valid to CLKOUT rising edge (MIN =
0.00 x B1 + 7.00)
valid to CLKOUT rising edge (setup
time) (MIN = 0.00 x B1 + 7.00)
valid (hold
time) (MIN = 0.00 x B1 + 2.00)
negation to memory controller
signals negation (MAX = TBD)
input is relevant when the MPC866/859 is selected to work with the external bus arbiter.
6.00 — 6.00 — 6.00 — 6.00 — ns
1.00 — 1.00 — 1.00 — 1.00 — ns
7.00 — 7.00 — 7.00 — 7.00 — ns
7.00 — 7.00 — 7.00 — 7.00 — ns
7.00 — 7.00 — 7.00 — 7.00 — ns
2.00 — 2.00 — 2.00 — 2.00 — ns
— TBD — TBD — TBD — TBD ns
Frees
MOTOROLA MPC866/859 Hardware Specifications 23
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Bus Signal Timing Bus Signal Timing
Freescale Semiconductor, Inc.
Figure 5 shows the control timing diagram.
nc...
I
cale Semiconductor,
Frees
CLKOUT
Outputs
Outputs
Inputs
Inputs
A
B Minimum output hold time
C Minimum input setup time specification
D Minimum input hold time specification
2.0 V
0.8 V
A
B
2.0 V
0.8 V
B
2.0 V
0.8 V
C
2.0 V
0.8 V
Maximum output delay specification
Figure 5. Control Timing
Figure 6 shows the timing for the external clock.
CLKOUT
2.0 V
0.8 V
0.8 V
A
D
2.0 V
0.8 V
2.0 V
0.8 V
C
2.0 V
0.8 V
2.0 V
D
2.0 V
0.8 V
B1
B1
B4
Figure 6. External Clock Timing
24 MPC866/859 Hardware Specifications MOTOROLA
B5
B3
B2
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Figure 7 shows the timing for the synchronous output signals.
CLKOUT
B7 B9
Output
Signals
Output
Signals
nc...
I
Output
Signals
B7b
Bus Signal Timing
B8
B8a
B9B7a
B8b
cale Semiconductor,
Frees
Figure 7. Synchronous Output Signals Timing
Figure 8 shows the timing for the synchronous active pull-up and open-drain output signals.
CLKOUT
B13
B12B11
TS
, BB
B13a
B11a B12a
TA, BI
B14
B15
TEA
Figure 8. Synchronous Active Pull-Up Resistor and Open-Drain Output Signals Timing
MOTOROLA MPC866/859 Hardware Specifications 25
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Freescale Semiconductor, Inc.
Bus Signal Timing Bus Signal Timing
Figure 9 shows the timing for the synchronous input signals.
CLKOUT
T
A, BI
TEA, KR,
RETR
Y, CR
nc...
I
B16
B17
B16a
B17a
B16b
B17
cale Semiconductor,
Frees
BB, BG, BR
Figure 9. Synchronous Input Signals Timing
Figure 10 shows normal case timing for input data. It also applies to normal read accesses under the control
of the UPM in the memory controller.
CLKOUT
B16
B17
T
A
B18
B19
D[0:31],
DP[0:3]
Figure 10. Input Data Timing in Normal Case
26 MPC866/859 Hardware Specifications MOTOROLA
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Freescale Semiconductor, Inc.
Figure 11 shows the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the
UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
CLKOUT
T
A
D[0:31],
DP[0:3]
Bus Signal Timing
B20
B21
nc...
I
cale Semiconductor,
Frees
Figure 11. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1
Figure 12 through Figure 15 show the timing for the external bus read controlled by v arious GPCM factors.
CLKOUT
B11 B12
TS
B8
A[0:31]
B22
CSx
B25
OE
B28
B23
B26
WE[0:3]
B18
D[0:31],
DP[0:3]
Figure 12. External Bus Read Timing (GPCM Controlled—ACS = 00)
MOTOROLA MPC866/859 Hardware Specifications 27
B19
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Bus Signal Timing Bus Signal Timing
CLKOUT
TS
A[0:31]
Freescale Semiconductor, Inc.
B11 B12
B8
nc...
I
cale Semiconductor,
Frees
B22a
CSx
B25B24
OE
D[0:31],
DP[0:3]
Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 0 or 1, ACS = 10)
CLKOUT
B11 B12
TS
B22bB8
A[0:31]
B22c B23
CSx
B24a B25 B26
B23
B26
B19B18
OE
B19B18
D[0:31],
DP[0:3]
Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = 0 or 1, ACS = 11)
28 MPC866/859 Hardware Specifications MOTOROLA
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CLKOUT
TS
A[0:31]
Freescale Semiconductor, Inc.
B11 B12
B8
Bus Signal Timing
B22a
CSx
B27
nc...
I
Figure 15. External Bus Read Timing (GPCM Controlled—TRLX = 0 or 1, ACS = 10, ACS = 11)
OE
D[0:31],
DP[0:3]
B27a
B22b B22c B19B18
cale Semiconductor,
B23
B26
Frees
MOTOROLA MPC866/859 Hardware Specifications 29
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Freescale Semiconductor, Inc.
Bus Signal Timing Bus Signal Timing
Figure 16 through Figure 18 show the timing for the external bus write controlled by various GPCM f actors.
CLKOUT
B11
TS
B8
A[0:31]
B22 B23
CSx
nc...
I
WE[0:3]
B26
OE
D[0:31],
DP[0:3]
Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 0)
cale Semiconductor,
B12
B8 B9
B30
B28B25
B29b
B29
Frees
30 MPC866/859 Hardware Specifications MOTOROLA
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CLKOUT
Freescale Semiconductor, Inc.
Bus Signal Timing
B11
TS
B8
A[0:31]
B22
CSx
nc...
I
WE[0:3]
B26
OE
B8
D[0:31],
DP[0:3]
Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1)
cale Semiconductor,
B12
B28b B28d
B25
B28aB9B28c
B30a B30c
B23
B29c B29g
B29a B29f
Frees
MOTOROLA MPC866/859 Hardware Specifications 31
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Bus Signal Timing Bus Signal Timing
CLKOUT
TS
Freescale Semiconductor, Inc.
B12B11
B8
A[0:31]
B28b B28d
CSx
B25
nc...
I
WE[0:3]
B26 B29d B29h
OE
B28a B28c B9B8
D[0:31],
DP[0:3]
Figure 18. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1)
cale Semiconductor,
B30dB30b
B29e B29i
B29b
B23B22
Frees
32 MPC866/859 Hardware Specifications MOTOROLA
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Freescale Semiconductor, Inc.
Figure 19 shows the timing for the external bus controlled by the UPM.
CLKOUT
B8
A[0:31]
CSx
nc...
I
B34
B34b
B31
B34a
B32
B31a
B31d
B32a B32d
Bus Signal Timing
B31c
B31b
B32c
B32b
cale Semiconductor,
Frees
BS_A
[0:3],
BS_B
[0:3]
GPL_A[0:5],
GPL_B
[0:5]
B36
B35
B35a
B35b
B33
Figure 19. External Bus Timing (UPM Controlled Signals)
B33a
MOTOROLA MPC866/859 Hardware Specifications 33
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Freescale Semiconductor, Inc.
Bus Signal Timing Bus Signal Timing
Figure 20 shows the timing for the asynchronous asserted UPWAIT signal controlled by the UPM.
CLKOUT
B37
UPWAIT
CSx
BS_A[0:3],
BS_B
[0:3]
B38
nc...
I
cale Semiconductor,
Frees
GPL_A
[0:5],
GPL_B
[0:5]
Figure 20. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing
Figure 21 shows the timing for the asynchronous negated UPWAIT signal controlled by the UPM.
CLKOUT
B37
UPWAIT
B38
CSx
BS_A[0:3],
BS_B
[0:3]
GPL_A
[0:5],
GPL_B
[0:5]
Figure 21. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing
34 MPC866/859 Hardware Specifications MOTOROLA
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Figure 22 shows the timing for the synchronous external master access controlled by the GPCM.
CLKOUT
TS
A[0:31],
TSIZ[0:1],
R/W
, BURST
CSx
Bus Signal Timing
B41 B42
B40
B22
nc...
I
cale Semiconductor,
Frees
Figure 22. Synchronous External Master Access Timing (GPCM Handled ACS = 00)
Figure 23 shows the timing for the asynchronous external master memory access controlled by the GPCM.
CLKOUT
B39
AS
B40
A[0:31],
TSIZ[0:1],
R/W
B22
CSx
Figure 23. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00)
Figure 24 shows the timing for the asynchronous external master control signals negation.
AS
B43
CSx, WE[0:3],
OE
, GPLx,
BS
[0:3]
Figure 24. Asynchronous External Master—Control Signals Negation Timing
MOTOROLA MPC866/859 Hardware Specifications 35
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Freescale Semiconductor, Inc.
Bus Signal Timing Bus Signal Timing
Table 10 shows the interrupt timing for the MPC866/859.
Table 10. Interrupt Timing
Num Characteristic
I39 IRQ
I40 IRQx hold time after CLKOUT 2.00 — ns
I41 IRQx pulse width low 3.00 — ns
I42 IRQx pulse width high 3.00 — ns
I43 IRQx edge-to-edge time 4xT
1
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
level sensitive. The IRQ
to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ
nc...
I
no direct relation with the total system interrupt latency that the MPC866/859 is able to support.
Figure 25 shows the interrupt detection timing for the external level-sensitive lines.
Figure 26 shows the interrupt detection timing for the external edge-sensitive lines.
cale Semiconductor,
x valid to CLKOUT rising edge (setup time) 6.00 — ns
lines are synchronized internally and do not have to be asserted or negated with reference
CLKOUT
IRQ
x
Figure 25. Interrupt Detection Timing for External Level Sensitive Lines
CLKOUT
1
I39
I40
I41 I42
All Frequencies
Unit
Min Max
CLOCKOUT
lines detection circuitry, and has
——
Frees
IRQ
x
I43
I43
Figure 26. Interrupt Detection Timing for External Edge Sensitive Lines
36 MPC866/859 Hardware Specifications MOTOROLA
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Table 11 shows the PCMCIA timing for the MPC866/859.
Table 11. PCMCIA Timing
33 MHz 40 MHz 50 MHz 66 MHz
Num Characteristic
Min Max Min Max Min Max Min Max
Bus Signal Timing
Unit
nc...
I
cale Semiconductor,
Frees
A(0:31), REG
P44
Strobe asserted
– 2.00)
A(0:31), REG
P45
negation
CLKOUT to REG valid (MAX = 0.25
P46
x B1 + 8.00)
CLKOUT to REG
P47
0.25 x B1 + 1.00)
CLKOUT to CE1
P48
(MAX = 0.25 x B1 + 8.00)
CLKOUT to CE1
P49
(MAX = 0.25 x B1 + 8.00)
CLKOUT to PCOE
P50
IO
WR assert time (MAX = 0.00 x
B1 + 11.00)
CLKOUT to PCOE
IO
P51
P52
P53
P54
P55
P56
1
WR negate time (MAX = 0.00 x
B1 + 11.00)
CLKOUT to ALE assert time (MAX
= 0.25 x B1 + 6.30)
CLKOUT to ALE negate time (MAX
= 0.25 x B1 + 8.00)
PCWE
invalid
AITA and WAITB valid to
W
CLKOUT rising edge
x B1 + 8.00)
CLKOUT rising edge to W
W
AITB invalid1 (MIN = 0.00 x B1 +
2.00)
PSST = 1. Otherwise, add PSST times cycle time.
PSHT = 0. Otherwise, add PSHT times cycle time.
These synchronous timings define when the W
current cycle. The W
PCMCIA Interface in the MPC866 PowerQUICC User’s Manual.
valid to PCMCIA
1
(MIN = 0.75 x B1
valid to ALE
1
(MIN = 1.00 x B1 – 2.00)
invalid (MIN =
, CE2 asserted
, CE2 negated
, IORD, PCWE,
, IORD, PCWE,
, IOWR negated to D(0:31)
1
(MIN = 0.25 x B1 – 2.00)
1
(MIN = 0.00
AITA and
AITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. See
20.70 — 16.70 — 13.00 — 9.40 — ns
28.30 — 23.00 — 18.00 — 13.20 — ns
7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns
8.60 — 7.30 — 6.00 — 4.80 — ns
7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns
7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.80 ns
— 11.00 — 11.00 — 11.00 — 11.00 ns
2.00 11.00 2.00 11.00 2.00 11.00 2.00 11.00 ns
7.60 13.80 6.30 12.50 5.00 11.30 3.80 10.00 ns
— 15.60 — 14.30 — 13.00 — 11.80 ns
5.60 — 4.30 — 3.00 — 1.80 — ns
8.00 — 8.00 — 8.00 — 8.00 — ns
2.00 — 2.00 — 2.00 — 2.00 — ns
AITx signals are detected in order to freeze (or relieve) the PCMCIA
MOTOROLA MPC866/859 Hardware Specifications 37
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Bus Signal Timing Bus Signal Timing
Figure 27 shows the PCMCIA access cycle timing for the external bus read.
CLKOUT
TS
A[0:31]
P44
P46 P45
REG
P48 P49
nc...
I
CE1/CE2
PCOE, IORD
P53P52 P52
ALE
D[0:31]
Figure 27. PCMCIA Access Cycles Timing External Bus Read
cale Semiconductor,
P47
P51P50
B19B18
Frees
38 MPC866/859 Hardware Specifications MOTOROLA
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Figure 28 shows the PCMCIA access cycle timing for the external bus write.
CLKOUT
TS
A[0:31]
P44
Bus Signal Timing
P46 P45
REG
nc...
I
cale Semiconductor,
Figure 29 shows the PCMCIA WAIT signals detection timing.
CE1/CE2
PCWE, IOWR
ALE
D[0:31]
Figure 28. PCMCIA Access Cycles Timing External Bus Write
CLKOUT
P48 P49
P53P52 P52
P47
P51P50
P54
B9B8
Frees
P55
P56
W
AITx
Figure 29. PCMCIA WAIT Signals Detection Timing
MOTOROLA MPC866/859 Hardware Specifications 39
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Bus Signal Timing Bus Signal Timing
Freescale Semiconductor, Inc.
Table 12 shows the PCMCIA port timing for the MPC866/859.
Table 12. PCMCIA Port Timing
33 MHz 40 MHz 50 MHz 66 MHz
Num Characteristic
Min Max Min Max Min Max Min Max
Unit
nc...
I
cale Semiconductor,
Frees
CLKOUT to OPx, valid (MAX = 0.00 x B1
P57
+ 19.00)
HRESET
P58
0.75 x B1 + 3.00)
IP_Xx valid to CLKOUT rising edge (MIN
P59
= 0.00 x B1 + 5.00)
CLKOUT rising edge to IP_Xx invalid
P60
(MIN = 0.00 x B1 + 1.00)
1
OP2 and OP3 only.
negated to OPx drive 1(MIN =
— 19.00 — 19.00 — 19.00 — 19.00 ns
25.70 — 21.70 — 18.00 — 14.40 — ns
5.00 — 5.00 — 5.00 — 5.00 — ns
1.00 — 1.00 — 1.00 — 1.00 — ns
Figure 30 shows the PCMCIA output port timing for the MPC866/859.
CLKOUT
P57
Output
Signals
HRESET
P58
OP2, OP3
Figure 30. PCMCIA Output Port Timing
Figure 31 shows the PCMCIA output port timing for the MPC866/859.
CLKOUT
P59
P60
Input
Signals
Figure 31. PCMCIA Input Port Timing
40 MPC866/859 Hardware Specifications MOTOROLA
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Table 13 shows the debug port timing for the MPC866/859.
Num Characteristic
Table 13. Debug Port Timing
Bus Signal Timing
All Frequencies
Unit
Min Max
nc...
I
cale Semiconductor,
Frees
D61 DSCK cycle time 3xT
D62 DSCK clock pulse width 1.25xT
D63 DSCK rise and fall times 0.00 3.00 ns
D64 DSDI input data setup time 8.00 — ns
D65 DSDI data hold time 5.00 — ns
D66 DSCK low to DSDO data valid 0.00 15.00 ns
D67 DSCK low to DSDO invalid 0.00 2.00 ns
Figure 32 shows the input timing for the debug port clock.
DSCK
D61
D61
D63
Figure 32. Debug Port Clock Input Timing
Figure 33 shows the timing for the debug port.
DSCK
DSDI
D66
D62
D62
D64
D65
D67
CLOCKOUT
CLOCKOUT
D63
—
—
DSDO
Figure 33. Debug Port Timings
MOTOROLA MPC866/859 Hardware Specifications 41
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Bus Signal Timing Bus Signal Timing
Freescale Semiconductor, Inc.
Table 14 shows the reset timing for the MPC866/859.
Table 14. Reset Timing
33 MHz 40 MHz 50 MHz 66 MHz
Num Characteristic
Min Max Min Max Min Max Min Max
Unit
nc...
I
cale Semiconductor,
Frees
CLKOUT to HRESET
R69
(MAX = 0.00 x B1 + 20.00)
CLKOUT to SRESET
R70
(MAX = 0.00 x B1 + 20.00)
RSTCONF
R71
B1)
R72— —————————
Configuration data to HRESET rising
R73
edge setup time (MIN = 15.00 x B1 +
50.00)
Configuration data to RSTCONF
edge setup time (MIN = 0.00 x B1 +
R74
350.00)
Configuration data hold time after
R75
RSTCONF
0.00)
Configuration data hold time after
R76
HRESET
0.00)
HRESET
data out drive (MAX = 0.00 x B1 +
R77
25.00)
RSTCONF
R78
impedance (MAX = 0.00 x B1 + 25.00)
CLKOUT of last rising edge before chip
R79
three-states HRESET
impedance (MAX = 0.00 x B1 + 25.00)
R80 DSDI, DSCK setup (MIN = 3.00 x B1) 90.90 — 75.00 — 60.00 — 45.50 — ns
DSDI, DSCK hold time (MIN = 0.00 x B1
R81
+ 0.00)
SRESET
R82
edge for DSDI and DSCK sample (MIN
= 8.00 x B1)
pulse width (MIN = 17.00 x
negation (MIN = 0.00 x B1 +
negation (MIN = 0.00 x B1 +
and RSTCONF asserted to
negated to data out high
negated to CLKOUT rising
high impedance
high impedance
rising
to data out high
— 20.00 — 20.00 — 20.00 — 20.00 ns
— 20.00 — 20.00 — 20.00 — 20.00 ns
515.20 — 425.00 — 340.00 — 257.60 — ns
504.50 — 425.00 — 350.00 — 277.30 — ns
350.00 — 350.00 — 350.00 — 350.00 — ns
0.00 — 0.00 — 0.00 — 0.00 — ns
0.00 — 0.00 — 0.00 — 0.00 — ns
— 25.00 — 25.00 — 25.00 — 25.00 ns
— 25.00 — 25.00 — 25.00 — 25.00 ns
— 25.00 — 25.00 — 25.00 — 25.00 ns
0.00 — 0.00 — 0.00 — 0.00 — ns
242.40 — 200.00 — 160.00 — 121.20 — ns
42 MPC866/859 Hardware Specifications MOTOROLA
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Freescale Semiconductor, Inc.
Figure 34 shows the reset timing for the data bus configuration.
HRESET
RSTCONF
D[0:31] (IN)
Figure 34. Reset Timing—Configuration from Data Bus
nc...
I
R71
R74
Bus Signal Timing
R76
R73
R75
cale Semiconductor,
Frees
Figure 35 shows the reset timing for the data bus weak drive during configuration.
CLKOUT
R69
HRESET
R79
RSTCONF
R77 R78
D[0:31] (OUT)
(Weak)
Figure 35. Reset Timing—Data Bus Weak Drive During Configuration
MOTOROLA MPC866/859 Hardware Specifications 43
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Freescale Semiconductor, Inc.
IEEE 1149.1 Electrical Specifications IEEE 1149.1 Electrical Specifications
Figure 36 shows the reset timing for the debug port configuration.
CLKOUT
SRESET
DSCK, DSDI
Figure 36. Reset Timing—Debug Port Configuration
nc...
I
R70
R81
R82
R80R80
R81
11 IEEE 1149.1 Electrical Specifications
cale Semiconductor,
Frees
Table 15 shows the JTAG timings for the MPC866/859 shown in Figure 37 through Figure 40.
Num Characteristic
J82 TCK cycle time 100.00 — ns
J83 TCK clock pulse width measured at 1.5 V 40.00 — ns
J84 TCK rise and fall times 0.00 10.00 ns
J85 TMS, TDI data setup time 5.00 — ns
J86 TMS, TDI data hold time 25.00 — ns
J87 TCK low to TDO data valid — 27.00 ns
J88 TCK low to TDO data invalid 0.00 — ns
J89 TCK low to TDO high impedance — 20.00 ns
J90 TRST
J91 TRST setup time to TCK low 40.00 — ns
J92 TCK falling edge to output valid — 50.00 ns
J93 TCK falling edge to output valid out of high impedance — 50.00 ns
assert time 100.00 — ns
Table 15. JTAG Timing
All Frequencies
Unit
Min Max
J94 TCK falling edge to output high impedance — 50.00 ns
J95 Boundary scan input valid to TCK rising edge 50.00 — ns
J96 TCK rising edge to boundary scan input invalid 50.00 — ns
44 MPC866/859 Hardware Specifications MOTOROLA
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TCK
TCK
Freescale Semiconductor, Inc.
J84 J84
IEEE 1149.1 Electrical Specifications
J82 J83
J82 J83
Figure 37. JTAG Test Clock Input Timing
J85
J86
nc...
I
cale Semiconductor,
Frees
TMS, TDI
TDO
TCK
TRST
J87
J88 J89
Figure 38. JTAG Test Access Port Timing Diagram
J91
J90
Figure 39. JTAG TRST Timing Diagram
MOTOROLA MPC866/859 Hardware Specifications 45
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Freescale Semiconductor, Inc.
CPM Electrical Characteristics CPM Electrical Characteristics
TCK
Output
Signals
Output
Signals
Output
Signals
Figure 40. Boundary Scan (JTAG) Timing Diagram
nc...
I
12 CPM Electrical Characteristics
J92 J94
J93
J95 J96
cale Semiconductor,
Frees
This section provides the AC and DC electrical specifications for the communications processor module
(CPM) of the MPC866/859.
12.1 PIP/PIO AC Electrical Specifications
Table 16 shows the PIP/PIO AC timings as shown in Figure 41 through Figure 45.
Table 16. PIP/PIO Timing
All Frequencies
Num Characteristic
Min Max
21 Data-in setup time to STBI low 0 — ns
22 Data-In hold time to STBI high 2.5 – t3
23 STBI pulse width 1.5 — clk
24 STBO pulse width 1 clk – 5ns — ns
25 Data-out setup time to STBO low 2 — clk
26 Data-out hold time from STBO high 5 — clk
27 STBI low to STBO low (Rx interlock) — 2 clk
28 STBI low to STBO high (Tx interlock) 2 — clk
1
— clk
Unit
29 Data-in setup time to clock high 15 — ns
30 Data-in hold time from clock high 7.5 — ns
31 Clock low to data-out valid (CPU writes data, control, or direction) — 25 ns
1
t3 = Specification 23
46 MPC866/859 Hardware Specifications MOTOROLA
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DATA-IN
Freescale Semiconductor, Inc.
CPM Electrical Characteristics
21
23
STBI
27
24
STBO
Figure 41. PIP Rx (Interlock Mode) Timing Diagram
nc...
I
DATA-OUT
25
24
STBO
(Output)
28
23
STBI
(Input)
Figure 42. PIP Tx (Interlock Mode) Timing Diagram
DATA-IN
cale Semiconductor,
23
22
2221
26
Frees
STBI
(Input)
24
STBO
(Output)
Figure 43. PIP Rx (Pulse Mode) Timing Diagram
MOTOROLA MPC866/859 Hardware Specifications 47
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Freescale Semiconductor, Inc.
CPM Electrical Characteristics CPM Electrical Characteristics
DATA-OUT
STBO
(Output)
STBI
(Input)
Figure 44. PIP TX (Pulse Mode) Timing Diagram
2625
24
23
nc...
I
cale Semiconductor,
Frees
CLKO
29
30
DATA-IN
31
DATA-OUT
Figure 45. Parallel I/O Data-In/Data-Out Timing Diagram
12.2 Port C Interrupt AC Electrical Specifications
Table 17 shows timings for port C interrupts.
Table 17. Port C Interrupt Timing
33.34 MHz
Num Characteristic
Min Max
Unit
35 Port C interrupt pulse width low (edge-triggered mode) 55 — ns
36 Port C interrupt minimum time between active edges 55 — ns
48 MPC866/859 Hardware Specifications MOTOROLA
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Figure 46 shows the port C interrupt detection timing.
Por t C
(Input)
Figure 46. Port C Interrupt Detection Timing
CPM Electrical Characteristics
36
35
12.3 IDMA Controller AC Electrical Specifications
Table 18 shows the IDMA controller timings as shown in Figure 47 through Figure 50.
Table 18. IDMA Controller Timing
nc...
I
cale Semiconductor,
Frees
All Frequencies
Num Characteristic
Min Max
40 DREQ
41 DREQ hold time from clock high 3 — ns
42 SDACK assertion delay from clock high — 12 ns
43 SDACK negation delay from clock low — 12 ns
44 SDACK negation delay from TA low — 20 ns
45 SDACK negation delay from clock high — 15 ns
46 TA assertion to falling edge of the clock setup time (applies to external TA)7 —ns
(Output)
setup time to clock high 7 — ns
CLKO
41
40
DREQ
(Input)
Figure 47. IDMA External Requests Timing Diagram
Unit
MOTOROLA MPC866/859 Hardware Specifications 49
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Freescale Semiconductor, Inc.
CPM Electrical Characteristics CPM Electrical Characteristics
CLKO
(Output)
TS
(Output)
R/W
(Output)
nc...
I
cale Semiconductor,
Frees
42
DATA
A
T
(Input)
ACK
SD
Figure 48. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA
CLKO
(Output)
TS
(Output)
R/W
(Output)
42 44
DATA
43
46
A
T
(Output)
ACK
SD
Figure 49. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA
50 MPC866/859 Hardware Specifications MOTOROLA
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Freescale Semiconductor, Inc.
CLKO
(Output)
TS
(Output)
R/W
(Output)
DATA
A
nc...
I
T
(Output)
CPM Electrical Characteristics
42 45
cale Semiconductor,
Frees
ACK
SD
Figure 50. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA
12.4 Baud Rate Generator AC Electrical Specifications
Table 19 shows the baud rate generator timings as shown in Figure 51.
Table 19. Baud Rate Generator Timing
All Frequencies
Num Characteristic
Min Max
50 BRGO rise and fall time — 10 ns
51 BRGO duty cycle 40 60 %
52 BRGO cycle 40 — ns
50
BRGOX
50
Unit
51
52
Figure 51. Baud Rate Generator Timing Diagram
MOTOROLA MPC866/859 Hardware Specifications 51
51
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Freescale Semiconductor, Inc.
CPM Electrical Characteristics CPM Electrical Characteristics
12.5 Timer AC Electrical Specifications
Table 20 shows the general-purpose timer timings as shown in Figure 52.
Num Characteristic
Table 20. Timer Timing
All Frequencies
Unit
Min Max
nc...
I
cale Semiconductor,
Frees
61 TIN/TGA
62 TIN/TGATE low time 1 — clk
63 TIN/TGATE high time 2 — clk
64 TIN/TGATE cycle time 3 — clk
65 CLKO low to TOUT valid 3 25 ns
CLKO
TIN/TGA
TE
(Input)
TOUT
(Output)
TE rise and fall time 10 — ns
60
626361
61
65
Figure 52. CPM General-Purpose Timers Timing Diagram
64
12.6 Serial Interface AC Electrical Specifications
Table 21 shows the serial interface timings as shown in Figure 53 through Figure 57.
Num Characteristic
70 L1RCLK, L1TCLK frequency (DSC = 0)
71 L1RCLK, L1TCLK width low (DSC = 0)
71a L1RCLK, L1TCLK width high (DSC = 0)
Table 21. SI Timing
All Frequencies
Min Max
1, 2
— SYNCCLK/2.5 MHz
2
3
P + 10 — ns
P + 10 — ns
Unit
72 L1TXD, L1ST(1–4), L1RQ, L1CLKO rise/fall time — 15.00 ns
73 L1RSYNC, L1TSYNC valid to L1CLK edge (SYNC
setup time)
74 L1CLK edge to L1RSYNC, L1TSYNC, invalid
(SYNC hold time)
52 MPC866/859 Hardware Specifications MOTOROLA
20.00 — ns
35.00 — ns
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Freescale Semiconductor, Inc.
Num Characteristic
75 L1RSYNC, L1TSYNC rise/fall time — 15.00 ns
76 L1RXD valid to L1CLK edge (L1RXD setup time) 17.00 — ns
77 L1CLK edge to L1RXD invalid (L1RXD hold time) 13.00 — ns
78 L1CLK edge to L1ST(1–4) valid
78A L1SYNC valid to L1ST(1–4) valid 10.00 45.00 ns
79 L1CLK edge to L1ST(1–4) invalid 10.00 45.00 ns
80 L1CLK edge to L1TXD valid 10.00 55.00 ns
80A L1TSYNC valid to L1TXD valid
Table 21. SI Timing (continued)
Min Max
4
4
10.00 45.00 ns
10.00 55.00 ns
CPM Electrical Characteristics
All Frequencies
Unit
nc...
I
cale Semiconductor,
Frees
81 L1CLK edge to L1TXD high impedance 0.00 42.00 ns
82 L1RCLK, L1TCLK frequency (DSC =1) — 16.00 or SYNCCLK/2 MHz
83 L1RCLK, L1TCLK width low (DSC =1) P + 10 — ns
83a L1RCLK, L1TCLK width high (DSC = 1)
84 L1CLK edge to L1CLKO valid (DSC = 1) — 30.00 ns
85 L1RQ valid before falling edge of L1TSYNC
86 L1GR setup time
87 L1GR hold time 42.00 — ns
88 L1CLK edge to L1SYNC valid (FSD = 00) CNT =
0000, BYT = 0, DSC = 0)
1
The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
2
These specs are valid for IDL mode only.
3
Where P = 1/CLKOUT. Thus, for a 25-MHz CLKO1 rate, P = 40 ns.
4
These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later.
2
3
4
P + 10 — ns
1.00 — L1TCLK
42.00 — ns
— 0.00 ns
MOTOROLA MPC866/859 Hardware Specifications 53
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Freescale Semiconductor, Inc.
CPM Electrical Characteristics CPM Electrical Characteristics
L1RCLK
(FE=0, CE=0)
(Input)
71
L1RCLK
(FE=1, CE=1)
(Input)
L1RSYNC
(Input)
73
70 71a
72
RFSD=1
75
74 77
nc...
I
cale Semiconductor,
Frees
L1RXD
(Input)
L1ST(4-1)
(Output)
BIT0
76
78
Figure 53. SI Receive Timing Diagram with Normal Clocking (DSC = 0)
79
54 MPC866/859 Hardware Specifications MOTOROLA
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L1RCLK
(FE=1, CE=1)
(Input)
L1RCLK
(FE=0, CE=0)
(Input)
L1RSYNC
(Input)
82
Freescale Semiconductor, Inc.
75
73
74 77
72
RFSD=1
83a
CPM Electrical Characteristics
nc...
I
cale Semiconductor,
Frees
L1RXD
(Input)
L1ST(4-1)
(Output)
L1CLKO
(Output)
BIT0
76
78
84
Figure 54. SI Receive Timing with Double-Speed Clocking (DSC = 1)
79
MOTOROLA MPC866/859 Hardware Specifications 55
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Freescale Semiconductor, Inc.
CPM Electrical Characteristics CPM Electrical Characteristics
L1TCLK
(FE=0, CE=0)
(Input)
71 70
L1TCLK
(FE=1, CE=1)
(Input)
L1TSYNC
(Input)
73
80a
72
TFSD=0
75
74
81
nc...
I
cale Semiconductor,
Frees
L1TXD
(Output)
L1ST(4-1)
(Output)
BIT0
80
78
Figure 55. SI Transmit Timing Diagram (DSC = 0)
79
56 MPC866/859 Hardware Specifications MOTOROLA
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L1RCLK
(FE=0, CE=0)
(Input)
L1RCLK
(FE=1, CE=1)
(Input)
L1RSYNC
(Input)
Freescale Semiconductor, Inc.
75
73
74
72
82
TFSD=0
CPM Electrical Characteristics
83a
81
nc...
I
cale Semiconductor,
Frees
L1TXD
(Output)
L1ST(4-1)
(Output)
L1CLKO
(Output)
BIT0
80
78a
78
84
Figure 56. SI Transmit Timing with Double Speed Clocking (DSC = 1)
79
MOTOROLA MPC866/859 Hardware Specifications 57
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Freescale Semiconductor, Inc.
CPM Electrical Characteristics CPM Electrical Characteristics
nc...
I
cale Semiconductor,
Frees
12345678910 11 12 13 14 15 16 17 18 19 20
73
71
71
80
74
81
78
87
72
76
B17 B16 B15 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 M
B17 B16 B14 B13 B12 B11 B10 D1 A B27 B26 B25 B24 B23 B22 B21 B20 D2 MB15
77
85
86
(Input)
L1RCLK
58 MPC866/859 Hardware Specifications MOTOROLA
(Input)
L1RSYNC
L1TXD
(Output)
Figure 57. IDL Timing
(Input)
L1RXD
(Output)
L1ST(4-1)
L1RQ
(Output)
L1GR
(Input)
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Freescale Semiconductor, Inc.
CPM Electrical Characteristics
12.7 SCC in NMSI Mode Electrical Specifications
Table 22 shows the NMSI external clock timings.
Table 22. NMSI External Clock Timings
All Frequencies
Num Characteristic
Min Max
100 RCLK1 and TCLK1 width high
101 RCLK1 and TCLK1 width low 1/SYNCCLK +5 — ns
102 RCLK1 and TCLK1 rise/fall time — 15.00 ns
103 TXD1 active delay (from TCLK1 falling edge) 0.00 50.00 ns
1
1/SYNCCLK — ns
Unit
104 R
105 CTS1 setup time to TCLK1 rising edge 5.00 — ns
nc...
I
106 RXD1 setup time to RCLK1 rising edge 5.00 — ns
107 RXD1 hold time from RCLK1 rising edge
108 CD1
1
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater than or equal to 2.25/1.
2
Also applies to CD and CTS hold time when they are used as an external sync signal.
Table 23 shows the NMSI internal clock timings.
Num Characteristic
100 RCLK1 and TCLK1 frequency
102 RCLK1 and TCLK1 rise/fall time — — ns
cale Semiconductor,
103 TXD1 active delay (from TCLK1 falling edge) 0.00 30.00 ns
104 R
105 CTS1 setup time to TCLK1 rising edge 40.00 — ns
TS1 active/inactive delay (from TCLK1 falling edge) 0.00 50.00 ns
2
setup time to RCLK1 rising edge 5.00 — ns
Table 23. NMSI Internal Clock Timings
1
TS1 active/inactive delay (from TCLK1 falling edge) 0.00 30.00 ns
5.00 — ns
All Frequencies
Unit
Min Max
0.00 SYNCCLK/3 MHz
Frees
106 RXD1 setup time to RCLK1 rising edge 40.00 — ns
107 RXD1 hold time from RCLK1 rising edge
108 CD1
1
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1.
2
Also applies to CD and CTS hold time when they are used as an external sync signals.
MOTOROLA MPC866/859 Hardware Specifications 59
setup time to RCLK1 rising edge 40.00 — ns
2
0.00 — ns
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Freescale Semiconductor, Inc.
CPM Electrical Characteristics CPM Electrical Characteristics
Figure 58 through Figure 60 show the NMSI timings.
RCLK1
102
106
RxD1
(Input)
CD1
(Input)
nc...
I
cale Semiconductor,
CD1
(SYNC Input)
Figure 58. SCC NMSI Receive Timing Diagram
TCLK1
102
TxD1
(Output)
RTS1
(Output)
102 101
107
102 101
103
104
100
100
105
104
108
107
Frees
CTS1
(Input)
107
CTS1
(SYNC Input)
Figure 59. SCC NMSI Transmit Timing Diagram
60 MPC866/859 Hardware Specifications MOTOROLA
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TCLK1
Freescale Semiconductor, Inc.
CPM Electrical Characteristics
102
TxD1
(Output)
RTS1
(Output)
nc...
I
CTS1
(Echo Input)
102 101
100
103
104
105
Figure 60. HDLC Bus Timing Diagram
104107
12.8 Ethernet Electrical Specifications
Table 24 shows the Ethernet timings as shown in Figure 61 through Figure 65.
Table 24. Ethernet Timing
All Frequencies
Num Characteristic
Min Max
120 CLSN width high 40 — ns
121 RCLK1 rise/fall time — 15 ns
122 RCLK1 width low 40 — ns
cale Semiconductor,
123 RCLK1 clock period
124 RXD1 setup time 20 — ns
125 RXD1 hold time 5 — ns
1
80 120 ns
Unit
Frees
126 RENA active delay (from RCLK1 rising edge of the last data bit) 10 — ns
127 RENA width low 100 — ns
128 TCLK1 rise/fall time — 15 ns
129 TCLK1 width low 40 — ns
130 TCLK1 clock period
131 TXD1 active delay (from TCLK1 rising edge) — 50 ns
132 TXD1 inactive delay (from TCLK1 rising edge) 6.5 50 ns
133 TENA active delay (from TCLK1 rising edge) 10 50 ns
134 TENA inactive delay (from TCLK1 rising edge) 10 50 ns
MOTOROLA MPC866/859 Hardware Specifications 61
1
99 101 ns
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Freescale Semiconductor, Inc.
CPM Electrical Characteristics CPM Electrical Characteristics
Num Characteristic
135 RSTRT active delay (from TCLK1 falling edge) 10 50 ns
136 RSTRT inactive delay (from TCLK1 falling edge) 10 50 ns
137 REJECT width low 1 — CLK
138 CLKO1 low to SDACK asserted
139 CLKO1 low to SDACK negated
1
The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2/1.
2
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
Table 24. Ethernet Timing (continued)
2
2
All Frequencies
Min Max
—20ns
—20ns
Unit
nc...
I
cale Semiconductor,
Frees
CLSN(CTS1)
(Input)
RCLK1
RxD1
(Input)
RENA(CD1)
(Input)
120
Figure 61. Ethernet Collision Timing Diagram
121
124 123
125
Figure 62. Ethernet Receive Timing Diagram
121
126
Last Bit
127
62 MPC866/859 Hardware Specifications MOTOROLA
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TCLK1
Freescale Semiconductor, Inc.
CPM Electrical Characteristics
128
131 121
TxD1
(Output)
133 134
TENA(RTS1)
(Input)
RENA(CD1)
Notes:
RxD1
(Input)
Transmit clock invert (TCI) bit in GSMR is set.
1.
If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the
2.
CSL bit is set in the buffer descriptor at the end of the frame transmission.
Figure 63. Ethernet T ransmit Timing Diagram
0
Start Frame Delimiter
1 1 BIT1 BIT2
nc...
I
RCLK1
(Input)
cale Semiconductor,
RSTRT
(Output)
128
132
125
129
136
Frees
Figure 64. CAM Interface Receive Start Timing Diagram
REJECT
137
Figure 65. CAM Interface REJECT
MOTOROLA MPC866/859 Hardware Specifications 63
Timing Diagram
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Freescale Semiconductor, Inc.
CPM Electrical Characteristics CPM Electrical Characteristics
12.9 SMC Transparent AC Electrical Specifications
Table 25 shows the SMC transparent timings as shown in Figure 66.
T able 25. SMC T ransparent Timing
All Frequencies
Num Characteristic
Min Max
150 SMCLK clock period
151 SMCLK width low 50 — ns
151A SMCLK width high 50 — ns
152 SMCLK rise/fall time — 15 ns
153 SMTXD active delay (from SMCLK falling edge) 10 50 ns
154 SMRXD/SMSYNC setup time 20 — ns
nc...
I
155 RXD1/SMSYNC hold time 5 — ns
1
Sync CLK must be at least twice as fast as SMCLK.
1
100 — ns
Unit
cale Semiconductor,
Frees
SMCLK
SMTXD
(Output)
SMSYNC
SMRXD
(Input)
NOTE:
152
This delay is equal to an integer number of character-length clocks.1.
152 151
NOTE 1
154 153
155
154
155
Figure 66. SMC T ransparent Timing Diagram
151A
150
64 MPC866/859 Hardware Specifications MOTOROLA
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Freescale Semiconductor, Inc.
CPM Electrical Characteristics
12.10 SPI Master AC Electrical Specifications
Table 26 shows the SPI master timings as shown in Figure 67 and Figure 68.
Table 26. SPI Master Timing
All Frequencies
Num Characteristic
Min Max
Unit
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I
cale Semiconductor,
Frees
160 MASTER cycle time 4 1024 t
161 MASTER clock (SCK) high or low time 2 512 t
162 MASTER data setup time (inputs) 15 — ns
163 Master data hold time (inputs) 0 — ns
164 Master data valid (after SCK edge) — 10 ns
165 Master data hold time (outputs) 0 — ns
166 Rise time output — 15 ns
167 Fall time output — 15 ns
SPICLK
(CI=0)
(Output)
166167161
161 160
SPICLK
(CI=1)
(Output)
SPIMISO
(Input)
SPIMOSI
(Output)
163
162
msb Data lsb msb
167 166
msb lsb msb
Figure 67. SPI Master (CP = 0) Timing Diagram
166
165 164
Data
167
cyc
cyc
MOTOROLA MPC866/859 Hardware Specifications 65
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CPM Electrical Characteristics CPM Electrical Characteristics
SPICLK
(CI=0)
(Output)
161 160
SPICLK
(CI=1)
(Output)
163
162
166167161
167
166
nc...
I
cale Semiconductor,
Frees
SPIMISO
(Input)
SPIMOSI
(Output)
msb Data lsb msb
165 164
167 166
msb lsb msb
Figure 68. SPI Master (CP = 1) Timing Diagram
Data
12.11 SPI Slave AC Electrical Specifications
Table 27 shows the SPI slave timings as shown in Figure 69 and Figure 70.
Table 27. SPI Slave Timing
All Frequencies
Num Characteristic
Min Max
170 Slave cycle time 2 — t
171 Slave enable lead time 15 — ns
172 Slave enable lag time 15 — ns
173 Slave clock (SPICLK) high or low time 1 — t
174 Slave sequential transfer delay (does not require deselect) 1 — t
175 Slave data setup time (inputs) 20 — ns
176 Slave data hold time (inputs) 20 — ns
Unit
cyc
cyc
cyc
177 Slave access time — 50 ns
66 MPC866/859 Hardware Specifications MOTOROLA
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SPISEL
(Input)
SPICLK
(CI=0)
(Input)
SPICLK
(CI=1)
(Input)
Freescale Semiconductor, Inc.
173 170
177 182
181182173
181
180
CPM Electrical Characteristics
171172
174
178
nc...
I
cale Semiconductor,
Frees
SPIMISO
(Output)
SPIMOSI
(Input)
SPISEL
(Input)
SPICLK
(CI=0)
(Input)
SPICLK
(CI=1)
(Input)
Datamsb lsb msbUndef
175 179
180
181
172
174
181182
181
178
176 182
msb lsb msb
Figure 69. SPI Slave (CP = 0) Timing Diagram
171 170
173
173
177 182
Data
SPIMISO
(Output)
175 179
SPIMOSI
(Input)
MOTOROLA MPC866/859 Hardware Specifications 67
msb
176 182
msb lsb
Figure 70. SPI Slave (CP = 1) Timing Diagram
Data
181
Data
lsbUndef
msb
msb
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Freescale Semiconductor, Inc.
CPM Electrical Characteristics CPM Electrical Characteristics
12.12 I2C AC Electrical Specifications
Table 28 shows the I2C (SCL < 100 kHz) timings.
Table 28. I2C Timing (SCL < 100 kHz)
Num Characteristic
200 SCL clock frequency (slave) 0 100 kHz
200 SCL clock frequency (master)
202 Bus free time between transmissions 4.7 — µs
203 Low period of SCL 4.7 — µs
204 High period of SCL 4.0 — µs
205 Start condition setup time 4.7 — µs
206 Start condition hold time 4.0 — µs
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207 Data hold time 0 — µs
208 Data setup time 250 — ns
209 SDL/SCL rise time — 1 µs
210 SDL/SCL fall time — 300 ns
211 Stop condition setup time 4.7 — µs
1
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.
1
cale Semiconductor,
All Frequencies
Unit
Min Max
1.5 100 kHz
Frees
68 MPC866/859 Hardware Specifications MOTOROLA
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Table 29 shows the I2C (SCL > 100 kHz) timings.
Num Characteristic Expression
200 SCL clock frequency (slave) fSCL 0 BRGCLK/48 Hz
200 SCL clock frequency (master)
202 Bus free time between transmissions — 1/(2.2 * fSCL) — s
203 Low period of SCL — 1/(2.2 * fSCL) — s
204 High period of SCL — 1/(2.2 * fSCL) — s
205 Start condition setup time — 1/(2.2 * fSCL) — s
206 Start condition hold time — 1/(2.2 * fSCL) — s
Table 29. I2C Timing (SCL > 100 kHz)
All Frequencies
Min Max
1
fSCL BRGCLK/16512 BRGCLK/48 Hz
CPM Electrical Characteristics
Unit
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I
cale Semiconductor,
Frees
207 Data hold time — 0 — s
208 Data setup time — 1/(40 * fSCL) — s
209 SDL/SCL rise time — — 1/(10 * fSCL) s
210 SDL/SCL fall time — — 1/(33 * fSCL) s
211 Stop condition setup time — 1/2(2.2 * fSCL) — s
1
SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.
2
Figure 71 shows the I
SDA
205
SCL
C bus timing.
202
206 209 211210
203
207
Figure 71. I2C Bus Timing Diagram
204
208
MOTOROLA MPC866/859 Hardware Specifications 69
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UTOPIA AC Electrical Specifications UTOPIA AC Electrical Specifications
13 UTOPIA AC Electrical Specifications
Table 30 through Table 32 show the AC electrical specifications for the UTOPIA interface.
Table 30. UTOPIA Master (Muxed Mode) Electrical Specifications
Num Signal Characteristic Direction Min Max Unit
U1 UtpClk rise/fall time (Internal clock option) Output — 4 ns
Duty cycle 50 50 %
Frequency — 33 MHz
U2 UTPB, SOC, RxEnb
delay (and PHREQ and PHSEL active delay in MPHY mode)
U3 UTPB, SOC, Rxclav and Txclav setup time Input 4 — ns
U4 UTPB, SOC, Rxclav and Txclav hold time Input 1 — ns
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Num Signal Characteristic Direction Min Max Unit
U1 UtpClk rise/fall time (Internal clock option) Output — 4 ns
Duty cycle 50 50 %
Frequency — 33 MHz
U2 UTPB, SOC, RxEnb
delay (PHREQ and PHSEL active delay in MPHY mode)
U3 UTPB_Aux, SOC_Aux, Rxclav, and Txclav setup time Input 4 — ns
U4 UTPB_Aux, SOC_Aux, Rxclav, and Txclav hold time Input 1 — ns
Num Signal Characteristic Direction Min Max Unit
cale Semiconductor,
U1 UtpClk rise/fall time (external clock option) Input — 4 ns
Duty cycle 40 60 %
Frequency — 33 MHz
Table 31. UTOPIA Master (Split Bus Mode) Electrical Specifications
Table 32. UTOPIA Slave (Split Bus Mode) Electrical Specifications
, TxEnb, RxAddr, and TxAddr-active
, TxEnb, RxAddr and TxAddr active
Output 2 16 ns
Output 2 16 ns
Frees
U2 UTPB, SOC, Rxclav and Txclav active delay Output 2 16 ns
U3 UTPB_AUX, SOC_Aux, RxEnb
setup time
U4 UTPB_AUX, SOC_Aux, RxEnb
hold time
70 MPC866/859 Hardware Specifications MOTOROLA
, TxEnb, RxAddr, and TxAddr
, TxEnb, RxAddr, and TxAddr
Input 4 — ns
Input 1 — ns
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Y
Freescale Semiconductor, Inc.
Figure 72 shows signal timings during UTOPIA receive operations.
UTOPIA AC Electrical Specifications
U1
UtpClk
U2
PHREQn
U3 U4
3
RxClav
RxEnb
UTPB
SOC
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HighZ at MPHY
Figure 72. UTOPIA Receive Timing
U2
2
4
U1
U3
3
HighZ at MPH
U4
4
Figure 73 shows signal timings during UTOPIA transmit operations.
U1
1
UtpClk
U2
5
PHSELn
U3 U4
TxClav
TxEnb
HighZ at MPHY
U2
2
3
4
cale Semiconductor,
UTPB
SOC
U2
5
U1
High-Z at MPHY
Frees
Figure 73. UTOPIA T ransmit Timing
MOTOROLA MPC866/859 Hardware Specifications 71
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FEC Electrical Characteristics FEC Electrical Characteristics
14 FEC Electrical Characteristics
This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the
timing specifications for the MII signals are independent of system clock frequency (part speed
designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 or 3.3
V.
14.1 MII Receive Signal Timing (MII_RXD [3:0], MII_RX_DV,
MII_RX_ER, MII_RX_CLK)
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz + 1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_RX_CLK frequency – 1%. Table 33 shows the timings for MII receive signal.
Table 33. MII Receive Signal Timing
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cale Semiconductor,
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Num Characteristic Min Max Unit
M1 MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup 5 — ns
M2 MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold 5 — ns
M3 MII_RX_CLK pulse width high 35% 65% MII_RX_CLK period
M4 MII_RX_CLK pulse width low 35% 65% MII_RX_CLK period
Figure 74 shows the timings for MII receive signal.
M3
MII_RX_CLK (input)
M4
MII_RXD[3:0] (inputs)
MII_RX_DV
MII_RX_ER
M1
M2
Figure 74. MII Receive Signal Timing Diagram
14.2 MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN,
MII_TX_ER, MII_TX_CLK)
The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. There is
no minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_TX_CLK frequency - 1%.
72 MPC866/859 Hardware Specifications MOTOROLA
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Table 34 shows information on the MII transmit signal timing.
Num Characteristic Min Max Unit
FEC Electrical Characteristics
Table 34. MII Transmit Signal Timing
M5 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER
invalid
M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER
valid
M7 MII_TX_CLK pulse width high 35% 65% MII_TX_CLK period
M8 MII_TX_CLK pulse width low 35% 65% MII_TX_CLK period
Figure 75 shows the MII transmit signal timing diagram.
M7
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MII_TX_CLK (input)
M5
MII_TXD[3:0] (outputs)
MII_TX_EN
MII_TX_ER
M6
Figure 75. MII Transmit Signal Timing Diagram
14.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 35 shows the timing for on the MII async inputs signal.
cale Semiconductor,
Num Characteristic Min Max Unit
Table 35. MII Async Inputs Signal Timing
5— ns
—25 —
M8
Frees
M9 MII_CRS, MII_COL minimum pulse width 1.5 — MII_TX_CLK period
Figure 76 shows the MII asynchronous inputs signal timing diagram.
MII_CRS, MII_COL
M9
Figure 76. MII Async Inputs Timing Diagram
MOTOROLA MPC866/859 Hardware Specifications 73
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FEC Electrical Characteristics FEC Electrical Characteristics
14.4 MII Serial Management Channel Timing (MII_MDIO,
MII_MDC)
T able 36 shows the timing for the MII serial management channel signal. The FEC functions correctly with
a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.
Table 36. MII Serial Management Channel Timing
Num Characteristic Min Max Unit
M10 MII_MDC falling edge to MII_MDIO output invalid (minimum
propagation delay)
M11 MII_MDC falling edge to MII_MDIO output valid (maximum
propagation delay)
M12 MII_MDIO (input) to MII_MDC rising edge setup 10 — ns
M13 MII_MDIO (input) to MII_MDC rising edge hold 0 — ns
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cale Semiconductor,
M14 MII_MDC pulse width high 40% 60% MII_MDC period
M15 MII_MDC pulse width low 40% 60% MII_MDC period
Figure 77 shows the MII serial management channel timing diagram.
M14
MM15
MII_MDC (output)
M10
MII_MDIO (output)
M11
MII_MDIO (input)
0— ns
—25 ns
Frees
M12
Figure 77. MII Serial Management Channel Timing Diagram
74 MPC866/859 Hardware Specifications MOTOROLA
M13
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Mechanical Data and Ordering Information
15 Mechanical Data and Ordering Information
Table 37 shows information on the MPC866/859 derivative devices.
Table 37. MPC866/859 Derivatives
Number
Device
MPC866T 4 10/100 Mbps Yes Yes 4 Kbyte 4 Kbytes
MPC866P 4 10/100 Mbps Yes Yes 16 Kbyte 8 Kbytes
MPC859T 1 (SCC1) 10/100 Mbps Yes Yes 4 Kbyte 4 Kbytes
MPC859DSL 1 (SCC1) 10/100 Mbps No Up to 4 addresses 4 Kbyte 4 Kbytes
1
Serial communications controller (SCC).
nc...
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cale Semiconductor,
Table 38 identifies the packages and operating frequencies orderable for the MPC866/859 derivative
devices.
Package Type Temperature (Tj) Frequency (MHz) Order Number
Plastic ball grid array
(ZP suffix)
Plastic ball grid array
(CZP suffix)
1
Additional extended temperature devices can be made available at 50, 66, 80, and100MHz.
of
SCCs
1
Ethernet
Support
Table 38. MPC866/859 Package/Frequency Orderable
Multi-Channel
HDLC Support
0° to 95°C 50 MPC859DSLZP50
–40° to 100°C TBD
ATM Support
Instruction Data
66 MPC859DSLZP66
100 MPC866PZP100
133 MPC866PZP133
1
Cache Size
MPC866TZP100
MPC859PZP100
MPC859TZP100
MPC866TZP133
MPC859PZP133
MPC859TZP133
TBD
Frees
MOTOROLA MPC866/859 Hardware Specifications 75
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Mechanical Data and Ordering Information Mechanical Data and Ordering Information
15.1 Pin Assignments
Figure 78 shows the top view pinout of the PBGA package. For additional information, see the MPC866
PowerQUICC Family User’s Manual.
NOTE: This is the top view of the device.
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cale Semiconductor,
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PD10 PD8
PD14
PD13 PD6 IRQ0
PB14 PD4 IRQ1
PC5 PD11 VDDH D12 D17 D9 D15 D22 D25 D31 IPA6 IPA0 IPA7 N/CIPA1PC4 PD7 VDDSYNPA 1
PA2 PD12
PB17 VDDL GND
PA5 PB16
PC8 PC7
PA 7
PC9 PB20 AS
PC10
PA9 PB21 GND IPB6 ALEABADDR30PB23 IRQ4
PB24 PB25 IPB1 IPB2IPB5PA10 ALEBPC11
M_MDIO
TMS PA11 IRQ6
PC12 VDDL
PC13 PB29
PC14 PC15 N/C N/C A15 A19 A25 A18 BSA0
PA15 A3 A12 A16 A20 A24 A26 TSIZ1 BSA1
A1 A6 A13 A17 A21 A23 A22 TSIZ0 BSA3
A2 A7 A14 A27 A29 A30 A28 A31 VDDL BSA2
18 16 141312111098765 32417 15 119
PD3 IRQ7 D0 D4 D1 D2 D3 D5 VDDL D6 D7 D29 CLKOUT IPA3DP2
D13 D27 D10 D14 D18 D20 D24 D28 DP1 DP0 N/CDP3PD9 M_Tx_EN
D8 D23 D11 D16 D19 D21 D26 D30 IPA5 IPA2 N/CIPA4PD15 PD5 VSSSYNPA 0
PB15
PB18 EXTALPB19
PA 6
TCK IRQ2 IPB0M_COLTDI IPB7VDDL
VDDH
GND GND
VDDH VDDH
GPLA0 N/C CS6 GPLA5 BDIPCS2PA14 A8 TEAPB28
WE0 GPLA1 GPLA3 CS0 TACS7PB31 A9 GPLA4PB30
M_CRS WE2 GPLA2 CE1A WRCS5A4 A10 GPLB4A0
VDDH
WAIT_B
RSTCONF
VDDLPA3 GND XTALPA 4
HRESET
MODCK2
WE1 WE3 CE2A CS1CS4A5 A11
WAIT_A
TEXP
BADDR28
TS
BI
PORESET
SRESET
EXTCLK
BADDR29
OP1OP0PA 8 MODCK1PB22
IPB4BRTDO IPB3TRST
IRQ3VDDLPA12 BURSTPB26
BGCS3PA13 BBPB27
VSSSYN1
VDDLPC6
VDDL
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Figure 78. Pinout of the PBGA Package
76 MPC866/859 Hardware Specifications MOTOROLA
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Mechanical Data and Ordering Information
Table 39 contains a list of the MPC866 input and output signals and shows multiplexing and pin
assignments.
Table 39. Pin Assignments
Name Pin Number Type
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cale Semiconductor,
Frees
A[0:31] B19, B18, A18, C16, B17, A17, B16, A16, D15, C15, B15, A15,
C14, B14, A14, D12, C13, B13, D9, D11, C12, B12, B10, B11, C11,
D10, C10, A13, A10, A12, A11, A9
TSIZ0
REG
TSIZ1 C9 Bidirectional
RD/WR
B
BDIP
GPL_B5
TS
T
TEA
BI E3 Bidirectional
IRQ2
RSV
IRQ4
KR
RETRY
SPKROUT
CR
IRQ3
D[0:31] W14, W12, W11, W10, W13, W9, W7, W6, U13, T11, V11, U11,
B2 Bidirectional
URST F1 Bidirectional
A C2 Bidirectional
B9 Bidirectional
D2 Output
F3 Bidirectional
D1 Open-drain
H3 Bidirectional
K1 Bidirectional
F2 Input
T13, V13, V10, T10, U10, T12, V9, U9, V8, U8, T9, U12, V7, T8, U7,
V12, V6, W5, U6, T7
Bidirectional
Three-state
Three-state
Three-state
Three-state
Three-state
Active Pull-up
Active Pull-up
Active Pull-up
Three-state
Three-state
Bidirectional
Three-state
DP0
IRQ3
DP1
IRQ4
DP2
IRQ5
DP3
IRQ6
BR
MOTOROLA MPC866/859 Hardware Specifications 77
V3 Bidirectional
Three-state
V5 Bidirectional
Three-state
W4 Bidirectional
Three-state
V4 Bidirectional
Three-state
G4 Bidirectional
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Mechanical Data and Ordering Information Mechanical Data and Ordering Information
Name Pin Number Type
BG E2 Bidirectional
BB E1 Bidirectional
Table 39. Pin Assignments (continued)
Active Pull-up
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cale Semiconductor,
Frees
FRZ
IRQ6
IRQ0
IRQ1 U14 Input
M_TX_CLK
IRQ7
CS
[0:5] C3, A2, D4, E4, A4, B4 Output
CS6
CE1_B
CS7
CE2_B
WE0
BS_B0
IORD
WE1
BS_B1
IOWR
WE2
BS_B2
PCOE
WE3
BS_B3
PCWE
BS_A
[0:3] D8, C8, A7, B8 Output
GPL_A0
GPL_B0
OE
GPL_A1
GPL_B1
G3 Bidirectional
V14 Input
W15 Input
D5 Output
C4 Output
C7 Output
A6 Output
B6 Output
A5 Output
D7 Output
C6 Output
[2:3]
GPL_A
GPL_B
[2:3]
CS
[2–3]
UPWAITA
GPL_A4
UPWAITB
GPL_B4
GPL_A5
PORESET R2 Input
78 MPC866/859 Hardware Specifications MOTOROLA
B5, C5 Output
C1 Bidirectional
B1 Bidirectional
D3 Output
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Name Pin Number Type
RSTCONF P3 Input
HRESET N4 Open-drain
SRESET P2 Open-drain
XTAL P1 Analog Output
EXTAL N1 Analog Input (3.3V only)
CLKOUT W3 Output
EXTCLK N2 Input (3.3V only)
TEXP N3 Output
Mechanical Data and Ordering Information
Table 39. Pin Assignments (continued)
nc...
I
cale Semiconductor,
Frees
ALE_A
MII-TXD1
CE1_A
MII-TXD2
CE2_A
MII-TXD3
WAIT_A
SOC_Split
W
AIT_B R4 Input
IP_A0
UTPB_Split0
MII-RXD3
IP_A1
UTPB_Split1
MII-RXD2
IP_A2
IOIS16_A
UTPB_Split2
MII-RXD1
IP_A3
UTPB_Split3
MII-RXD0
IP_A4
UTPB_Split4
MII-RXCLK
2
2
2
2
2
2
K2 Output
B3 Output
A3 Output
R3 Input
T5 Input
T4 Input
U3 Input
W2 Input
U4 Input
IP_A5
UTPB_Split5
MII-RXERR
IP_A6
UTPB_Split6
MII-TXERR
IP_A7
UTPB_Split7
MII-RXDV
MOTOROLA MPC866/859 Hardware Specifications 79
2
2
2
U5 Input
T6 Input
T3 Input
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Mechanical Data and Ordering Information Mechanical Data and Ordering Information
Name Pin Number Type
Table 39. Pin Assignments (continued)
nc...
I
cale Semiconductor,
Frees
ALE_B
DSCK/AT1
IP_B[0:1]
IWP[0:1]
VFLS[0:1]
IP_B2
IOIS16_B
AT 2
IP_B3
IWP2
VF2
IP_B4
LWP0
VF0
IP_B5
LWP1
VF1
IP_B6
DSDI
AT 0
IP_B7
PTR
AT 3
OP0
MII-TXD0
UtpClk_Split
OP1 L2 Output
OP2
MODCK1
STS
OP3
MODCK2
DSDO
BADDR30
REG
2
J1 Bidirectional
Three-state
H2, J3 Bidirectional
J2 Bidirectional
Three-state
G1 Bidirectional
G2 Bidirectional
J4 Bidirectional
K3 Bidirectional
Three-state
H1 Bidirectional
Three-state
L4 Bidirectional
L1 Bidirectional
M4 Bidirectional
K4 Output
BADDR[28:29] M3, M2 Output
AS
PA15
RXD1
RXD4
PA14
TXD1
TXD4
80 MPC866/859 Hardware Specifications MOTOROLA
L3 Input
C18 Bidirectional
D17 Bidirectional
(Optional: Open-drain)
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Name Pin Number Type
Mechanical Data and Ordering Information
Table 39. Pin Assignments (continued)
nc...
I
cale Semiconductor,
Frees
PA13
RXD2
PA12
TXD2
PA11
L1TXDB
RXD3
PA10
L1RXDB
TXD3
PA 9
L1TXDA
RXD4
PA 8
L1RXDA
TXD4
PA 7
CLK1
L1RCLKA
BRGO1
TIN1
PA 6
CLK2
T
OUT1
PA 5
CLK3
L1TCLKA
BRGO2
TIN2
PA 4
CLK4
T
OUT2
PA 3
CLK5
BRGO3
TIN3
E17 Bidirectional
F17 Bidirectional
(Optional: Open-drain)
G16 Bidirectional
(Optional: Open-drain)
J17 Bidirectional
(Optional: Open-drain)
K18 Bidirectional
(Optional: Open-drain)
L17 Bidirectional
(Optional: Open-drain)
M19 Bidirectional
M17 Bidirectional
N18 Bidirectional
P19 Bidirectional
P17 Bidirectional
PA 2
CLK6
T
OUT3
L1RCLKB
PA 1
CLK7
BRGO4
TIN4
MOTOROLA MPC866/859 Hardware Specifications 81
R18 Bidirectional
T19 Bidirectional
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Mechanical Data and Ordering Information Mechanical Data and Ordering Information
Name Pin Number Type
Table 39. Pin Assignments (continued)
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PA 0
CLK8
T
OUT4
L1TCLKB
PB31
SPISEL
REJECT1
PB30
SPICLK
RSTR
T2
PB29
SPIMOSI
PB28
SPIMISO
BRGO4
PB27
I2CSDA
BRGO1
PB26
I2CSCL
BRGO2
PB25
RXADDR3
SMTXD1
PB24
TXADDR3
SMRXD1
PB23
TXADDR2
SDACK1
SMSYN1
PB22
TXADDR4
SDACK2
SMSYN2
U19 Bidirectional
C17 Bidirectional
(Optional: Open-drain)
C19 Bidirectional
(Optional: Open-drain)
E16 Bidirectional
(Optional: Open-drain)
D19 Bidirectional
(Optional: Open-drain)
E19 Bidirectional
(Optional: Open-drain)
F19 Bidirectional
(Optional: Open-drain)
2
2
2
2
J16 Bidirectional
(Optional: Open-drain)
J18 Bidirectional
(Optional: Open-drain)
K17 Bidirectional
(Optional: Open-drain)
L19 Bidirectional
(Optional: Open-drain)
PB21
SMTXD2
L1CLKOB
PHSEL1
TXADDR1
PB20
SMRXD2
L1CLKOA
PHSEL0
TXADDR0
82 MPC866/859 Hardware Specifications MOTOROLA
1
2
1
2
K16 Bidirectional
(Optional: Open-drain)
L16 Bidirectional
(Optional: Open-drain)
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Name Pin Number Type
Mechanical Data and Ordering Information
Table 39. Pin Assignments (continued)
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PB19
R
TS1
L1ST1
PB18
RXADDR4
RTS2
L1ST2
PB17
L1RQb
L1ST3
R
TS3
PHREQ1
RXADDR1
PB16
L1RQa
L1ST4
R
TS4
PHREQ0
RXADDR0
PB15
BRGO3
TxClav
RxClav
PB14
RXADDR2
RSTRT1
PC15
DREQ0
RTS1
L1ST1
RxClav
TxClav
PC14
DREQ1
RTS2
L1ST2
PC13
L1RQb
L1ST3
RTS3
N19 Bidirectional
(Optional: Open-drain)
2
1
2
1
2
2
N17 Bidirectional
(Optional: Open-drain)
P18 Bidirectional
(Optional: Open-drain)
N16 Bidirectional
(Optional: Open-drain)
R17 Bidirectional
U18 Bidirectional
D16 Bidirectional
D18 Bidirectional
E18 Bidirectional
PC12
L1RQa
L1ST4
RTS4
PC11
CTS1
MOTOROLA MPC866/859 Hardware Specifications 83
F18 Bidirectional
J19 Bidirectional
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Mechanical Data and Ordering Information Mechanical Data and Ordering Information
Name Pin Number Type
Table 39. Pin Assignments (continued)
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PC10
CD1
TGATE1
PC9
CTS2
PC8
CD2
TGATE2
PC7
CTS3
L1TSYNCB
SD
ACK2
PC6
CD3
L1RSYNCB
PC5
CTS4
L1TSYNCA
SDACK1
PC4
CD4
L1RSYNCA
PD15
L1TSYNCA
MII-RXD3
UTPB0
PD14
L1RSYNCA
MII-RXD2
UTPB1
PD13
L1TSYNCB
MII-RXD1
UTPB2
PD12
L1RSYNCB
MII-MDC
UTPB3
K19 Bidirectional
L18 Bidirectional
M18 Bidirectional
M16 Bidirectional
R19 Bidirectional
T18 Bidirectional
T17 Bidirectional
U17 Bidirectional
V19 Bidirectional
V18 Bidirectional
R16 Bidirectional
PD11
RXD3
MII-TXERR
RXENB
PD10
TXD3
MII-RXD0
TXENB
84 MPC866/859 Hardware Specifications MOTOROLA
T16 Bidirectional
W18 Bidirectional
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Name Pin Number Type
Mechanical Data and Ordering Information
Table 39. Pin Assignments (continued)
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PD9
RXD4
MII-TXD0
UTPCLK
PD8
TXD4
MII-MDC
MII-RXCLK
PD7
R
TS3
MII-RXERR
UTPB4
PD6
R
TS4
MII-RXDV
UTPB5
PD5
REJECT2
MII-TXD3
UTPB6
PD4
REJECT3
MII-TXD2
UTPB7
PD3
REJECT4
MII-TXD1
SOC
TMS G18 Input
TDI
DSDI
TCK
DSCK
TRST
TDO
DSDO
V17 Bidirectional
W17 Bidirectional
T15 Bidirectional
V16 Bidirectional
U15 Bidirectional
U16 Bidirectional
W16 Bidirectional
H17 Input
H16 Input
G19 Input
G17 Output
MII_CRS B7 Input
MII_MDIO H18 Bidirectional
MII_TXEN V15 Output
MII_COL H4 Input
VSSSYN1 V1 PLL analog VDD and
GND
VSSSYN U1 Power
MOTOROLA MPC866/859 Hardware Specifications 85
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Mechanical Data and Ordering Information Mechanical Data and Ordering Information
Name Pin Number Type
VDDSYN T1 Power
Table 39. Pin Assignments (continued)
GND F6, F7, F8, F9, F10, F11, F12, F13, F14, G6, G7, G8, G9, G10,
G11, G12, G13, G14, H6, H7, H8, H9, H10, H11, H12, H13, H14,
J6, J7, J8, J9, J10, J11, J12, J13, J14, K6, K7, K8, K9, K10, K11,
K12, K13, K14, L6, L7, L8, L9, L10, L11, L12, L13, L14, M6, M7,
M8, M9, M10, M11, M12, M13, M14, N6, N7, N8, N9, N10, N11,
N12, N13, N14, P6, P7, P8, P9, P10, P11, P12, P13, P14
VDDL A8, M1, W8, H19, F4, F16, P4, P16, R1 Power
VDDH E5, E6, E7, E8, E9, E10, E11, E12, E13, E14, E15, F5, F15, G5,
G15, H5, H15, J5, J15, K5, K15, L5, L15, M5, M15, N5, N15, P5,
P15, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, T14
N/C D6, D13, D14, U2, V2, T2 No-connect
1
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Classic SAR mode only
2
ESAR mode only
Power
Power
15.2 Mechanical Dimensions of the PBGA Package
For more information on the printed-circuit board layout of the PBGA package, including thermal via
design and suggested pad layout, please refer to Plastic Ball Grid Array Application Note (order number:
AN1231/D) available from your local Motorola sales of fice. Figure 79 shows the mechanical dimensions of
the PBGA package.
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86 MPC866/859 Hardware Specifications MOTOROLA
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Mechanical Data and Ordering Information
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Note: Solder sphere composition for MPC866XZP, MPC859PZP, MPC859DSLZP, and MPC859TZP
is 62%Sn 36%Pb 2%Ag
Figure 79. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package
MOTOROLA MPC866/859 Hardware Specifications 87
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Document Revision History Document Revision History
16 Document Revision History
Table 40 lists significant changes between revisions of this document.
Table 40. Document Revision History
Revision
Number
0 5/2002 Initial revision
1 11/2002 Added the 5-V tolerant pins, new package dimensions, and other changes.
1.1 4/2003 Added the Spec. B1d and changed spec. B1a. Added the Note Solder sphere
1.2 4/2003 Added the MPC859P.
1.3 5/2003 Changed the SPI Master Timing Specs. 162 and 164.
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1.4 7-8/2003 • Added TxClav and RxClav to PB15 and PC15. Changed B28a through B28d and
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Date Substantive Changes
composition for MPC866XZP, MPC859DSLZP, and MPC859TZP is 62%Sn 36%Pb
2%Ag to Figure 15-79.
B29b to show that TRLX can be 0 or 1.
• Added nontechnical reformatting.
Frees
88 MPC866/859 Hardware Specifications MOTOROLA
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Document Revision History
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MOTOROLA MPC866/859 Hardware Specifications 89
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90 MPC866/859 Hardware Specifications MOTOROLA
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Document Revision History
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MOTOROLA MPC866/859 Hardware Specifications 91
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Tai Po Industrial Estate, Tai Po, N.T., Hong Kong
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© Motorola, Inc. 2003
MPC866EC/D
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