This document contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for the MPC866/859 family (refer to Table 1 for
a list of devices). The MPC866P is the superset device of the MPC866/859 family.
This document describes pertinent electrical and physical characteristics of the MPC8245. For
functional characteristics of the processor, refer to the
The MPC866/859 is a derivative of Motorola’s MPC860 PowerQUICC™ family of devices.
It is a versatile single-chip integrated microprocessor and peripheral combination that can be
used in a variety of controller applications and communications and networking systems. The
MPC866/859/859DSL provides enhanced ATM functionality over that of other ATM-enabled
members of the MPC860 family.
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1
Features Features
Table 1 shows the functionality supported by the members of the MPC866/859 family.
Part
MPC866P 16 Kbytes8 KbytesUp to 4 1 4 2
MPC866T 4 Kbytes4 KbytesUp to 4 1 4 2
MPC859P16 Kbytes8 Kbytes1112
MPC859T 4 Kbytes4 Kbytes1112
MPC859DSL4 Kbytes4 Kbytes111
MPC852T
1
On the MPC859DSL, the SCC (SCC1) is for ethernet only. Also, the MPC859DSL does not support the Time Slot
Assigner (TSA).
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2
On the MPC859DSL, the SMC (SMC1) is for UART only.
3
For more details on the MPC852T, please refer to the MPC852T Hardware Specifications.
3
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Instruction Data 10T10/100
4 KBytes4 Kbytes2121
Table 1. MPC866 Family Functionality
CacheEthernet
SCC SMC
2
1
cale Semiconductor,
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2Features
The following list summarizes the key MPC866/859 features:
•Embedded single-issue, 32-bit PowerPC™ core (implementing the PowerPC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see Table 1)
– 16-Kbyte instruction cache (MPC866P and MPC859P) is four-way , set-associativ e with 256
sets; 4-Kbyte instruction cache (MPC866T, MPC859T, and MPC859DSL) is two-way,
set-associative with 128 sets.
– 8-Kbyte data cache (MPC866P and MPC859P) is two-way, set-associative with 256 sets;
4-Kbyte data cache(MPC866T, MPC859T, and MPC859DSL) is two-way, set-associative
with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word)
cache blocks
– Caches are physically addressed, implement a least recently used (LRU) replacement
algorithm, and are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address
spaces and 16 protection groups.
— Advanced on-chip-emulation debug mode
•The MPC866/859 provides enhanced ATM functionality over that of the MPC860SAR. The
MPC866/859 adds major new features available in 'enhanced SAR' (ESAR) mode, including the
following:
— Improved operation, administration, and maintenance (OAM) support
— OAM performance monitoring (PM) support
2
MPC866/859 Hardware Specifications
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— Multiple APC priority levels available to support a range of traffic pace requirements
— ATM port-to-port switching capability without the need for RAM-based microcode
— Simultaneous MII (10/100Base-T) and UTOPIA (half-duplex) capability
— Optional statistical cell counters per PHY
— UTOPIA level 2 compliant interface with added FIFO buffering to reduce the total cell
transmission time. (The earlier UTOPIA level 1 specification is also supported.)
– Multi-PHY support on the MPC866, MPC859P, and MPC859T
– Four PHY support on the MPC866/859
— Parameter RAM for both SPI and I
— Supports full-duplex UTOPIA both master (ATM side) and slave (PHY side) operation using a
'split' bus
— AAL2/VBR functionality is ROM-resident.
•Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
•Thirty-two address lines
•Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS
— Up to 30 wait states programmable per memory bank
— Glueless interface to page mode/EDO/SDRAM, SRAM, EPROMs, flash EPROMs, and other
memory devices.
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbytes–256 Mbytes)
— Selectable write protection
— On-chip bus arbitration logic
•General-purpose timers
— Four 16-bit timers cascadable to be two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
•Fast Ethernet controller (FEC)
— Simultaneous MII (10/100Base-T) and UTOPIA operation when using the UTOPIA
multiplexed bus
•System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Low-power stop mode
— Clock synthesizer
— Decrementer and time base from the PowerPC architecture
— Reset controller
Freescale Semiconductor, Inc.
lines, four WE lines, and one OE line
2
C can be relocated without RAM-based microcode
to support a DRAM bank
Features
MOTOROLA
MPC866/859 Hardware Specifications
3
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Features Features
•Interrupts
•Communications processor module (CPM)
•Four baud rate generators
•MPC866P and MPC866T have four SCCs (serial communication controller); MPC859P,
•Two SMCs (serial management channels) (MPC859DSL has one SMC (SMC1) for UART.)
— IEEE 1149.1 test access port (JTAG)
— Seven external interrupt request (IRQ) lines
— Twelve port pins with interrupt capability
— The MPC866P and MPC866T have 23 internal interrupt sources; the MPC859P, MPC859T,
— Programmable priority between SCCs (MPC866P and MPC866T)
— Programmable highest priority request
— RISC controller
— Communication-specific commands (for example,
— Supports continuous mode transmission and reception on all serial channels
— Up to 8-Kbytes of dual-port RAM
— MPC866P and MPC866T have 16 serial DMA (SDMA) channels; MPC859P, MPC859T , and
— Three parallel I/O registers with open-drain capability
— Independent (can be connected to any SCC or SMC)
— Allow changes during operation
— Autobaud support option
MPC859T, and MPC859DSL have one SCC; and SCC1 on MPC859DSL supports Ethernet only.
— Serial ATM capability on all SCCs
— Optional UTOPIA port on SCC4
— Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC)
— UART
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division multiplexed (TDM) channels
and MPC859DSL have 20 internal interrupt sources.
MODE
, and
MPC859DSL have 10 serial DMA (SDMA) channels.
Freescale Semiconductor, Inc.
RESTART
TRANSMIT
GRACEFUL
)
STOP
TRANSMIT
,
ENTER
HUNT
4
MPC866/859 Hardware Specifications
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•One serial peripheral interface (SPI)
— Supports master and slave modes
— Supports multiple-master operation on the same bus
•One inter-integrated circuit (I
— Supports master and slave modes
— Multiple-master environment support
•Time slot assigner (TSA) (MPC859DSL does not have TSA.)
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame synchronization, and clocking
— Allows dynamic changes
— On MPC866P and MPC866T , can be internally connected to six serial channels (four SCCs and
two SMCs); on MPC859P and MPC859T, can be connected to three serial channels (one SCC
and two SMCs).
•Parallel interface port (PIP)
— Centronics interface support
— Supports fast connection between compatible ports on MPC866/859 or MC68360
•PCMCIA interface
— Master (socket) interface, compliant with PCI Local Bus Specification (Rev 2.1)
— Supports one or two PCMCIA sockets whether ESAR functionality is enabled
— Eight memory or I/O windows supported
•Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two
operate on data.
— Supports conditions: =
— Each watchpoint can generate a breakpoint internally
•Normal high and normal low power modes to conserve power
•1.8 V core and 3.3 V I/O operation with 5-V TTL compatibility; refer to Table 6 for a listing of the
5-V tolerant pins.
•357-pin plastic ball grid array (PBGA) package
•Operation up to 133 MHz
≠
2
< >
Features
C) port
The MPC866/859 is comprised of three modules that each use a 32-bit internal bus: MPC8xx core, system
integration unit (SIU), and communication processor module (CPM). The MPC866P block diagram is
shown in Figure 1 on page 6. The MPC859P/859T/859DSL block diagram is sho wn in Figure 2 on page 7.
MOTOROLA
MPC866/859 Hardware Specifications
5
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Features Features
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Instruction
Bus
Embedded
MPC8xx
Processor
Core
Fast Ethernet
Controller
DMAs
FIFOs
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I
10/100
Base-T
Media Access
Control
MII
Load/Store
Bus
Parallel Interface Port
cale Semiconductor,
16-Kbyte
Instruction Cache
Instruction MMU
32-Entry ITLB
8-Kbyte
Data Cache
Data MMU
32-Entry DTLB
Parallel I/O
4 Baud Rate
Generators
and UTOPIA
SCC1
Figure 1. MPC866P Block Diagram
4
Timers
Timers
SCC3
Time Slot Assigner
Time Slot Assigner
Unified
Bus
Interrupt
Controllers
32-Bit RISC Controller
and Program
ROM
SCC4
Serial Interface
System Interface Unit (SIU)
Internal
Bus Interface
PCMCIA/ATA Interface
8-Kbyte
Dual-Port RAM
Memory Controller
External
Unit
System Functions
Bus Interface
Unit
16 Virtual
Serial
and
2
Independent
DMA
Channels
I2CSPISMC2SMC1SCC2
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6
MPC866/859 Hardware Specifications
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Embedded
MPC8xx
Processor
Core
Fast Ethernet
Controller
DMAs
Freescale Semiconductor, Inc.
Instruction
Bus
Load/Store
Bus
†
4-Kbyte
Instruction Cache
Instruction MMU
32-Entry ITLB
†
4-Kbyte
Data Cache
Data MMU
32-Entry DTLB
Unified
Bus
Maximum Tolerated Ratings
System Interface Unit (SIU)
Memory Controller
Internal
Bus Interface
Unit
System Functions
PCMCIA/ATA Interface
External
Bus Interface
Unit
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FIFOs
10/100
Base-T
Media Access
Control
MII
†
The MPC859P has a 16-Kbyte instruction cache and a 8-Kbyte data cache.
* The MPC859DSL does not contain SMC2 nor the time slot assigner, and provides eight SDMA
controllers.
Parallel I/O
4 Baud Rate
Generators
Parallel Interface Port
and UTOPIA
SCC1
Figure 2. MPC859P/859T/MPC859DSL Block Diagram
4
Timers
Timers
Time Slot Assigner*
Interrupt
Controllers
32-Bit RISC Controller
and Program
Time Slot Assigner
Dual-Port RAM
ROM
Serial Interface
8-Kbyte
10 Virtual
Serial
and
2
Independent
DMA
Channels
I2CSPISMC2*SMC1
3Maximum T olerated Ratings
This section provides the maximum tolerated voltage and temperature ranges for the MPC866/859. Table 2
shows the maximum tolerated ratings, and Table 3 shows the operating temperatures.
Supply voltage
MOTOROLA
Table 2. Maximum Tolerated Ratings
RatingSymbolValueUnit
1
VDDH– 0.3 to 4.0V
VDDL– 0.3 to 2.0V
VDDSYN– 0.3 to 2.0V
Difference between VDDL to VDDSYN100mV
MPC866/859 Hardware Specifications
7
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Maximum Tolerated Ratings Maximum Tolerated Ratings
Table 2. Maximum Tolerated Ratings (continued)
RatingSymbolValueUnit
Input voltage
Storage temperature rangeT
1
The power supply of the device must start its ramp from 0.0 V.
2
Functional operating conditions are provided with the DC electrical specifications in Table 6. Absolute maximum
ratings are stress ratings only; functional operation at the maxima is not guaranteed. Stress beyond those listed may
affect device reliability or cause permanent damage to the device. See page 14.
Caution
power-up and normal operation (that is, if the MPC866/859 is unpowered, a voltage greater than 2.5 V must not be
applied to its inputs).
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Temperature
Temperature (extended)T
1
Minimum temperatures are guaranteed as ambient temperature, T
junction temperature, T
2
: All inputs that tolerate 5 V cannot be more than 2.5 V greater than VDDH. This restriction applies to
RatingSymbolValueUnit
1
(standard)
V
.
j
This device contains circuitry protecting against damage due to high-static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for example, either GND or V
cale Semiconductor,
in
stg
Table 3. Operating Temperatures
T
A(min)
T
j(max)
A(min)
T
j(max)
. Maximum temperatures are guaranteed as
A
GND – 0.3 to VDDHV
–55 to +150˚C
0˚C
95˚C
–40˚C
100˚C
).
DD
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8
MPC866/859 Hardware Specifications
MOTOROLA
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θ
θ
θ
θ
θ
θ
Thermal Characteristics
4Thermal Characteristics
Table 4 shows the thermal characteristics for the MPC866/859.
Table 4. MPC866/859 Thermal Resistance Data
RatingEnvironmentSymbolValueUnit
R
R
JMA
JMA
JMA
Ψ
Ψ
JA
JT
JT
JB
JC
2
3
3
3
37°C/W
23
30
19
13
6
2
2
Junction-to-ambient
Junction-to-board
Junction-to-case
Junction-to-package top
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1
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal
resistance.
2
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
3
Per JEDEC JESD51-6 with the board horizontal.
4
Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
5
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate
method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed
pad packages where the pad would be expected to be soldered, junction-to-case thermal resistance is a simulated
value from the junction to the exposed pad without contact resistance.
6
Thermal characterization parameter indicating the temperature difference between package top and junction
temperature per JEDEC JESD51-2.
1
4
5
6
Natural ConvectionSingle-layer board (1s)R
Four-layer board (2s2p)R
Airflow (200 ft/min)Single-layer board (1s)R
Four-layer board (2s2p)R
Natural Convection
Airflow (200 ft/min)
cale Semiconductor,
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Power Dissipation Power Dissipation
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5Power Dissipation
T able 5 shows po wer dissipation information. The modes are 1:1, where CPU and b us speeds are equal, and
2:1 mode, where CPU frequency is twice the bus speed.
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Table 5. Power Dissipation (P
Die RevisionBus Mode
01:1 50 MHz110140mW
2:166 MHz140160mW
1
Typical power dissipation at VDDL and VDDSYN is at 1.8 V. and VDDH is at 3.3 V.
2
Maximum power dissipation at VDDL and VDDSYN is at 1.9 V, and VDDH is at 3.465 V.
CPU
Frequency
66 MHz150180mW
80 MHz170200mW
100 MHz210250mW
133 MHz260320mW
)
D
Typical
1
Maximum
2
Unit
NOTE
Values in Table 5 represent VDDL based power dissipation and
do not include I/O power dissipation over VDDH. I/O power
dissipation varies widely by application due to buffer current,
depending on external circuitry. The VDDSYN power
dissipation is negligible.
6DC Characteristics
Table 6 shows the DC electrical characteristics for the MPC866/859.
Table 6. DC Electrical Specifications
CharacteristicSymbolMinMaxUnit
Operating voltageVDDL (core)1.71.9V
VDDH (I/O)3.1353.465V
VDDSYN
Difference between
VDDL to VDDSYN
1
1.71.9V
—100mV
Input high voltage (all inputs except EXTAL and
EXTCLK)
10
2
MPC866/859 Hardware Specifications
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VIH2.03.465V
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Thermal Calculation and Measurement
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Table 6. DC Electrical Specifications (continued)
CharacteristicSymbolMinMaxUnit
Input low voltageVILGND0.8V
EXTAL, EXTCLK input high voltageVIHC0.7*(VDDH)VDDHV
Input leakage current, Vin = 5.5V (except TMS, TRST,
DSCK and DSDI pins) for 5 Volts Tolerant Pins
For the following discussions, PD = (VDDL x IDDL) + PI/O, where PI/O is the power dissipation of the I/O
drivers. The VDDSYN power dissipation is negligible.
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Thermal Calculation and Measurement Thermal Calculation and Measurement
7.1Estimation with Junction-to-Ambient Thermal
Resistance
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
= TA +(R
T
J
where:
T
= ambient temperature (ºC)
A
R
θJA
P
= power dissipation in package
D
The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy
estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated
that errors of a factor of two (in the quantity TJ-TA) are possible.
7.2Estimation with Junction-to-Case Thermal Resistance
Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal
resistance and a case-to-ambient thermal resistance:
= R
R
θJA
where:
R
R
R
is device related and cannot be influenced by the user. The user adjusts the thermal environment to
R
θJC
affect the case-to-ambient thermal resistance, R
the device, add a heat sink, change the mounting arrangement on the printed-circuit board, or change the
thermal dissipation on the printed-circuit board surrounding the device. This thermal model is most useful
for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink
to the ambient environment. For most packages, a better model is required.
+ R
θJC
= junction-to-ambient thermal resistance (ºC/W)
θJA
= junction-to-case thermal resistance (ºC/W)
θJC
= case-to-ambient thermal resistance (ºC/W)
θCA
θCA
. For instance, the user can change the airflow around
θCA
7.3Estimation with Junction-to-Board Thermal Resistance
A simple package thermal model that has demonstrated reasonable accuracy (about 20%) is a two-resistor
model consisting of a junction-to-board and a junction-to-case thermal resistance. The junction-to-case
covers the situation where a heat sink is used or where a substantial amount of heat is dissipated from the
top of the package. The junction-to-board thermal resistance describes the thermal performance when most
of the heat is conducted to the printed-circuit board. It has been observed that the thermal performance of
most plastic packages and especially PBGA packages is strongly dependent on the board temperature; see
Figure 3.
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100
90
80
70
60
50
40
30
20
10
Junction Temperature Rise Above
Ambient Divided by Package Power
0
0 2040 6080
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Figure 3. Effect of Board Temperature Rise on Thermal Behavior
Board Temperture Rise Above Ambient Divided by Package
Thermal Calculation and Measurement
Power
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If the board temperature is known, an estimate of the junction temperature in the en vironment can be made
using the following equation:
= TB +(R
T
J
where:
R
T
P
If the board temperature is known and the heat loss from the package case to the air can be ignored,
acceptable predictions of junction temperature can be made. For this method to work, the board and board
mounting must be similar to the test board used to determine the junction-to-board thermal resistance,
namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground
plane.
x PD)
θJB
= junction-to-board thermal resistance (ºC/W)
θJB
= board temperature ºC
B
= power dissipation in package
D
7.4Estimation Using Simulation
When the board temperature is not known, a thermal simulation of the application is needed. The simple
two-resistor model can be used with the thermal simulation of the application [2], or a more accurate and
complex model of the package can be used in the thermal simulation.
MOTOROLAMPC866/859 Hardware Specifications 13
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Power Supply and Power Sequencing Power Supply and Power Sequencing
7.5Experimental Determination
To determine the junction temperature of the device in the application after prototypes are available, the
thermal characterization parameter (Ψ
measurement of the temperature at the top center of the package case using the following equation:
= TT +(ΨJT x PD)
T
J
where:
= thermal characterization parameter
Ψ
JT
T
= thermocouple temperature on top of package
T
= power dissipation in package
P
D
The thermal characterization parameter is measured per JESD51-2 specification published by JEDEC using
a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be
positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over
the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
nc...
I
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
) can be used to determine the junction temperature with a
JT
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7.6References
Semiconductor Equipment and Materials International(415) 964-5111
805 East Middlefield Rd.
Mountain View, CA 94043
MIL-SPEC and EIA/JESD (JEDEC) specifications800-854-7179 or
(Available from Global Engineering Documents)303-397-7956
JEDEC Specifications http://www.jedec.org
1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive
Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.
2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its
Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
8Power Supply and Power Sequencing
This section provides design considerations for the MPC866/859 power supply. The MPC866/859 has a
core voltage (VDDL) and PLL voltage (VDDSYN) that operates at a lower voltage than the I/O voltage
VDDH. The I/O section of the MPC866/859 is supplied with 3.3 V across VDDH and V
Signals PA[0:15], PB[14:31], PC[4:15], PD[3:15], TDI, TDO, TCK, TRST_B, TMS, MII_TXEN, and
MII_MDIO are 5-V tolerant. All inputs cannot be more than 2.5 V greater than VDDH. In addition, 5-V
tolerant pins cannot exceed 5.5 V and the remaining input pins cannot exceed 3.465 V. This restriction
applies to power up/down and normal operation.
(GND).
SS
One consequence of multiple power supplies is that when power is initially applied the voltage rails ramp
up at different rates. The rates depend on the nature of the power supply, the type of load on each power
supply, and the manner in which different voltages are derived. The following restrictions apply:
•VDDL must not exceed VDDH during power up and power down.
•VDDL must not exceed 1.9 V and VDDH must not exceed 3.465 V.
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These cautions are necessary for the long term reliability of the part. If they are violated, the electrostatic
discharge (ESD) protection diodes are forward-biased and excessi v e current can flo w through these diodes.
If the system power supply design does not control the voltage sequencing, the circuit shown in Figure 4
can be added to meet these requirements. The MUR420 Schottky diodes control the maximum potential
difference between the external bus and core power supplies on powerup and the 1N5820 diodes regulate
the maximum potential difference on powerdown.
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Layout Practices
VDDHVDDL
MUR420
1N5820
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Figure 4. Example Voltage Sequencing Circuit
9Layout Practices
Each VDD pin on the MPC866/859 should be provided with a low-impedance path to the board’s supply.
Furthermore, each GND pin should be provided with a low-impedance path to ground. The power supply
pins drive distinct groups of logic on chip. The V
least four 0.1 µF bypass capacitors located as close as possible to the four sides of the package. Each board
designed should be characterized and additional appropriate decoupling capacitors should be used if
required. The capacitor leads and associated printed-circuit traces connecting to chip V
be kept to less than 1/2” per capacitor lead. At a minimum, a four-layer board employing two inner layers
as V
All output pins on the MPC866/859 have fast rise and fall times. Printed-circuit (PC) trace interconnection
length should be minimized in order to minimize undershoot and reflections caused by these fast output
switching times. This recommendation particularly applies to the address and data buses. Maximum PC
trace lengths of 6” are recommended. Capacitance calculations should consider all device loads as well as
parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes
especially critical in systems with higher capacitive loads because these loads create higher transient
currents in the V
Special care should be taken to minimize the noise levels on the PLL supply pins. For more information,
please refer to Section 14.4.3, Clock Synthesizer Power (VDDSYN, VSSSYN, VSSSYN1), in the MPC866User’s Manual.
and GND planes should be used.
DD
and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
DD
power supply should be bypassed to ground using at
DD
and GND should
DD
10Bus Signal Timing
The maximum bus speed supported by the MPC866/859 is 66 MHz. Higher-speed parts must be operated
in half-speed bus mode (for example, an MPC866/859 used at 100 MHz must be configured for a 50-MHz
bus). Table 7 and Table 8 show the frequency ranges for standard part frequencies.
MOTOROLAMPC866/859 Hardware Specifications 15
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Bus Signal Timing Bus Signal Timing
Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode)
Part Freq50 MHz66 MHz
MinMaxMinMax
Core 40504066.67
Bus 40504066.67
Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode)
nc...
I
cale Semiconductor,
Frees
Part
Freq
Core 40504066.674010040133.34
Bus 20252033.3320502066.67
50 MHz66 MHz100 MHz133 MHz
MinMaxMinMaxMinMaxMinMax
T able 9 shows the timings for the MPC866/859 at 33, 40, 50, and 66 MHz b us operation. The timing for the
MPC866/859 bus shown in this table assumes a 50-pF load for maximum delays and a 0-pF load for
minimum delays. CLKOUT assumes a 100-pF load maximum delay.
requested by control bit CST4 in the
corresponding word in the UPM (MAX
= 0.00 X B1 + 6.00)
requested by control bit CST1 in the
corresponding word in the UPM (MAX
= 0.25 x B1 + 6.80)
requested by control bit CST2 in the
corresponding word in the UPM (MAX
= 0.00 x B1 + 8.00)
requested by control bit CST3 in the
corresponding word in the UPM (MAX
= 0.25 x B1 + 6.30)
requested by control bit CST1 in the
corresponding word in the UPM EBDF
= 1 (MAX = 0.375 x B1 + 6.6)
requested by control bit BST4 in the
corresponding word in the UPM (MAX
= 0.00 x B1 + 6.00)
valid, as
valid, as
valid, as
valid, as
valid, as
valid, as
8.40—6.40—4.50—2.70—ns
38.67—31.38—24.50—17.83—ns
1.506.001.506.001.506.001.506.00ns
7.6014.306.3013.005.0011.803.8010.50ns
1.508.001.508.001.508.001.508.00ns
7.6013.806.3012.505.0011.303.8010.00ns
13.3018.0011.3016.009.4014.107.6012.30ns
1.506.001.506.001.506.001.506.00ns
B32a CLKOUT falling edge to BS
requested by control bit BST1 in the
corresponding word in the UPM, EBDF
= 0 (MAX = 0.25 x B1 + 6.80)
B32b CLKOUT rising edge to BS
requested by control bit BST2 in the
corresponding word in the UPM (MAX
= 0.00 x B1 + 8.00)
MOTOROLAMPC866/859 Hardware Specifications 21
valid, as
valid, as
7.6014.306.3013.005.0011.803.8010.50ns
1.508.001.508.001.508.001.508.00ns
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Bus Signal Timing Bus Signal Timing
NumCharacteristic
Freescale Semiconductor, Inc.
Table 9. Bus Operation Timings (continued)
33 MHz40 MHz50 MHz66 MHz
MinMaxMinMaxMinMaxMinMax
Unit
nc...
I
cale Semiconductor,
Frees
B32c CLKOUT rising edge to BS valid, as
requested by control bit BST3 in the
corresponding word in the UPM (MAX
= 0.25 x B1 + 6.80)
B32d CLKOUT falling edge to BS
requested by control bit BST1 in the
corresponding word in the UPM, EBDF
= 1 (MAX = 0.375 x B1 + 6.60)
B33 CLKOUT falling edge to GPL
requested by control bit GxT4 in the
corresponding word in the UPM (MAX
= 0.00 x B1 + 6.00)
B33a CLKOUT rising edge to GPL
requested by control bit GxT3 in the
corresponding word in the UPM (MAX
= 0.25 x B1 + 6.80)
B34 A(0:31), BADDR(28:30), and D(0:31)
to CS
valid, as requested by control bit
CST4 in the corresponding word in the
UPM (MIN = 0.25 x B1 - 2.00)
B34a A(0:31), BADDR(28:30), and D(0:31)
to CS
valid, as requested by control bit
CST1 in the corresponding word in the
UPM (MIN = 0.50 x B1 – 2.00)
B34b A(0:31), BADDR(28:30), and D(0:31)
to CS
valid, as requested by CST2 in
the corresponding word in UPM (MIN =
0.75 x B1 – 2.00)
B35 A(0:31), BADDR(28:30) to CS
requested by control bit BST4 in the
corresponding word in the UPM (MIN =
0.25 x B1 – 2.00)
B35a A(0:31), BADDR(28:30), and D(0:31)
to BS
valid, as Requested by BST1 in
the corresponding word in the UPM
(MIN = 0.50 x B1 – 2.00)
valid- as
valid, as
valid, as
valid, as
7.6014.306.3013.005.0011.803.8010.50ns
13.3018.0011.3016.009.4014.107.6012.30ns
1.506.001.506.001.506.001.506.00ns
7.6014.306.3013.005.0011.803.8010.50ns
5.60—4.30—3.00—1.80—ns
13.20—10.50—8.00—5.60—ns
20.70—16.70—13.00—9.40—ns
5.60—4.30—3.00—1.80—ns
13.20—10.50—8.00—5.60—ns
B35b A(0:31), BADDR(28:30), and D(0:31)
to BS
valid, as requested by control bit
BST2 in the corresponding word in the
UPM (MIN = 0.75 x B1 – 2.00)
B36 A(0:31), BADDR(28:30), and D(0:31)
to GPL
valid as requested by control bit
GxT4 in the corresponding word in the
UPM (MIN = 0.25 x B1 – 2.00)
22MPC866/859 Hardware Specifications MOTOROLA
20.70—16.70—13.00—9.40—ns
5.60—4.30—3.00—1.80—ns
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NumCharacteristic
Bus Signal Timing
Table 9. Bus Operation Timings (continued)
33 MHz40 MHz50 MHz66 MHz
Unit
MinMaxMinMaxMinMaxMinMax
B37 UPWAIT valid to CLKOUT falling
B38 CLKOUT falling edge to UPWAIT
B39 AS valid to CLKOUT rising edge 9 (MIN
B40 A(0:31), TSIZ(0:1), RD/WR
B41 TS
nc...
I
cale Semiconductor,
B42 CLKOUT rising edge to TS
B43 AS
1
For part speeds above 50 MHz, use 9.80 ns for B11a.
2
The timing required for BR input is relevant when the MPC866/859 is selected to work with the internal bus arbiter.
The timing for BG
3
For part speeds above 50 MHz, use 2 ns for B17.
4
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of CLKOUT, in which the TA input signal
is asserted.
5
For part speeds above 50 MHz, use 2 ns for B19.
6
The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for
read accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats, where
DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
7
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
8
The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally. The timings specified in B37
and B38 are specified to enable the freeze of the UPM output signals as described in Figure 20.
9
The AS signal is considered asynchronous to CLKOUT. The timing B39 is specified in order to allow the behavior
specified in Figure 23.
8
edge
(MIN = 0.00 x B1 + 6.00)
8
valid
(MIN = 0.00 x B1 + 1.00)
= 0.00 x B1 + 7.00)
, BURST,
valid to CLKOUT rising edge (MIN =
0.00 x B1 + 7.00)
valid to CLKOUT rising edge (setup
time) (MIN = 0.00 x B1 + 7.00)
valid (hold
time) (MIN = 0.00 x B1 + 2.00)
negation to memory controller
signals negation (MAX = TBD)
input is relevant when the MPC866/859 is selected to work with the external bus arbiter.
6.00—6.00—6.00—6.00—ns
1.00—1.00—1.00—1.00—ns
7.00—7.00—7.00—7.00—ns
7.00—7.00—7.00—7.00—ns
7.00—7.00—7.00—7.00—ns
2.00—2.00—2.00—2.00—ns
—TBD—TBD—TBD—TBDns
Frees
MOTOROLAMPC866/859 Hardware Specifications 23
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Bus Signal Timing Bus Signal Timing
Freescale Semiconductor, Inc.
Figure 5 shows the control timing diagram.
nc...
I
cale Semiconductor,
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CLKOUT
Outputs
Outputs
Inputs
Inputs
A
BMinimum output hold time
CMinimum input setup time specification
DMinimum input hold time specification
2.0 V
0.8 V
A
B
2.0 V
0.8 V
B
2.0 V
0.8 V
C
2.0 V
0.8 V
Maximum output delay specification
Figure 5. Control Timing
Figure 6 shows the timing for the external clock.
CLKOUT
2.0 V
0.8 V
0.8 V
A
D
2.0 V
0.8 V
2.0 V
0.8 V
C
2.0 V
0.8 V
2.0 V
D
2.0 V
0.8 V
B1
B1
B4
Figure 6. External Clock Timing
24MPC866/859 Hardware Specifications MOTOROLA
B5
B3
B2
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Figure 7 shows the timing for the synchronous output signals.
CLKOUT
B7B9
Output
Signals
Output
Signals
nc...
I
Output
Signals
B7b
Bus Signal Timing
B8
B8a
B9B7a
B8b
cale Semiconductor,
Frees
Figure 7. Synchronous Output Signals Timing
Figure 8 shows the timing for the synchronous active pull-up and open-drain output signals.
CLKOUT
B13
B12B11
TS
, BB
B13a
B11aB12a
TA, BI
B14
B15
TEA
Figure 8. Synchronous Active Pull-Up Resistor and Open-Drain Output Signals Timing
MOTOROLAMPC866/859 Hardware Specifications 25
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Bus Signal Timing Bus Signal Timing
Figure 9 shows the timing for the synchronous input signals.
CLKOUT
T
A, BI
TEA, KR,
RETR
Y, CR
nc...
I
B16
B17
B16a
B17a
B16b
B17
cale Semiconductor,
Frees
BB, BG, BR
Figure 9. Synchronous Input Signals Timing
Figure 10 shows normal case timing for input data. It also applies to normal read accesses under the control
of the UPM in the memory controller.
CLKOUT
B16
B17
T
A
B18
B19
D[0:31],
DP[0:3]
Figure 10. Input Data Timing in Normal Case
26MPC866/859 Hardware Specifications MOTOROLA
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Figure 11 shows the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the
UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
CLKOUT
T
A
D[0:31],
DP[0:3]
Bus Signal Timing
B20
B21
nc...
I
cale Semiconductor,
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Figure 11. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1
Figure 12 through Figure 15 show the timing for the external bus read controlled by v arious GPCM factors.
CLKOUT
B11B12
TS
B8
A[0:31]
B22
CSx
B25
OE
B28
B23
B26
WE[0:3]
B18
D[0:31],
DP[0:3]
Figure 12. External Bus Read Timing (GPCM Controlled—ACS = 00)
MOTOROLAMPC866/859 Hardware Specifications 27
B19
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Bus Signal Timing Bus Signal Timing
CLKOUT
TS
A[0:31]
Freescale Semiconductor, Inc.
B11B12
B8
nc...
I
cale Semiconductor,
Frees
B22a
CSx
B25B24
OE
D[0:31],
DP[0:3]
Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 0 or 1, ACS = 10)
CLKOUT
B11B12
TS
B22bB8
A[0:31]
B22cB23
CSx
B24aB25B26
B23
B26
B19B18
OE
B19B18
D[0:31],
DP[0:3]
Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = 0 or 1, ACS = 11)
28MPC866/859 Hardware Specifications MOTOROLA
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CLKOUT
TS
A[0:31]
Freescale Semiconductor, Inc.
B11B12
B8
Bus Signal Timing
B22a
CSx
B27
nc...
I
Figure 15. External Bus Read Timing (GPCM Controlled—TRLX = 0 or 1, ACS = 10, ACS = 11)
OE
D[0:31],
DP[0:3]
B27a
B22b B22cB19B18
cale Semiconductor,
B23
B26
Frees
MOTOROLAMPC866/859 Hardware Specifications 29
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Bus Signal Timing Bus Signal Timing
Figure 16 through Figure 18 show the timing for the external bus write controlled by various GPCM f actors.
CLKOUT
B11
TS
B8
A[0:31]
B22B23
CSx
nc...
I
WE[0:3]
B26
OE
D[0:31],
DP[0:3]
Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 0)
Table 10 shows the interrupt timing for the MPC866/859.
Table 10. Interrupt Timing
NumCharacteristic
I39IRQ
I40IRQx hold time after CLKOUT2.00—ns
I41IRQx pulse width low3.00—ns
I42IRQx pulse width high3.00—ns
I43IRQx edge-to-edge time4xT
1
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
level sensitive. The IRQ
to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ
nc...
I
no direct relation with the total system interrupt latency that the MPC866/859 is able to support.
Figure 25 shows the interrupt detection timing for the external level-sensitive lines.
Figure 26 shows the interrupt detection timing for the external edge-sensitive lines.
cale Semiconductor,
x valid to CLKOUT rising edge (setup time)6.00—ns
lines are synchronized internally and do not have to be asserted or negated with reference
CLKOUT
IRQ
x
Figure 25. Interrupt Detection Timing for External Level Sensitive Lines
CLKOUT
1
I39
I40
I41I42
All Frequencies
Unit
MinMax
CLOCKOUT
lines detection circuitry, and has
——
Frees
IRQ
x
I43
I43
Figure 26. Interrupt Detection Timing for External Edge Sensitive Lines
36MPC866/859 Hardware Specifications MOTOROLA
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Table 11 shows the PCMCIA timing for the MPC866/859.
Table 11. PCMCIA Timing
33 MHz40 MHz50 MHz66 MHz
NumCharacteristic
MinMaxMinMaxMinMaxMinMax
Bus Signal Timing
Unit
nc...
I
cale Semiconductor,
Frees
A(0:31), REG
P44
Strobe asserted
– 2.00)
A(0:31), REG
P45
negation
CLKOUT to REG valid (MAX = 0.25
P46
x B1 + 8.00)
CLKOUT to REG
P47
0.25 x B1 + 1.00)
CLKOUT to CE1
P48
(MAX = 0.25 x B1 + 8.00)
CLKOUT to CE1
P49
(MAX = 0.25 x B1 + 8.00)
CLKOUT to PCOE
P50
IO
WR assert time (MAX = 0.00 x
B1 + 11.00)
CLKOUT to PCOE
IO
P51
P52
P53
P54
P55
P56
1
WR negate time (MAX = 0.00 x
B1 + 11.00)
CLKOUT to ALE assert time (MAX
= 0.25 x B1 + 6.30)
CLKOUT to ALE negate time (MAX
= 0.25 x B1 + 8.00)
PCWE
invalid
AITA and WAITB valid to
W
CLKOUT rising edge
x B1 + 8.00)
CLKOUT rising edge to W
W
AITB invalid1 (MIN = 0.00 x B1 +
2.00)
PSST = 1. Otherwise, add PSST times cycle time.
PSHT = 0. Otherwise, add PSHT times cycle time.
These synchronous timings define when the W
current cycle. The W
PCMCIA Interface in the MPC866 PowerQUICC User’s Manual.
valid to PCMCIA
1
(MIN = 0.75 x B1
valid to ALE
1
(MIN = 1.00 x B1 – 2.00)
invalid (MIN =
, CE2 asserted
, CE2 negated
, IORD, PCWE,
, IORD, PCWE,
, IOWR negated to D(0:31)
1
(MIN = 0.25 x B1 – 2.00)
1
(MIN = 0.00
AITA and
AITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. See
20.70—16.70—13.00—9.40—ns
28.30—23.00—18.00—13.20—ns
7.6015.606.3014.305.0013.003.8011.80ns
8.60—7.30—6.00—4.80—ns
7.6015.606.3014.305.0013.003.8011.80ns
7.6015.606.3014.305.0013.003.8011.80ns
—11.00—11.00—11.00—11.00ns
2.0011.002.0011.002.0011.002.0011.00ns
7.6013.806.3012.505.0011.303.8010.00ns
—15.60—14.30—13.00—11.80ns
5.60—4.30—3.00—1.80—ns
8.00—8.00—8.00—8.00—ns
2.00—2.00—2.00—2.00—ns
AITx signals are detected in order to freeze (or relieve) the PCMCIA
MOTOROLAMPC866/859 Hardware Specifications 37
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Bus Signal Timing Bus Signal Timing
Figure 27 shows the PCMCIA access cycle timing for the external bus read.
CLKOUT
TS
A[0:31]
P44
P46P45
REG
P48P49
nc...
I
CE1/CE2
PCOE, IORD
P53P52P52
ALE
D[0:31]
Figure 27. PCMCIA Access Cycles Timing External Bus Read
cale Semiconductor,
P47
P51P50
B19B18
Frees
38MPC866/859 Hardware Specifications MOTOROLA
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Figure 28 shows the PCMCIA access cycle timing for the external bus write.
CLKOUT
TS
A[0:31]
P44
Bus Signal Timing
P46P45
REG
nc...
I
cale Semiconductor,
Figure 29 shows the PCMCIA WAIT signals detection timing.
CE1/CE2
PCWE, IOWR
ALE
D[0:31]
Figure 28. PCMCIA Access Cycles Timing External Bus Write
CLKOUT
P48P49
P53P52P52
P47
P51P50
P54
B9B8
Frees
P55
P56
W
AITx
Figure 29. PCMCIA WAIT Signals Detection Timing
MOTOROLAMPC866/859 Hardware Specifications 39
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Bus Signal Timing Bus Signal Timing
Freescale Semiconductor, Inc.
Table 12 shows the PCMCIA port timing for the MPC866/859.
Table 12. PCMCIA Port Timing
33 MHz40 MHz50 MHz66 MHz
NumCharacteristic
MinMaxMinMaxMinMaxMinMax
Unit
nc...
I
cale Semiconductor,
Frees
CLKOUT to OPx, valid (MAX = 0.00 x B1
P57
+ 19.00)
HRESET
P58
0.75 x B1 + 3.00)
IP_Xx valid to CLKOUT rising edge (MIN
P59
= 0.00 x B1 + 5.00)
CLKOUT rising edge to IP_Xx invalid
P60
(MIN = 0.00 x B1 + 1.00)
1
OP2 and OP3 only.
negated to OPx drive 1(MIN =
—19.00—19.00—19.00—19.00ns
25.70—21.70—18.00—14.40—ns
5.00—5.00—5.00—5.00—ns
1.00—1.00—1.00—1.00—ns
Figure 30 shows the PCMCIA output port timing for the MPC866/859.
CLKOUT
P57
Output
Signals
HRESET
P58
OP2, OP3
Figure 30. PCMCIA Output Port Timing
Figure 31 shows the PCMCIA output port timing for the MPC866/859.
CLKOUT
P59
P60
Input
Signals
Figure 31. PCMCIA Input Port Timing
40MPC866/859 Hardware Specifications MOTOROLA
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Table 13 shows the debug port timing for the MPC866/859.
NumCharacteristic
Table 13. Debug Port Timing
Bus Signal Timing
All Frequencies
Unit
MinMax
nc...
I
cale Semiconductor,
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D61DSCK cycle time3xT
D62DSCK clock pulse width1.25xT
D63DSCK rise and fall times0.003.00ns
D64DSDI input data setup time8.00—ns
D65DSDI data hold time5.00—ns
D66DSCK low to DSDO data valid0.0015.00ns
D67DSCK low to DSDO invalid0.002.00ns
Figure 32 shows the input timing for the debug port clock.
DSCK
D61
D61
D63
Figure 32. Debug Port Clock Input Timing
Figure 33 shows the timing for the debug port.
DSCK
DSDI
D66
D62
D62
D64
D65
D67
CLOCKOUT
CLOCKOUT
D63
—
—
DSDO
Figure 33. Debug Port Timings
MOTOROLAMPC866/859 Hardware Specifications 41
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Bus Signal Timing Bus Signal Timing
Freescale Semiconductor, Inc.
Table 14 shows the reset timing for the MPC866/859.
Table 14. Reset Timing
33 MHz40 MHz50 MHz66 MHz
NumCharacteristic
MinMaxMinMaxMinMaxMinMax
Unit
nc...
I
cale Semiconductor,
Frees
CLKOUT to HRESET
R69
(MAX = 0.00 x B1 + 20.00)
CLKOUT to SRESET
R70
(MAX = 0.00 x B1 + 20.00)
RSTCONF
R71
B1)
R72——————————
Configuration data to HRESET rising
R73
edge setup time (MIN = 15.00 x B1 +
50.00)
Configuration data to RSTCONF
edge setup time (MIN = 0.00 x B1 +
R74
350.00)
Configuration data hold time after
R75
RSTCONF
0.00)
Configuration data hold time after
R76
HRESET
0.00)
HRESET
data out drive (MAX = 0.00 x B1 +
R77
25.00)
RSTCONF
R78
impedance (MAX = 0.00 x B1 + 25.00)
CLKOUT of last rising edge before chip
R79
three-states HRESET
impedance (MAX = 0.00 x B1 + 25.00)
R80DSDI, DSCK setup (MIN = 3.00 x B1)90.90—75.00—60.00—45.50—ns
DSDI, DSCK hold time (MIN = 0.00 x B1
R81
+ 0.00)
SRESET
R82
edge for DSDI and DSCK sample (MIN
= 8.00 x B1)
pulse width (MIN = 17.00 x
negation (MIN = 0.00 x B1 +
negation (MIN = 0.00 x B1 +
and RSTCONF asserted to
negated to data out high
negated to CLKOUT rising
high impedance
high impedance
rising
to data out high
—20.00—20.00—20.00—20.00ns
—20.00—20.00—20.00—20.00ns
515.20—425.00—340.00—257.60—ns
504.50—425.00—350.00—277.30—ns
350.00—350.00—350.00—350.00—ns
0.00—0.00—0.00—0.00—ns
0.00—0.00—0.00—0.00—ns
—25.00—25.00—25.00—25.00ns
—25.00—25.00—25.00—25.00ns
—25.00—25.00—25.00—25.00ns
0.00—0.00—0.00—0.00—ns
242.40—200.00—160.00—121.20—ns
42MPC866/859 Hardware Specifications MOTOROLA
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Figure 34 shows the reset timing for the data bus configuration.
HRESET
RSTCONF
D[0:31] (IN)
Figure 34. Reset Timing—Configuration from Data Bus
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R71
R74
Bus Signal Timing
R76
R73
R75
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Figure 35 shows the reset timing for the data bus weak drive during configuration.
CLKOUT
R69
HRESET
R79
RSTCONF
R77R78
D[0:31] (OUT)
(Weak)
Figure 35. Reset Timing—Data Bus Weak Drive During Configuration
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(BRGCLK/pre_scaler) must be greater or equal to 4/1.
1
cale Semiconductor,
All Frequencies
Unit
MinMax
1.5100kHz
Frees
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Table 29 shows the I2C (SCL > 100 kHz) timings.
NumCharacteristicExpression
200SCL clock frequency (slave)fSCL0BRGCLK/48Hz
200SCL clock frequency (master)
202Bus free time between transmissions —1/(2.2 * fSCL)—s
203Low period of SCL—1/(2.2 * fSCL)—s
204High period of SCL—1/(2.2 * fSCL)—s
205Start condition setup time—1/(2.2 * fSCL)—s
206Start condition hold time—1/(2.2 * fSCL)—s
Table 29. I2C Timing (SCL > 100 kHz)
All Frequencies
MinMax
1
fSCLBRGCLK/16512BRGCLK/48Hz
CPM Electrical Characteristics
Unit
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207Data hold time—0—s
208Data setup time—1/(40 * fSCL)—s
209SDL/SCL rise time ——1/(10 * fSCL)s
210SDL/SCL fall time ——1/(33 * fSCL)s
211Stop condition setup time—1/2(2.2 * fSCL)—s
1
SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2).
The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1.
2
Figure 71 shows the I
SDA
205
SCL
C bus timing.
202
206209211210
203
207
Figure 71. I2C Bus Timing Diagram
204
208
MOTOROLAMPC866/859 Hardware Specifications 69
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UTOPIA AC Electrical Specifications UTOPIA AC Electrical Specifications
13UTOPIA AC Electrical Specifications
Table 30 through Table 32 show the AC electrical specifications for the UTOPIA interface.
This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the
timing specifications for the MII signals are independent of system clock frequency (part speed
designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 or 3.3
V.
14.1MII Receive Signal Timing (MII_RXD [3:0], MII_RX_DV,
MII_RX_ER, MII_RX_CLK)
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz + 1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_RX_CLK frequency – 1%. Table 33 shows the timings for MII receive signal.
Table 33. MII Receive Signal Timing
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NumCharacteristicMinMaxUnit
M1MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup5—ns
M2MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold5—ns
M3MII_RX_CLK pulse width high35%65%MII_RX_CLK period
M4MII_RX_CLK pulse width low35%65%MII_RX_CLK period
Figure 74 shows the timings for MII receive signal.
M3
MII_RX_CLK (input)
M4
MII_RXD[3:0] (inputs)
MII_RX_DV
MII_RX_ER
M1
M2
Figure 74. MII Receive Signal Timing Diagram
14.2MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN,
MII_TX_ER, MII_TX_CLK)
The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. There is
no minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_TX_CLK frequency - 1%.
72MPC866/859 Hardware Specifications MOTOROLA
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Table 34 shows information on the MII transmit signal timing.
NumCharacteristicMinMaxUnit
FEC Electrical Characteristics
Table 34. MII Transmit Signal Timing
M5MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER
invalid
M6MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER
valid
M7MII_TX_CLK pulse width high35%65%MII_TX_CLK period
M8MII_TX_CLK pulse width low35%65%MII_TX_CLK period
Figure 75 shows the MII transmit signal timing diagram.
M7
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MII_TX_CLK (input)
M5
MII_TXD[3:0] (outputs)
MII_TX_EN
MII_TX_ER
M6
Figure 75. MII Transmit Signal Timing Diagram
14.3MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 35 shows the timing for on the MII async inputs signal.
cale Semiconductor,
NumCharacteristicMinMaxUnit
Table 35. MII Async Inputs Signal Timing
5—ns
—25—
M8
Frees
M9MII_CRS, MII_COL minimum pulse width1.5—MII_TX_CLK period
Figure 76 shows the MII asynchronous inputs signal timing diagram.
14.4MII Serial Management Channel Timing (MII_MDIO,
MII_MDC)
T able 36 shows the timing for the MII serial management channel signal. The FEC functions correctly with
a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation.
Table 36. MII Serial Management Channel Timing
NumCharacteristicMinMaxUnit
M10MII_MDC falling edge to MII_MDIO output invalid (minimum
propagation delay)
M11MII_MDC falling edge to MII_MDIO output valid (maximum
propagation delay)
M12MII_MDIO (input) to MII_MDC rising edge setup10—ns
M13MII_MDIO (input) to MII_MDC rising edge hold0—ns
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M14MII_MDC pulse width high40%60%MII_MDC period
M15MII_MDC pulse width low40%60%MII_MDC period
Figure 77 shows the MII serial management channel timing diagram.
M14
MM15
MII_MDC (output)
M10
MII_MDIO (output)
M11
MII_MDIO (input)
0—ns
—25ns
Frees
M12
Figure 77. MII Serial Management Channel Timing Diagram
74MPC866/859 Hardware Specifications MOTOROLA
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Mechanical Data and Ordering Information
15Mechanical Data and Ordering Information
Table 37 shows information on the MPC866/859 derivative devices.
Table 37. MPC866/859 Derivatives
Number
Device
MPC866T4 10/100 MbpsYesYes4 Kbyte4 Kbytes
MPC866P4 10/100 MbpsYesYes16 Kbyte8 Kbytes
MPC859T1 (SCC1)10/100 MbpsYesYes4 Kbyte4 Kbytes
MPC859DSL1 (SCC1)10/100 MbpsNoUp to 4 addresses4 Kbyte4 Kbytes
1
Serial communications controller (SCC).
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Table 38 identifies the packages and operating frequencies orderable for the MPC866/859 derivative
devices.
Package TypeTemperature (Tj)Frequency (MHz)Order Number
Plastic ball grid array
(ZP suffix)
Plastic ball grid array
(CZP suffix)
1
Additional extended temperature devices can be made available at 50, 66, 80, and100MHz.
of
SCCs
1
Ethernet
Support
Table 38. MPC866/859 Package/Frequency Orderable
Multi-Channel
HDLC Support
0° to 95°C50MPC859DSLZP50
–40° to 100°CTBD
ATM Support
InstructionData
66MPC859DSLZP66
100MPC866PZP100
133MPC866PZP133
1
Cache Size
MPC866TZP100
MPC859PZP100
MPC859TZP100
MPC866TZP133
MPC859PZP133
MPC859TZP133
TBD
Frees
MOTOROLAMPC866/859 Hardware Specifications 75
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Mechanical Data and Ordering Information Mechanical Data and Ordering Information
15.1Pin Assignments
Figure 78 shows the top view pinout of the PBGA package. For additional information, see the MPC866
PowerQUICC Family User’s Manual.
For more information on the printed-circuit board layout of the PBGA package, including thermal via
design and suggested pad layout, please refer to Plastic Ball Grid Array Application Note (order number:
AN1231/D) available from your local Motorola sales of fice. Figure 79 shows the mechanical dimensions of
the PBGA package.
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Mechanical Data and Ordering Information
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Note: Solder sphere composition for MPC866XZP, MPC859PZP, MPC859DSLZP, and MPC859TZP
is 62%Sn 36%Pb 2%Ag
Figure 79. Mechanical Dimensions and Bottom Surface Nomenclature of the PBGA Package
MOTOROLAMPC866/859 Hardware Specifications 87
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Document Revision History Document Revision History
16Document Revision History
Table 40 lists significant changes between revisions of this document.
Table 40. Document Revision History
Revision
Number
05/2002Initial revision
111/2002Added the 5-V tolerant pins, new package dimensions, and other changes.
1.14/2003Added the Spec. B1d and changed spec. B1a. Added the Note Solder sphere
1.24/2003Added the MPC859P.
1.35/2003Changed the SPI Master Timing Specs. 162 and 164.
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1.47-8/2003 • Added TxClav and RxClav to PB15 and PC15. Changed B28a through B28d and
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DateSubstantive Changes
composition for MPC866XZP, MPC859DSLZP, and MPC859TZP is 62%Sn 36%Pb
2%Ag to Figure 15-79.
B29b to show that TRLX can be 0 or 1.
• Added nontechnical reformatting.
Frees
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MOTOROLAMPC866/859 Hardware Specifications 89
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90MPC866/859 Hardware Specifications MOTOROLA
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MOTOROLAMPC866/859 Hardware Specifications 91
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