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PowerPC
™
MPC801
Integrated Microprocessor
for Embedded Systems
User’s Manual
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©
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™
is a registered trademark of Motorola, Inc. PowerPC
™
is a registered
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C is a trademark
TABLE OF CONTENTS
Paragraph Page
Number Title Number
Section 1
Introduction
1.1 Features ...............................................................................................1-1
1.2 MPC801 Architecture ...........................................................................1-4
1.2.1 The Embedded PowerPC Core ..................................................1-5
1.2.2 The System Interface Unit ..........................................................1-6
1.2.3 The UART Controller ..................................................................1-6
1.2.4 The I
1.2.5 The Serial Peripheral Interface Controller ..................................1-7
1.3 Power Management .............................................................................1-7
1.4 MPC801 Applications ...........................................................................1-7
1.5 Differences Between the MPC801 and MPC860 .................................1-8
1.6 MPC801 Glueless System Design .......................................................1-8
2
C
Controller ....................................................................... 1-7
Section 2
External Signals
2.1 The System Bus Signals ......................................................................2-2
Section 3
Memory Map
Section 4
Reset
4.1 Types of Reset .....................................................................................4-1
4.1.1 Power-On Reset .........................................................................4-2
4.1.2 External Hard Reset ...................................................................4-2
4.1.3 Internal Hard Reset ....................................................................4-3
4.1.3.1 Loss of Lock ....................................................................4-3
4.1.3.2 Software Watchdog Reset ..............................................4-3
4.1.3.3 Checkstop Reset ............................................................4-3
4.1.3.4 Debug Port Hard Reset ..................................................4-3
4.1.3.5 JTAG Reset ....................................................................4-3
4.1.4 External Soft Reset ....................................................................4-3
4.1.5 Internal Soft Reset ......................................................................4-4
4.1.5.1 Debug Port Soft Reset ....................................................4-4
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4.2 Reset Status Register ..........................................................................4-4
4.3 How to Configure Reset .......................................................................4-6
4.3.1 Hard Reset .................................................................................4-6
4.3.2 Soft Reset ................................................................................4-11
Section 5
Clocks and Power Control
5.1 The Clock Module ................................................................................5-3
5.2 On-Chip Oscillators and External Clock Input ......................................5-6
5.3 The System Phase-Locked Loop .........................................................5-7
5.3.1 Multiplying the Frequency ..........................................................5-7
5.3.2 Eliminating Skew ........................................................................5-7
5.3.3 Operating the PLL Block ............................................................5-8
5.4 The Low-Power Divider ........................................................................5-8
5.5 Internal Clock Signals ..........................................................................5-9
5.5.1 The General System Clocks ......................................................5-9
5.5.2 The Baud Rate Generator Clock ..............................................5-11
5.5.3 The Synchronization Clocks .....................................................5-11
5.6 The Phase-Locked Loop Pins ............................................................5-12
5.7 Controlling The System Clock ............................................................5-13
5.8 PLL Low-Power and Reset Control Register .....................................5-16
5.9 Basic Power Structure ........................................................................5-22
5.10 Keep Alive Power ...............................................................................5-23
5.10.1 Configuration ............................................................................5-23
5.10.2 The Key Mechanism ................................................................5-24
Section 6
The PowerPC Core
6.1 Features ...............................................................................................6-1
6.1.1 Basic Structure of the Core ........................................................6-2
6.1.2 Instruction Flow Within the Core ................................................6-2
6.1.3 Basic Instruction Pipeline ...........................................................6-4
6.2 The Sequencer Unit .............................................................................6-4
6.2.1 Flow Control ...............................................................................6-4
6.2.2 Issuing Instructions ....................................................................6-6
6.2.3 Interrupts ....................................................................................6-6
6.2.4 Precise Exception Model Implementation ..................................6-8
6.2.5 Processing An Interrupt ............................................................6-11
6.2.6 Serialization ..............................................................................6-12
6.2.7 The External Interrupt ..............................................................6-13
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6.2.7.1 Latency .........................................................................6-13
6.2.8 Interrupt Ordering .....................................................................6-13
6.3 The Register Unit ...............................................................................6-15
6.3.1 The Control Registers ..............................................................6-15
6.3.1.1 Physical Location of Special Registers .........................6-19
6.3.1.2 Bit Assignment of the Control Registers .......................6-20
6.3.1.3 Initializing the Control Registers ...................................6-24
6.4 The Fixed-Point Unit ...........................................................................6-24
6.4.1 Updating XER with Divide Instructions .....................................6-24
6.5 The Load/Store Unit ...........................................................................6-25
6.5.1 Load/Store Instruction ..............................................................6-26
6.5.2 Synchronizing Load/Store Instructions .....................................6-27
6.5.3 Instructions Issued to the Data Cache .....................................6-27
6.5.4 Issuing Store Instruction ...........................................................6-27
6.5.5 Nonspeculative Load Instructions ............................................6-28
6.5.6 Executing Unaligned Instructions .............................................6-28
6.5.7 Little-Endian Mode Support ......................................................6-29
6.5.8 Atomic Update Primitives .........................................................6-29
6.5.9 Instruction Timing .....................................................................6-29
6.5.10 Stalling Storage Control Instructions ........................................6-30
6.5.11 Accessing Off-Core Special Registers .....................................6-30
6.5.12 Storage Control Instructions .....................................................6-30
6.5.13 Exception Processing ...............................................................6-31
6.5.13.1 Using DAR, DSISR, and BAR .......................................6-31
Section 7
PowerPC Architecture Compliance
7.1 PowerPC User Instruction Set Architecture (Book I) ............................7-1
7.1.1 Computation Modes ...................................................................7-1
7.1.2 Reserved Fields .........................................................................7-1
7.1.3 Classes of Instructions ...............................................................7-1
7.1.4 Exceptions ..................................................................................7-2
7.1.5 The Branch Processor ................................................................7-2
7.1.6 Fetching Instructions ..................................................................7-2
7.1.7 Branch Instructions .....................................................................7-2
7.1.7.1 Invalid Branch Instruction Forms ....................................7-2
7.1.7.2 Branch Prediction ...........................................................7-2
7.1.8 The Fixed-Point Processor .........................................................7-2
7.1.8.1 Move To/From System Register Instructions ..................7-3
7.1.8.2 Fixed-Point Arithmetic Instructions .................................7-3
7.1.9 The Load/Store Processor .........................................................7-3
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7.1.9.1 Fixed-Point Load and Store With Update Instructions ....7-3
7.1.9.2 Fixed-Point Load and Store Multiple Instructions ...........7-3
7.1.9.3 Fixed-Point Load String Instructions ...............................7-3
7.1.9.4 Storage Synchronization Instructions .............................7-3
7.1.9.5 Optional Instructions .......................................................7-3
7.1.9.6 Little-Endian Byte Ordering ............................................7-4
7.2 PowerPC Virtual Environment Architecture (Book II) ...........................7-4
7.2.1 Storage Model ............................................................................7-4
7.2.1.1 Memory Coherence ........................................................7-4
7.2.1.2 Atomic Update Primitives ...............................................7-4
7.2.2 The Effect of Operand Placement on Performance ...................7-4
7.2.3 The Storage Control Instructions ...............................................7-5
7.2.3.1 Instruction Cache Block Invalidate (icbi) .........................7-5
7.2.3.2 Instruction Synchronize (isync) .......................................7-5
7.2.3.3 Data Cache Block Touch (dcbt) ......................................7-5
7.2.3.4 Data Cache Block Touch for Store (dcbtst) ....................7-5
7.2.3.5 Data Cache Block Set to Zero (dcbz) .............................7-5
7.2.3.6 Data Cache Block Store (dcbst) .....................................7-5
7.2.3.7 Data Cache Block Invalidate (dcbi) ................................7-5
7.2.3.8 Data Cache Block Flush (dcbf) .......................................7-5
7.2.3.9 Enforce In-Order Execution of I/O (eieio) .......................7-6
7.2.4 Timebase ...................................................................................7-6
7.3 PowerPC Operating Environment Architecture (Book III) ....................7-6
7.3.1 The Branch Processor ...............................................................7-6
7.3.1.1 Branch Processor Registers ...........................................7-6
7.3.1.2 Branch Processor Instructions ........................................7-6
7.3.2 The Fixed-Point Processor .........................................................7-6
7.3.2.1 Special-Purpose Registers .............................................7-6
7.3.3 Storage Model ............................................................................7-7
7.3.3.1 Address Translation ........................................................7-7
7.3.4 Reference and Change Bits .......................................................7-7
7.3.5 Storage Protection .....................................................................7-7
7.3.6 Storage Control Instructions .......................................................7-7
7.3.6.1 Data Cache Block Invalidate (dcbi) ................................7-7
7.3.6.2 TLB Invalidate Entry (tlbie) .............................................7-7
7.3.6.3 TLB Invalidate All (tlbia) ..................................................7-8
7.3.6.4 TLB Synchronize (tlbsync) ..............................................7-8
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7.3.7 Interrupts ....................................................................................7-8
7.3.7.1 Classes ...........................................................................7-8
7.3.7.2 Processing ......................................................................7-8
7.3.7.3 Definitions .......................................................................7-8
7.3.7.4 Partially Executed Instructions ......................................7-17
7.3.8 Timer Facilities .........................................................................7-17
7.3.9 Optional Facilities and Instructions ...........................................7-17
Section 8
Instruction Execution Timing
8.1 Instruction Execution Timing Examples ...............................................8-4
8.1.1 Data Cache Load .......................................................................8-4
8.1.2 Writeback ...................................................................................8-5
8.1.2.1 Writeback Arbitration ......................................................8-5
8.1.2.2 Private Writeback Bus Dedicated for Load .....................8-6
8.1.3 Fastest External Load (Data Cache Miss) ..................................8-7
8.1.4 A Full History Buffer ...................................................................8-8
8.1.5 Branch Folding ...........................................................................8-9
8.1.6 Branch Prediction .....................................................................8-10
Section 9
Instruction Cache
9.1 Features ...............................................................................................9-1
9.2 Programming the Instruction Cache .....................................................9-4
9.2.1 Instruction Cache Control and Status Register ..........................9-4
9.2.2 Instruction Cache Address Register ...........................................9-5
9.2.3 Instruction Cache Data Port Register .........................................9-6
9.3 How the Instruction Cache Works ........................................................9-6
9.3.1 Instruction Cache Hit ..................................................................9-6
9.3.2 Instruction Cache Miss ...............................................................9-6
9.3.3 Instruction Fetch On A Predicted Path .......................................9-7
9.4 Instruction Cache Commands ..............................................................9-7
9.4.1 Instruction Cache Block Invalidate .............................................9-8
9.4.2 Invalidate All Instruction Cache ..................................................9-8
9.4.3 Load & Lock ...............................................................................9-8
9.4.4 Unlock Line .................................................................................9-9
9.4.5 Unlock All ...................................................................................9-9
9.4.6 Instruction Cache Inhibit .............................................................9-9
9.4.7 Instruction Cache Read ............................................................9-10
9.4.8 Instruction Cache Write ............................................................9-11
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9.5 Restrictions ........................................................................................9-11
9.6 Instruction Cache Coherency .............................................................9-11
9.7 Updating Code And Memory Region Attributes .................................9-11
9.8 Reset Sequence .................................................................................9-12
9.9 Debug Support ...................................................................................9-12
9.9.1 Fetching Instructions From the Development Port ...................9-12
Section 10
Data Cache
10.1 Features .............................................................................................10-1
10.2 Organization of the Data Cache .........................................................10-2
10.3 Programming the Data Cache ............................................................10-3
10.3.1 PowerPC Architecture Instructions ..........................................10-3
10.3.1.1 PowerPC User Instruction Set Architecture ..................10-3
10.3.1.2 PowerPC Virtual Environment Architecture ..................10-3
10.3.1.3 PowerPC Operating Environment Architecture ............10-3
10.3.2 Implementation Specific Operations ........................................10-3
10.3.3 Special Registers of the Data Cache .......................................10-3
10.3.3.1 Data Cache Control and Status Register .....................10-4
10.3.3.2 Data Cache Address Register ......................................10-6
10.3.3.3 Reading the Cache Structures .....................................10-6
10.3.3.4 Data Cache Data Register ............................................10-7
10.4 Operating the Data Cache .................................................................10-7
10.4.1 Data Cache Read .....................................................................10-7
10.4.2 Data Cache Write .....................................................................10-8
10.4.2.1 Copyback Mode ............................................................10-8
10.4.2.2 Writethrough Mode .......................................................10-9
10.4.3 Data Cache-Inhibited Accesses ...............................................10-9
10.4.4 Data Cache Freeze ..................................................................10-9
10.4.5 Data Cache Coherency ..........................................................10-10
10.5 Controlling the Data Cache ..............................................................10-10
10.5.1 Flushing and Invalidating .......................................................10-10
10.5.2 Disabling ................................................................................10-10
10.5.3 Locking ...................................................................................10-10
10.5.4 Storage Control Instructions in the Data Cache .....................10-11
10.5.4.1 dcbi, dcbst, dcbf And dcbz Instructions ......................10-11
10.5.4.2 Touch ..........................................................................10-11
10.5.4.3 Storage Synchronization and Reservation .................10-11
10.5.5 Reading the Data Cache Structures ......................................10-11
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Section 11
Memory Management Unit
11.1 Features .............................................................................................11-1
11.2 Address Translation ...........................................................................11-2
11.2.1 Translation Lookaside Buffer Operation ...................................11-2
11.3 Protection ...........................................................................................11-3
11.4 Storage Attributes ...............................................................................11-4
11.4.1 Reference and Change Bit Updates .........................................11-4
11.4.2 Storage Control ........................................................................11-4
11.5 Translation Table Structure ................................................................11-4
11.5.1 Level One Descriptor ................................................................11-8
11.5.2 Level Two Descriptor ................................................................11-9
11.6 Memory Management Unit Programming Model ..............................11-10
11.6.1 Configuration Registers ..........................................................11-10
11.6.1.1 Instruction MMU Control Register ...............................11-10
11.6.1.2 MI_AP Register ...........................................................11-11
11.6.1.3 Data MMU Control Register ........................................11-12
11.6.1.4 MD_AP Register .........................................................11-13
11.6.1.5 CASID Register ..........................................................11-14
11.6.2 Tablewalk Registers ...............................................................11-14
11.6.2.1 M_TWB Register ........................................................11-14
11.6.2.2 M_TW Register ...........................................................11-15
11.6.2.3 MI_EPN Register ........................................................11-15
11.6.2.4 MI_TWC Register .......................................................11-16
11.6.2.5 MI_RPN Register ........................................................11-17
11.6.2.6 MD_EPN Register ......................................................11-18
11.6.2.7 Data MMU Tablewalk Control Register ......................11-19
11.6.2.8 MD_RPN Register ......................................................11-20
11.6.3 Instruction Debug Registers ...................................................11-22
11.6.3.1 MI_DCAM Register .....................................................11-22
11.6.3.2 MI_DRAM0 Register ...................................................11-23
11.6.3.3 MI_DRAM1 Register ...................................................11-24
11.6.4 Data Debug Registers ............................................................11-25
11.6.4.1 MD_DCAM Register ...................................................11-25
11.6.4.2 MD_DRAM0 Register .................................................11-26
11.6.4.3 MD_DRAM1 Register .................................................11-27
11.7 Interrupts ..........................................................................................11-29
11.7.1 Implementation Specific Instruction TLB Miss ........................11-29
11.7.2 Implementation Specific Data TLB Miss .................................11-29
11.7.3 Implementation Specific Instruction TLB Error .......................11-29
11.7.4 Implementation Specific Data TLB Error ................................11-29
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11.8 Manipulating the TLB .......................................................................11-30
11.8.1 Reloading the TLB .................................................................11-30
11.8.1.1 Translation Reload Examples .....................................11-31
11.8.2 Controlling the TLB Replacement Counter ............................11-32
11.8.3 Invalidating the TLB ...............................................................11-32
11.8.4 Loading the Reserved TLB Entries ........................................11-32
11.9 Requirements For Accessing The Memory Management
Unit Control Registers ......................................................................11-32
Section 12
System Interface Unit
12.1 Features .............................................................................................12-2
12.2 System Configuration and Protection .................................................12-2
12.3 Configuring the System ......................................................................12-4
12.3.1 Configuring the Interrupt ..........................................................12-4
12.3.2 Priority of the Interrupt Sources ...............................................12-5
12.3.2.1 Programming the Interrupt Controller ...........................12-6
12.3.2.2 SIU Interrupt Mask Register .........................................12-7
12.3.2.3 SIU Interrupt Edge Level Mask Register ......................12-8
12.3.2.4 SIU Interrupt Vector Register .......................................12-9
12.4 The Bus Monitor ...............................................................................12-10
12.5 The PowerPC Decrementer .............................................................12-10
12.6 The PowerPC Timebase ..................................................................12-11
12.7 The Real-Time Clock .......................................................................12-11
12.8 The Periodic Interrupt Timer ............................................................12-12
12.9 The Software Watchdog Timer ........................................................12-13
12.10 Freeze Operation .............................................................................12-15
12.10.1 Low-Power Stop Operation ....................................................12-15
12.11 Multiplexing the System Interface Unit Pins .....................................12-16
12.12 Programming the System Interface Unit ..........................................12-17
12.12.1 System Configuration and Protection Registers ....................12-17
12.12.1.1 SIU Module Configuration Register ............................12-17
12.12.1.2 Internal Memory Map Register ...................................12-20
12.12.1.3 System Protection Control Register ...........................12-21
12.12.1.4 Software Service Register ..........................................12-22
12.12.1.5 Transfer Error Status Register ....................................12-22
12.12.2 System Timer Registers .........................................................12-23
12.12.2.1 Decrementer Register ................................................12-23
12.12.2.2 Timebase Register .....................................................12-24
12.12.2.3 Timebase Reference Register ....................................12-24
12.12.2.4 Timebase Control and Status Register .......................12-25
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12.12.2.5 Real-Time Clock Status and Control Register ............12-26
12.12.2.6 Real-Time Clock Register ...........................................12-27
12.12.2.7 Real-Time Clock Alarm Register ................................12-27
12.12.2.8 Periodic Interupt Status and Control Register ............12-27
12.12.2.9 Periodic Interrupt Timer Count Register .....................12-28
12.12.2.10 Periodic Interrupt Timer Register ................................12-29
Section 13
External Bus Interface
13.1 Features .............................................................................................13-1
13.2 Transfer Signals .................................................................................13-2
13.2.1 Control Signals .........................................................................13-3
13.3 Signal Descriptions .............................................................................13-4
13.4 Operations on the Bus ........................................................................13-8
13.4.1 Basic Transfer Protocol ............................................................13-8
13.4.2 Single Beat Transfers ...............................................................13-8
13.4.2.1 Single Beat Read Flow .................................................13-9
13.4.2.2 Single Beat Write Flow ...............................................13-12
13.4.3 Burst Transfers .......................................................................13-16
13.4.4 The Burst Mechanism ............................................................13-16
13.4.5 Transfer Alignment and Packaging ........................................13-25
13.4.6 Arbitration Phase Signals .......................................................13-27
13.4.6.1 Bus Request ...............................................................13-28
13.4.6.2 Bus Grant ....................................................................13-28
13.4.6.3 Bus Busy .....................................................................13-29
13.4.7 Address Transfer Phase-Related Signals ..............................13-32
13.4.7.1 Transfer Start ..............................................................13-32
13.4.7.2 Address Bus ...............................................................13-32
13.4.7.3 Transfer Attributes ......................................................13-32
13.4.8 Termination Signals ................................................................13-35
13.4.8.1 Transfer Acknowledge ................................................13-35
13.4.8.2 Burst Inhibit .................................................................13-35
13.4.8.3 Transfer Error Acknowledge .......................................13-35
13.4.8.4 Protocol for Termination Signals .................................13-35
13.4.9 Storage Reservation Protocol ................................................13-37
13.4.10 Exception Control Cycles .......................................................13-40
13.4.10.1 RETRY ........................................................................13-40
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Section 14
Endian Modes
14.1 Little-Endian System Features ...........................................................14-2
14.2 Big-Endian System Features .............................................................14-4
14.3 PowerPC Little-Endian System Features ...........................................14-4
14.4 Setting the Endian Mode Of Operation ..............................................14-5
Section 15
Memory Controller
15.1 Features .............................................................................................15-1
15.2 Basic Architecture ..............................................................................15-3
15.2.1 Registers Associated with the Memory Controller ...................15-6
15.2.1.1 8-, 16-, and 32-Bit Port Size Configuration ...................15-7
15.2.1.2 Write-Protect Configuration ..........................................15-7
15.2.1.3 Address and Address Space Checking ........................15-7
15.2.1.4 Parity Generation and Checking ...................................15-7
15.2.1.5 Transfer Error Acknowledge Generation ......................15-7
15.2.2 The General-Purpose Chip-Select Machine ............................15-7
15.2.2.1 Programmable Wait State configuration .....................15-13
15.2.2.2 Extended Hold Time on Read Accesses ....................15-13
15.2.2.3 Global Chip-Select Operation .....................................15-15
15.2.2.4 SRAM interface ..........................................................15-16
15.2.2.5 GPCM External Asynchronous Master Support .........15-17
15.2.3 User-Programmable Machines ..............................................15-19
15.2.3.1 RAM Word Structure and Timing Specification ..........15-25
15.2.3.2 CS Signals ..................................................................15-28
15.2.3.3 Byte Select Signals .....................................................15-29
15.2.3.4 General-Purpose Signals ...........................................15-30
15.2.3.5 Loop Control Signal ....................................................15-31
15.2.3.6 Exception Handling .....................................................15-31
15.2.3.7 Address Control Signals .............................................15-32
15.2.3.8 The Disable Timer Mechanism ...................................15-35
15.2.3.9 Transfer Acknowledge And Data Sample Control ......15-36
15.2.3.10 The WAIT Mechanism ................................................15-36
15.2.3.11 Location of UPM Start Addresses ..............................15-39
15.2.3.12 Example DRAM Interface ...........................................15-39
15.2.3.13 Extended Data-Out Interface Example .......................15-52
15.3 External Master Support ..................................................................15-59
15.4 Programming the Memory Controller ...............................................15-68
15.4.1 Memory Status Register .........................................................15-68
15.4.2 Memory Periodic Timer Prescaler Register ...........................15-69
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15.4.3 Base Register .........................................................................15-70
15.4.4 Option Register ......................................................................15-72
15.4.5 Machine A Mode Register ......................................................15-75
15.4.6 Machine B Mode Register ......................................................15-78
15.4.7 Memory Command Register ..................................................15-82
15.4.8 Memory Data Register ...........................................................15-84
15.4.9 Memory Address Register ......................................................15-84
Section 16
Serial Communication Modules
16.1 The UART Controllers ........................................................................16-1
16.2 Features .............................................................................................16-2
16.3 Serial Interface Signals ......................................................................16-2
16.3.1 Sub-Block Description ..............................................................16-3
16.3.1.1 The Transmitter ............................................................16-3
16.3.1.2 The Receiver ................................................................16-5
16.3.1.3 The Baud Rate Generator ............................................16-8
16.3.1.4 The Global Controller Interface .....................................16-8
16.4 The Serial Controller ........................................................................16-15
16.4.1 Programming the Serial Controller .........................................16-15
16.4.1.1 Serial Controller Command Register ..........................16-15
16.4.2 The Serial Peripheral Interface ...............................................16-15
16.4.2.1 Features ......................................................................16-16
16.4.2.2 Clocking and Pin Functions ........................................16-17
16.4.2.3 SPI Transmission and Reception Process .................16-18
16.4.2.4 Programming the Serial Peripheral Interface ..............16-20
16.4.3 The I
16.4.3.1 Features ......................................................................16-27
16.4.3.2 Clocking and Pin Functions ........................................16-28
16.4.3.3 I
16.4.3.4 Programming the I
16.5 The Parallel I/O Port .........................................................................16-35
16.5.1 Features .................................................................................16-35
16.5.2 Port B Pin Functions ...............................................................16-35
16.5.3 The Port B Registers ..............................................................16-37
16.5.3.1 Port B Open-Drain Register ........................................16-37
16.5.3.2 Port B Data Register ...................................................16-37
16.5.3.3 Port B Data Direction Register ....................................16-38
16.5.3.4 Port B Pin Assignment Register .................................16-38
2
C Controller ...................................................................16-26
2
C Controller Transmission and Reception Process...16-28
2
C Controller ..................................16-30
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TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
Section 17
Data Alignment
Section 18
Development Support
18.1 Program Flow Tracking ......................................................................18-1
18.1.1 Basic Operation ........................................................................18-2
18.1.1.1 The Internal Hardware ..................................................18-2
18.1.1.2 Special Case of Queue Flush Information ....................18-4
18.1.1.3 Program Trace In Debug Mode ....................................18-5
18.1.1.4 Sequential Instructions Marked As Indirect Branch ......18-5
18.1.1.5 The External Hardware .................................................18-5
18.1.1.6 Benefits of Compression ..............................................18-7
18.1.2 Controlling the Instruction Fetch Show Cycle ..........................18-8
18.2 Watchpoint And Breakpoint Generation .............................................18-8
18.2.1 Internal Watchpoints and Breakpoints .....................................18-9
18.2.1.1 Features .....................................................................18-11
18.2.1.2 Restrictions .................................................................18-12
18.2.1.3 Byte And Half-Word Working Modes ..........................18-12
18.2.1.4 Context Dependent Filter ............................................18-14
18.2.1.5 Ignore First Match Option ...........................................18-14
18.2.1.6 Generating Compare Types .......................................18-15
18.2.2 Basic Watchpoint/Breakpoint Operation ................................18-16
18.2.2.1 Instruction Support .....................................................18-16
18.2.2.2 Load/Store Support ....................................................18-17
18.2.2.3 Counter Support .........................................................18-18
18.2.2.4 Trap Enable Programming .........................................18-20
18.3 Development System Interface ........................................................18-20
18.3.1 Trap Enable Mode ..................................................................18-22
18.3.2 Debug Mode ...........................................................................18-22
18.3.2.1 Debug Mode Enable vs. Debug Mode Disable ...........18-24
18.3.2.2 Entering Debug Mode .................................................18-24
18.3.2.3 CheckStop State And Debug Mode ............................18-27
18.3.2.4 Saving the Machine State in Debug Mode .................18-27
18.3.2.5 Running in Debug Mode .............................................18-28
18.3.2.6 Exiting Debug Mode ...................................................18-28
18.3.3 The Development Port ...........................................................18-28
18.3.3.1 The Development Port Pins ........................................18-29
18.3.3.2 Development Port Registers .......................................18-30
18.3.3.3 Development Port Serial Communications .................18-31
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Paragraph Page
Number Title Number
18.4 The Software Monitor Debugger ......................................................18-40
18.4.1 Freeze Indication ....................................................................18-41
18.5 Programming the Development Support Registers ..........................18-41
18.5.1 Protecting the Development Port Registers ...........................18-41
18.5.2 Development Port Registers ..................................................18-42
18.5.2.1 Comparator A–D Value Register ................................18-42
18.5.2.2 Comparator E–F Value Register .................................18-42
18.5.2.3 Comparator G–H Value Register ................................18-42
18.5.2.4 Breakpoint Address Register ......................................18-42
18.5.2.5 Instruction Support Control Register ...........................18-43
18.5.2.6 Load/Store Support Comparators Control Register ....18-46
18.5.2.7 Load/Store Support AND–OR Control Register ..........18-48
18.5.2.8 Breakpoint Counter A Value and Control Register .....18-50
18.5.2.9 Breakpoint Counter B Value and Control Register .....18-51
18.5.3 Debug Mode Registers ...........................................................18-51
18.5.3.1 Interrupt Cause Register .............................................18-51
18.5.3.2 Debug Enable Register ...............................................18-53
18.5.4 Development Port Data Register ............................................18-55
Section 19
IEEE 1149.1 Test Access Port
19.1 The TAP Controller .............................................................................19-3
19.2 The Boundary Scan Register .............................................................19-4
19.3 The Instruction Register ...................................................................19-17
19.3.1 The External Test Instruction .................................................19-18
19.3.2 The sample/preload Instruction ..............................................19-18
19.3.3 The bypass Instruction ...........................................................19-18
19.3.4 The clamp Instruction .............................................................19-19
19.3.5 The hi-z Instruction .................................................................19-19
19.4 MPC801 Restrictions ........................................................................19-19
19.5 Nonscan Chain Operation ................................................................19-19
19.6 Motorola MPC801 BSDL Description ...............................................19-19
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TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
Section 20
Electrical Characteristics
20.1 Maximum Ratings (GND = 0V) ..........................................................20-1
20.2 Thermal Characteristics .....................................................................20-2
20.3 Power Considerations ........................................................................20-2
20.3.1 Layout Practices .......................................................................20-3
20.4 DC Electrical Specifications (V
20.5 MPC801 AC Electrical Specifications Control Timing ........................20-5
20.6 IEEE 1149.1 Electrical Specifications ..............................................20-26
Section 21
Communication Electrical Characteristics
= 3.0 – 3.6V) .................................20-4
CC
21.1 PIO AC Electrical Specifications ........................................................21-1
21.2 UART BRG Clock AC Electrical Specifications ..................................21-2
21.3 UART—External Clock AC Electrical Specifications ..........................21-3
21.4 UART—Internal Clock AC Electrical Specifications ...........................21-3
21.5 SPI Master AC Electrical Specifications .............................................21-5
21.6 SPI Slave AC Electrical Specifications ...............................................21-6
2
21.7 I
21.8 I
C AC Electrical Specifications–SCL < 100kHz ................................21-8
2
C AC Electrical Specifications–SCL > 100kHz ................................21-8
Section 22
Mechanical Specifications
22.1 Ordering Information ..........................................................................22-1
22.2 Pin Assignments – PBGA-Top View ..................................................22-2
22.3 Package Dimensions–Plastic Ball Grid Array (PBGA) .......................22-3
Section 23
Terminology
Appendix A
Quick Reference Guide to MPC801 Registers
A.1 Core Control Registers .........................................................................A-1
A.2 Internally Mapped Registers ................................................................A-4
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TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
AppendixB
Applications
B.1 MPC801 Basic Initialization ................................................................. B-1
B.1.1 Programming the UPM .............................................................. B-2
B.1.2 MPC801 MMU/Cache Example ................................................ B-5
B.1.2.1 Basic MMU and Cache Concept .................................... B-5
B.1.2.2 General Concept ............................................................ B-5
B.1.3 Memory Management Unit ........................................................ B-6
B.1.3.1 Memory Protection ....................................................... B-10
B.1.3.2 MMU Example ............................................................. B-10
B.1.4 M_TWB MMU TABLEWALK BASE REGISTER ..................... B-12
B.1.5 MI_CTR Instruction MMU Control Register ............................. B-12
B.1.6 Mx_AP Instruction/Data Access Protection Register .............. B-13
B.1.7 MD_CTR Data MMU Control Register .................................... B-14
B.1.8 Level One Descriptor Format Register .................................... B-15
B.1.9 Level Two Descriptor 1K Resolution Format Register ............ B-18
B.1.10 Level Two Descriptor 4K Resolution Format Register ............ B-20
B.2 Configuring the MPC801 Memory Controller .................................... B-26
B.2.1 General Configuration ............................................................. B-27
B.2.2 SRAM Configuration ................................................................ B-27
B.2.3 EPROM Configuration ............................................................. B-31
B.2.4 DRAM Configuration ............................................................... B-34
B.3 Porting to the PowerQUICC .............................................................. B-43
B.4 Using the PowerPC Core .................................................................. B-44
B.5 Bit Labeling ........................................................................................ B-44
B.5.1 Code Portability ....................................................................... B-44
B.6 Cache ................................................................................................ B-44
B.6.1 Cache Performance Impact ..................................................... B-44
B.6.2 Data Coherency ...................................................................... B-45
B.6.3 Debugging ............................................................................... B-45
B.7 Memory Management Unit ................................................................ B-45
B.8 Real-Time Operating Systems .......................................................... B-45
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xx
LIST OF ILLUSTRATIONS
Figure Page
Number Title Number
1-1. MPC801 Block Diagram ........................................................................1-4
1-2. MPC801 System Configuration .............................................................1-8
2-1. MPC801 External Signals .....................................................................2-1
4-1. Reset Configuration Basic Scheme .......................................................4-6
4-2. Reset Configuration Sampling Scheme For Short PORESET
Assertion ...............................................................................................4-7
4-3. Reset Configuration Sampling Scheme For Long PORESET
Assertion ...............................................................................................4-7
4-4. Reset Configuration Sampling Timing Requirements ...........................4-8
5-1. Clock Unit Block Diagram ......................................................................5-2
5-2. MPC801 Power Supply .........................................................................5-3
5-3. MPC801 Clocks Timing Diagram ..........................................................5-4
5-4. System PLL Block Diagram ...................................................................5-7
5-5. General System Clocks Select ..............................................................5-9
5-6. Divided System Clocks Timing Diagram .............................................5-10
5-7. MPC801 Clocks For DFNH = 1 or DFNL = 0 Timing Diagram ............5-11
5-8. MPC801 Low-Power Modes Flowchart ...............................................5-19
5-9. MPC801 Basic Power Supply Configuration .......................................5-22
5-10. External Power Supply Scheme (2.0 V Internal Voltage) ....................5-23
5-11. Key Mechanism Diagram ....................................................................5-24
6-1. Core Block Diagram ..............................................................................6-3
6-2. Instruction Flow Conceptual Diagram ...................................................6-3
6-3. Basic Instruction Pipeline Timing Diagram ............................................6-4
6-4. Sequencer Data Path ............................................................................6-5
6-5. History Buffer Queue .............................................................................6-9
6-6. Load/Store Unit Functional Block Diagram .........................................6-26
6-7. Number of Bus Cycles Needed For Unaligned, Single Register
Fixed-Point Load/Store Instructions ....................................................6-28
6-8. Number of Bus Cycles Needed For String Instruction Execution .......6-30
MPC801 USER’S MANUAL
MOTOROLA
LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
8-1. Example of a Data Cache Load ............................................................8-4
8-2. Example of a Writeback Arbitration .......................................................8-5
8-3. Another Example of a Writeback Arbitration .........................................8-5
8-4. Example of a Private Writeback Bus Load ............................................8-6
8-5. Example of an External Load ................................................................8-7
8-6. Example of a Full History Buffer ............................................................8-8
8-7. Example of Branch Folding ...................................................................8-9
8-8. Example of Branch Prediction .............................................................8-10
9-1. Instruction Cache Organization .............................................................9-2
9-2. Cache Data Path Block Diagram ...........................................................9-3
10-1. Data Cache Organization ....................................................................10-2
11-1. Effective to Real Address Translation For 4K Pages ..........................11-3
11-2. Two Level Translation Table When MD_CTR(TWAM) = 1 .................11-5
11-3. Two Level Translation Table When MD_CTR(TWAM) = 0 .................11-6
12-1. System Configuration and Protection Logic ........................................12-3
12-2. MPC801 Interrupt Structure ................................................................12-4
12-3. Interrupt Table Handling Example .......................................................12-9
12-4. RTC Block Diagram ...........................................................................12-12
12-5. Periodic Interrupt Timer Block Diagram ............................................12-12
12-6. Software Watchdog Timer Service State Diagram ............................12-14
12-7. Software Watchdog Timer Block Diagram ........................................12-15
13-1. Input Sample Window .........................................................................13-2
13-2. MPC801 Bus Signals ..........................................................................13-3
13-3. Basic Transfer Protocol .......................................................................13-8
13-4. Simplified Diagram of a Single Beat Read Cycle ................................13-9
13-5. Single Beat Read Cycle–Basic Timing–Zero Wait States .................13-10
13-6. Single Beat Read Cycle–Basic Timing–One Wait State ...................13-11
13-7. Simplified Flow Diagram of a Single Beat Write Cycle ......................13-12
13-8. Single Beat Write Cycle–Basic Timing–Zero Wait States .................13-13
13-9. Single Beat Write Cycle–Basic Timing–One Wait State ....................13-14
13-10. Single Beat–32-Bit Data–Write Cycle–16-Bit Port Size Basic
Timing ................................................................................................13-15
13-11. Simplified Flow Diagram Of A Burst Read Cycle ..............................13-17
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LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
13-12. Burst-Read Cycle–32-Bit Port Size–Zero Wait State ........................13-18
13-13. Burst-Read Cycle–32-Bit Port Size–One Wait State .........................13-19
13-14. Burst-Read Cycle–32-Bit Port Size–Wait States Between Beats .....13-20
13-15. Burst-Read Cycle–16-Bit Port Size–One Wait State Between
Beats ................................................................................................. 13-21
13-16. Simplified Flow Diagram of a Burst Write Cycle ................................13-22
13-17. Burst Write Cycle–32-Bit Port Size–Zero Wait States .......................13-23
13-18. Burst-Inhibit Cycle–32-Bit Port Size ..................................................13-24
13-19. Internal Operand Representation ......................................................13-25
13-20. Interface To Different Port Size Devices ...........................................13-26
13-21. Bus Arbitration Flowchart ..................................................................13-28
13-22. Basic Connection of the Master Signal .............................................13-29
13-23. Bus Arbitration Timing Diagram ........................................................13-30
13-24. Internal Bus Arbitration State Machine ..............................................13-31
13-25. Termination Signals Protocol Basic Connection ...............................13-36
13-26. Termination Signals Protocol Timing Diagram ..................................13-37
13-27. Reservation On A Local Bus .............................................................13-38
13-28. Reservation On Multilevel Bus Hierarchy ..........................................13-39
13-29. Retry Transfer Timing–Internal Arbiter ..............................................13-41
13-30. Retry Transfer Timing–External Arbiter .............................................13-42
13-31. Retry On Burst Cycle ........................................................................13-43
14-1. General MPC801 System Diagram .....................................................14-2
15-1. Memory Controller Block Diagram ......................................................15-2
15-2. MPC801 Simple System Configuration ...............................................15-4
15-3. Memory Controller Machine Selection ................................................15-5
15-4. Memory Controller Basic Operation ....................................................15-6
15-5. MPC801 GPCM–Memory Devices Interface .......................................15-8
15-6. MPC801 GPCM–Memory Device Basic Timing
(ACS = 00,TRLX = 0) ..........................................................................15-9
15-7. MPC801 GPCM–Peripheral Device Interface .....................................15-9
15-8. MPC801 GPCM–Peripheral Device Basic Timing
(ACS = 10, ACS = 11,TRLX = 0) ......................................................15-10
15-9. MPC801 GPCM–Relaxed Timing–Read Access
(ACS = 10, ACS = 11, SCY = 1, TRLX =1) .......................................15-11
15-10. MPC801 GPCM–Relaxed Timing–Write Access
(ACS = 10, ACS = 11, SCY = 0, CSNT = 0, TRLX =1) .....................15-11
15-11. MPC801 GPCM–Relaxed Timing–Write Access
(ACS = 10, ACS = 11, SCY = 0, CSNT = 1, TRLX =1) .....................15-12
xxii
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MOTOROLA
LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
15-12. MPC801 GPCM–Relaxed Timing–Write Access
(ACS = 00, SCY = 0, CSNT = 1, TRLX =1 ........................................15-12
15-13. MPC801 Consecutive Accesses Write
After Read–(ORx-EHTR = 0) ............................................................15-13
15-14. MPC801 Consecutive Accesses Write
After Read–(ORx-EHTR = 1) ............................................................15-14
15-15. MPC801 Consecutive Accesses Read After Read From
Different Banks–(ORx-EHTR = 1) .....................................................15-14
15-16. MPC801 Consecutive Accesses Read After Read From
Same Bank– (ORx-EHTR = 1) ..........................................................15-15
15-17. MPC801–Simple 128K SRAM Configuration ....................................15-16
15-18. MPC801–Asynchronous External Master Configuration For
GPCM–Handled Memory Devices ....................................................15-17
15-19. Asynchronous Master GPCM–Memory Devices
Basic Timing (TRLX = 0) ...................................................................15-18
15-20. General Description of a UPM ...........................................................15-19
15-21. Memory Periodic Timer Request Block Diagram ..............................15-20
15-22. Memory Controller UPM Clock Scheme
(For System_To CLKOUT Division Factor 1–EBDF = 00) ................15-21
15-23. Memory Controller UPM Clock Scheme
(For System_To CLKOUT Division Factor 2–EBDF = 01) ................15-21
15-24. UPM Signals Timing Example
(For System_To CLKOUT Division Factor 1–EBDF = 00) ................15-22
15-25. UPM Signals Timing Example
(For System_To CLKOUT Division Factor 2–EBDF = 01) ................15-23
15-26. UPM External Signal Generation ......................................................15-24
15-27. RAM Word Structure .........................................................................15-25
15-28. CS Signal Control Model ...................................................................15-28
15-29. Byte Select Control Model .................................................................15-29
15-30. UPM Data Handling In Read Accesses .............................................15-36
15-31. UPM Wait Mechanism Timing For Internal and External
Synchronous Masters 1........................................................................5-38
15-32. UPM Wait Mechanism Timing For An External Asynchronous
Master ...............................................................................................15-39
15-33. MPC801–DRAM Interface Connection ..............................................15-40
15-34. Address Start Pointers of the UPM RAM Array .................................15-41
15-35. Single Beat Read Access To Page Mode DRAM ..............................15-43
15-36. Single Beat Write Access To Page Mode DRAM ..............................15-44
15-37. Burst Read Access To Page Mode DRAM (No LOOP) .....................15-45
15-38. Burst Read Access To Page Mode DRAM (LOOP) ..........................15-46
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LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
15-39. Burst Write Access To Page Mode DRAM (No LOOP) .....................15-47
15-40. Refresh Cycle (CBR) To Page Mode DRAM ....................................15-48
15-41. Exception Cycle ................................................................................15-49
15-42. Page Mode DRAM Burst Read Access
(Data Sampling on Falling Edge of CLKOUT) ...................................15-51
15-43. EDO Interface Connection ................................................................15-52
15-44. Single Beat Read Access To Page Mode DRAM With Extended
Data-Out ............................................................................................15-53
15-45. Single Beat Write Access To Page Mode DRAM With Extended
Data-Out ............................................................................................15-54
15-46. Burst Read Access To Page Mode DRAM With Extended
Data-Out ............................................................................................15-55
15-47. Burst Write Access To Page Mode DRAM With Extended
Data-Out ............................................................................................15-56
15-48. Refresh Cycle (CBR) To Page Mode DRAM With Extended
Data-Out ............................................................................................15-57
15-49. Exception Cycle For Page Mode DRAM With Extended
Data-Out ............................................................................................15-58
15-50. Synchronous External Master Basic Access (GPCM Controlled) .....15-62
15-51. Asynchronous External Master Basic Access (GPCM Controlled) ...15-63
15-52. Synchronous External Master–MPC801–DRAM Device
Typical Configuration ........................................................................15-64
15-53. Synchronous External Master–Burst Read Access To Page
Mode DRAM ......................................................................................15-65
15-54. Asynchronous External Master–MPC801–DRAM Device
Typical Configuration ........................................................................15-66
15-55. Asynchronous External Master–Read Access To Page Mode
DRAM ................................................................................................15-67
15-56. Blank Worksheet for a UPM ..............................................................15-85
16-1. UART Block Diagram ..........................................................................16-1
16-2. SPI Block Diagram ............................................................................16-16
16-3. SPI Transfer Format with CP = 0 ......................................................16-21
16-4. SPI Transfer Format with CP = 1 ......................................................16-22
2
16-5. I
xxiv
C Controller Block Diagram ............................................................16-27
MPC801 USER’S MANUAL
MOTOROLA
LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
18-1. Watchpoints and Breakpoint Support ................................................18-10
18-2. Partially Supported Watchpoints/Breakpoint Example ......................18-14
18-3. Instruction Support General Structure ...............................................18-16
18-4. Load/Store Support General Structure ..............................................18-19
18-5. Relationship Between the Core and Debug Mode ............................18-21
18-6. Debug Mode Logic Implementation ...................................................18-23
18-7. Debug Mode Reset Configuration Timing Diagram ...........................18-25
18-8. Development Port/BDM Connector Pinout Options ..........................18-30
18-9. Asynchronous Clocked Serial Communications Timing Diagram .....18-33
18-10. Synchronous Self-Clocked Serial Communications Timing
Diagram ............................................................................................. 18-34
18-11. Enabling Clock Mode Following Reset Timing Diagram ...................18-35
18-12. Example of Download Procedure Code ............................................18-39
18-13. Slow Download Procedure Loop .......................................................18-40
18-14. Fast Download Procedure Loop ........................................................18-40
19-1. Test Logic Block Diagram ...................................................................19-2
19-2. TAP Controller State Machine .............................................................19-3
19-3. Output Pin Cell (O.Pin) ........................................................................19-4
19-4. Observe-Only Input Pin Cell (I.Obs) ....................................................19-4
19-5. Output Control Cell (IO.CTL) ...............................................................19-5
19-6. General Arrangement of Bidirectional Pin Cells ..................................19-5
19-7. Bypass Register ................................................................................19-18
20-1. External Clock Timing Diagram .........................................................20-10
20-2. Synchronous Output Signals Timing Diagram ..................................20-11
20-3. Synchronous Active Pull-Up And Open-Drain Outputs Signals
Timing Diagram .................................................................................20-12
20-4. Synchronous Input Signals Timing Diagram .....................................20-12
20-5. Input Data In Normal Case Timing Diagram .....................................20-13
20-6. Input Data Timing When Controlled By The UPM In The
Memory Controller .............................................................................20-13
20-7. External Bus Read Timing Diagram
(GPCM Controlled–ACS = ‘00’) .........................................................20-14
20-8. External Bus Read Timing Diagram
(GPCM Controlled–TRLX = ‘0’ ACS = ‘10’) .......................................20-14
20-9. External Bus Read Timing Diagram
(GPCM Controlled–TRLX = ‘0’ ACS = ‘11’) .......................................20-15
20-10. External Bus Read Timing Diagram
(GPCM Controlled–TRLX = ‘1’, ACS = ‘10’, ACS = ‘11’) ...................20-15
MOTOROLA
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LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
20-11. External Bus Write Timing Diagram
(GPCM Controlled–TRLX = ‘0’, CSNT = ‘0’) .....................................20-16
20-12. External Bus Write Timing Diagram
(GPCM Controlled–TRLX = ‘0’, CSNT = ‘1’) .....................................20-16
20-13. External Bus Write Timing Diagram
(GPCM Controlled–TRLX = ‘1’, CSNT = ‘1’) .....................................20-17
20-14. External Bus Timing Diagram (UPM Controlled Signals) ..................20-18
20-15. Asynchronous UPWAIT Asserted Detection In
UPM Handled Cycles Timing Diagram ..............................................20-19
20-16. Asynchronous UPWAIT Negated Detection In
UPM Handled Cycles Timing Diagram ..............................................20-19
20-17. Synchronous External Master Access Timing Diagram
(GPCM Handled ACS = ‘00’) ............................................................20-20
20-18. Asynchronous External Master Memory Access Timing Diagram
(GPCM Controlled–ACS = ’00’) ........................................................20-20
20-19. Asynchronous External Master Timing Diagram
(Control Signals Negation Time) .......................................................20-21
20-20. Interrupt Detection Timing Diagram
for External Level-Sensitive Lines .....................................................20-21
20-21. Interrupt Detection Timing Diagram
for External Edge-Sensitive Lines .....................................................20-22
20-22. Debug Port Clock Input Timing Diagram ...........................................20-22
20-23. Debug Port Timing Diagram ..............................................................20-23
20-24. Reset Timing Diagram (Configuration From Data Bus) ....................20-24
20-25. Reset Timing Diagram–MPC801 Data Bus Weak Drive
During Configuration .........................................................................20-25
20-26. Reset Timing Diagram–Debug Port Configuration ............................20-25
20-27. JTAG Test Clock Input Timing Diagram ............................................20-26
20-28. JTAG–Test Access Port Timing Diagram .........................................20-27
20-29. JTAG–TRST Timing Diagram ...........................................................20-27
20-30. Boundary Scan (JTAG) Timing Diagram ...........................................20-28
21-1. Parallel I/O Data-In/Data-Out Timing Diagram ....................................21-1
21-2. Baud Rate Generator from UART–Timing ..........................................21-2
21-3. UART Receive ....................................................................................21-4
21-4. UART Transmit ...................................................................................21-4
21-5. SPI Master (CP=0) ..............................................................................21-5
21-6. SPI Master (CP=1) ..............................................................................21-6
21-7. SPI Slave (CP=0) ................................................................................21-7
21-8. SPI Slave (CP=1) ................................................................................21-7
2
21-9. I
xxvi
C Bus Timing ....................................................................................21-9
MPC801 USER’S MANUAL
MOTOROLA
LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
B-1. General System Configuration ........................................................... B-27
B-2. SRAM Read Timing Analysis ............................................................. B-30
B-3. SRAM Write Timing Analysis ............................................................. B-30
B-4. EPROM 1 Wait State Read ................................................................ B-32
B-5. UPM Signal Timings ........................................................................... B-35
B-6. UPM RAM Configuration .................................................................... B-36
B-7. DRAM 3-Cycle Read .......................................................................... B-38
B-8. DRAM 3-Cycle Write .......................................................................... B-41
B-9. Burst Read Access ............................................................................. B-42
B-10. Write Burst Access ............................................................................. B-43
MOTOROLA
MPC801 USER’S MANUAL
xxvii
LIST OF TABLES
Table Page
Number Title Number
2-1. Signal Descriptions ................................................................................2-2
2-2. Pin Breakout ........................................................................................2-10
3-1. MPC801 Internal Memory Map .............................................................3-1
4-1. Possible Reset Results .........................................................................4-1
5-1. Reset Clocks Source Configuration ......................................................5-5
5-2. tmbclk Divisions .....................................................................................5-6
5-3. XFC Capacitor Values .........................................................................5-13
5-4. MPC801 Low-Power Modes ................................................................5-18
6-1. Branch Prediction Policy .......................................................................6-6
6-2. “Before” and “After” Interrupts ...............................................................6-8
6-3. Special Ports to the Machine State Register Bits ................................6-11
6-4. Interrupt Latency .................................................................................6-11
6-5. Detection Order of Instruction-Related Interrupts ................................6-14
6-6. Interrupt Priorities Mapping .................................................................6-14
6-7. Standard Special-Purpose Registers ..................................................6-15
6-8. Standard Timebase Register Mapping ................................................6-16
6-9. Additional Special-Purpose Registers .................................................6-16
6-10. Other Control Registers .......................................................................6-18
6-11. Encoding of Special Registers Located Outside the Core ..................6-19
6-12. Address of Special Registers Located Outside the Core ....................6-19
6-13. Load/Store Instructions Timing ............................................................6-30
6-14. DAR, BAR, and DSISR Value Summary .............................................6-31
7-1. Offset of First Instruction by Interrupt Type ...........................................7-8
8-1. Instruction Execution Timing .................................................................8-1
9-1. IC_ADR Bits Functionality for the Cache Read Command .................9-10
9-2. IC_DAT Bit Layout When Reading a Tag ............................................9-11
xxviii
MPC801 USER’S MANUAL
MOTOROLA
LIST OF TABLES (Continued)
Table Page
Number Title Number
10-1. DC_ADR Bit Functionality for Reading the Cache ..............................10-6
10-2. DC_DAT Bit Layout For Reading a Tag ..............................................10-7
11-1. Number of Effective Address Bits Replaced By Real Address Bits .....11-7
11-2. Number of Identical Entries Required in the Level One Table ............11-7
11-3. Number of Identical Entries Required in the Level Two Table ............11-7
11-4. Level One (Segment) Descriptor Format ............................................11-8
11-5. Level Two (Page) Descriptor Format ..................................................11-9
12-1. Priority of System Interface Unit Interrupt Sources .............................12-5
12-2. Multiplexing Control ...........................................................................12-16
12-3. Standard Timebase Register Mapping ..............................................12-24
13-1. MPC801 System Interface Unit Signals ..............................................13-4
13-2. Data Bus Requirements For Read Cycles ........................................13-26
13-3. Data Bus Contents for Write Cycles ..................................................13-27
13-4. BURST/TSIZE Encoding ...................................................................13-33
13-5. Definitions of Address Types .............................................................13-34
13-6. Termination Signal Protocol ..............................................................13-36
14-1. PowerPC Little-Endian Effective Address Modification For
Individually Aligned Scalar ..................................................................14-1
14-2. Endian Mode Programming For Core Data Structures .......................14-1
14-3. Little-Endian Program/Data Path Between the Register and
32-Bit Memory .....................................................................................14-3
14-4. Little-Endian Program/Data Path Between the Register and
16-Bit Memory .....................................................................................14-3
14-5. Little-Endian Program/Data Path Between the Register and
8-Bit Memory .......................................................................................14-4
15-1. Boot Bank Field Values After Reset ..................................................15-16
15-2. UPM RAM Word ................................................................................15-25
15-3. Byte Select Enable Function .............................................................15-30
15-4. Loop Field For UPM Service Requests .............................................15-31
15-5. Address Multiplexing .........................................................................15-32
15-6. AMA/AMB Definition For DRAM Interfaces .......................................15-33
15-7. UPM Start Address Locations ...........................................................15-39
15-8. UPM RAM Word Bit Field Example ...................................................15-40
MOTOROLA
MPC801 USER’S MANUAL
xxix
LIST OF TABLES (Continued)
Table Page
Number Title Number
15-9. UPM RAM Word Bit Field Example ...................................................15-50
15-10. EDO Connection Field Value Example .............................................15-52
15-11. GPL5 Signal Behavior .......................................................................15-60
16-1. Typical Baud Rates of Asynchronous Communication .....................16-13
16-2. Port B Pin Assignment ......................................................................16-36
18-1. VF Pin Encoding .................................................................................18-4
18-2. Detecting the Trace Buffer Starting Point ............................................18-7
18-3. Fetch Show Cycle Control ...................................................................18-8
18-4. Instruction Watchpoints Programming Options .................................18-17
18-5. Load/Store Data Events ....................................................................18-18
18-6. Load/Store Watchpoint Programming Options ..................................18-18
18-7. Checkstop State and Debug Mode ...................................................18-27
18-8. Trap Enable Data Shifted Into Development Port Shift Register ......18-36
18-9. Debug Port Command Shifted Into the Development Port
Shift Register .....................................................................................18-36
18-10. Status/Data Shifted Out of the Development Port
Shift Register .....................................................................................18-37
18-11. Debug Instructions/Data Shifted Into the Development Port
Shift Register .....................................................................................18-38
18-12. Development Support Register Protection ........................................18-41
19-1. Boundary Scan Bit Definition ..............................................................19-6
19-2. Instruction Decoding .........................................................................19-17
20-1. Bus Operation Timing .........................................................................20-6
20-2. Interrupt Timing .................................................................................20-21
20-3. Debug Port Timing ............................................................................20-22
20-4. Reset Timing .....................................................................................20-23
20-5. JTAG Timing .....................................................................................20-26
A-1. Standard Special-Purpose Registers ....................................................A-2
A-2. Standard Timebase Register Mapping ..................................................A-2
A-3. Added Special-Purpose Registers ........................................................A-3
A-4. Other Control Registers ........................................................................A-4
A-5. MPC801 Internal Memory Map .............................................................A-5
xxx
MPC801 USER’S MANUAL
MOTOROLA
LIST OF TABLES (Continued)
Table Page
Number Title Number
B-1. Read Single Beat–RSSA ...................................................................... B-3
B-2. Write Single Beat–WSSA ..................................................................... B-3
B-3. Read Burst Cycle–RBSA ...................................................................... B-3
B-4. Write Burst Cycle–WBSA ..................................................................... B-3
B-5. Refresh Cycle–RBSA ........................................................................... B-4
B-6. Exception Cycle–ECSA ........................................................................ B-4
B-7. Physical Memory Map Example ......................................................... B-11
B-8. MMU Register .................................................................................... B-11
B-9. Option Register .................................................................................. B-28
B-10. Base Register ..................................................................................... B-28
B-11. UPM Word Structure .......................................................................... B-34
MOTOROLA
MPC801 USER’S MANUAL
xxxi
1
SECTION 1
INTRODUCTION
The MPC801 PowerPC
™
Quad Integrated Communications Controller (PowerQUICC) is a
versatile one-chip integrated microprocessor and peripheral combination that can be used
in a variety of controller applications. It is a low-cost version of the MPC860 that provides an
effective price/performance solution across a wide range of applications. The MPC801, like
the MPC860, combines a high-performance PowerPC core with a multifaceted system
integration package. Unless otherwise specified, the PowerQUICC unit will be referred to as
the MPC801 in this manual.
The MPC801 is a PowerPC-based derivative of Motorola’s MC68360 Quad Integrated
™
Communications Controller (QUICC
). The CPU on the MPC801 is a 32-bit PowerPC
implementation that incorporates memory management units and instruction and data
caches. The memory controller has been enhanced, thus enabling the MPC801 to support
any type of memory, including high performance memories and newer dynamic random
access memories (DRAMs).
The purpose of this manual is to describe the operation of all the MPC801 functionality with
concentration on the I/O functions. Additional details on the MPC801 can be found in the
PowerPC architectural specifications.
1.1 FEATURES
The following list summarizes the main features of the MPC801:
• PowerPC Single-Issue Integer Core Performs Branch Folding and Prediction with
Conditional Prefetch, but Without Conditional Execution
• Precise Exception Model
• Extensive System Development Support
— On-chip watchpoints and breakpoints
— Program flow tracking
— On-chip emulation (OnCE) development interface
• High Performance (52K Dhrystone 2.1 MIPS @40MHz, 3.3V, 1.3W Total Power)
• Low Power (3.3V Operation with 5V TTL Compatibility)
• MPC8XX PowerPC System Interface, Including a Periodic Interrupt Timer, a Bus
Monitor, and Real-Time Clocks
• Fully Static Design (0-40MHz Operation)
MOTOROLA
MPC801 USER’S MANUAL
1-1
Introduction
1
• Four Major Power-Saving Modes
— Full on, doze, sleep, and deep sleep
— Gear mode
• 256-Pin Ball Grid Array Packaging
• 26-Bit Address Bus and 32-bit Data Bus
— Supports multiple master designs
— Four-beat transfer bursts, two-clock minimum bus transactions
— Dynamic bus sizing controlled by on-chip memory controller
— Supports data parity
— Tolerates 5V inputs and provides 3.3V outputs
• Flexible Memory Management
— 8-entry, fully associative instruction translation lookaside buffers (TLBs)
— 8-entry, fully associative data translation lookaside buffers
— 4K, 16K, 512K, or 8M page size support
— 1K protection granularity
— Support for multiple protection groups and tasks
— Attribute support for trapping, writethrough, cache inhibit, and memory-mapped I/O
— Supports software tablewalk
• 1K Physical Address, Two-Way, Set-Associative Data Cache
— Single-cycle access on hit
— 4-word line size, burst fill, least recently used (LRU) replacement
— Cache lockable on line granularity
— Read capability of all tags and attributes provided for debugging purposes
• 2K Physical Address, Two-Way, Set-Associative Instruction Cache
— Single-cycle access on hit
— Four-word line size, burst fill, least recently used replacement
— Cache lockable on line granularity
— Cache control supports PowerPC invalidate instruction
— Cache inhibit supported for the entire cache or per memory management unit page
in conjunction with memory management logic
— Read capability of all tags and attributes provided for debugging purposes
• Memory Controller with Eight Banks
— Glueless interface to SRAM, DRAM, EPROM, FLASH and other peripherals
— Byte write enables and selectable parity generation
— 32-bit address decodes with bit masks
— Each bank can be a chip-select or RAS
to support a DRAM bank
— Maximum of 30 programmable wait states per bank
— Programmable DRAM controller supports most size and speed memory interfaces
— Four CAS
lines, four WE lines, and one OE line
— Boot chip-select available at reset (optional 8-, 16-, or 32-bit memory)
— Variable block sizes (32K to 256M)
— Selectable write protection
1-2
MPC801 USER’S MANUAL
MOTOROLA
Introduction
• System Interface Unit
— Clock synthesizer
— Power management
— Reset controller
— PowerPC decrementer and timebase
— Real-time clock register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
— Low-power stop mode
— On-chip bus arbitration logic
• Interrupt Support
— Eight external interrupt request lines
— Internal interrupt sources
• UART Support
— Two UARTs
— Standard baud rates of 300bps to 115.2kbps with 16 × sample clock
— External 1 × clock for high-speed synchronous communication
— Flexible 5-wire serial interface
— Direct support of IrDA physical layer protocol
— 8-byte FIFOs for transmit and receive
— Programmable data format:
— Programmable channel modes (normal and local loopback)
— Parity, framing, and overrun error detection
— Generation and detection of break
— Robust receiver data sampling with noise filtering
— Eight maskable interrupts
— Low-power idle mode
1
2
®
C
Support
•I
— Two-wire interface (SDA and SCL)
— Full-duplex operation
— Master or slave I
2
C mode support
— Multimaster environment support
— Clock rate support at a maximum of 520KHz, assuming a 25MHz system clock
— Local loopback capability for testing
• Serial Peripheral Interface Support
— Four-wire interface (SPIMOSI, SPIMISO, SPICLK, and SPISEL
)
— Full-duplex operation
— 8- and 16-bit data character operation
— Back-to-back character transmission and reception support
— Master or slave serial peripheral interface mode support
— Multimaster environment support
MOTOROLA
MPC801 USER’S MANUAL
1-3
Introduction
1
— Clock rates support at a maximum of 6.25MHz in master mode and 12.5MHz in
slave mode (assuming a 25MHz system clock)
— Independent programmable baud rate generator
— Programmable clock phase and polarity
— Open-drain output pins support multimaster configuration
— Local loopback capability for testing
• Debug Interface Support
— Eight comparators
— Supports =, ≠ , <, and > conditions
— Each watchpoint can generate a breakpoint internally
1.2 MPC801 ARCHITECTURE
The MPC801 is a combination of the embedded PowerPC core and integrated peripherals
brought together to meet the demands of various communications and networking products.
The MPC801 is comprised of six modules that all use the 32-bit internal bus:
• An embedded PowerPC core
• A system interface unit
• Two UARTs
2
• An I
• A serial peripheral interface
The MPC801 block diagram is illustrated in Figure 1-1.
C controller
1-4
I-CACHE
EMBEDDED
POWERPC
CORE
INSTRUCTION
BUS
LOAD/STORE
BUS
I-MMU
D-CACHE
D-MMU
Figure 1-1. MPC801 Block Diagram
MPC801 USER’S MANUAL
SYSTEM
INTERFACE UNIT
SYSTEM
FUNCTIONS
BIU
MEMORY
CONTROLLER
UART
UART
I2C
SPI
PIO
MOTOROLA
Introduction
1.2.1 The Embedded PowerPC Core
The embedded PowerPC core complies with the specifications discussed in the
Family: The Programming Environment (MPCFPE/D)
Motorola. The core has a fully static design that consists of two functional blocks—the
integer block and load/store block. It executes all integer and load/store operations directly
on the hardware. The core supports integer operations on a 32-bit internal data path with
32-bit arithmetic hardware. The interface to the internal and external buses is 32 bits.
The core uses a 2-instruction load/store queue, a 4-instruction prefetch queue, and a
6-instruction history buffer. It does branch folding and prediction with conditional prefetch,
but does not support conditional execution. The core can operate on 32-bit external
operands with one bus cycle. The PowerPC integer block supports 32 × 32-bit fixed-point
general-purpose registers and it can execute one integer instruction per clock cycle.
The embedded PowerPC core is integrated with the memory management unit as well with
the instruction and data caches. Each memory management unit (MMU) provides an
8-entry, fully associative instruction and data TLB, with 4K, 16K, 512K, and 8M page sizes.
It supports 16 virtual address spaces with 16 protection groups. Three special registers are
available as scratch registers to support software tablewalk and update.
The instruction cache is 2K, two way, set associative with physical addressing. It allows
single-cycle access on hit with no added latency for miss. It has four words per line
supporting burst line fill using least recently used replacement. The cache can be locked on
a per line basis for application critical routines. The cache inhibit mode can be programmed
on a per MMU page basis.
manual that is available from
PowerPC
1
The data cache is 1K, two way, set associative with physical addressing. It allows
single-cycle access on hit with one added clock latency for miss. It has four words per line,
supporting burst line fill using LRU replacement. The cache can be locked on a per line basis
for application critical data. The data cache can be programmed to support copyback or
writethrough via the memory management unit. The cache inhibit mode can be programmed
on a per MMU page basis. The PowerPC core, together with its instruction and data caches,
delivers approximately 52 MIPS at 40MHz using Dhrystone 2.1.
The core contains a debug interface that provides superior debug capabilities without
causing any degradation in the speed of operation. This interface supports six watchpoint
pins that are used to detect software events. Internally, it has eight comparators, four of
which operate on the effective address of the address bus. The remaining four comparators
are split—two comparators operate on the effective address of the data address bus and
two operate on the data bus. The core can compare using the =, ≠ , <, and > conditions to
generate watchpoints. Then each watchpoint can generate a breakpoint that can be
programmed to trigger after a certain number of events.
MOTOROLA
MPC801 USER’S MANUAL
1-5
Introduction
1
1.2.2 The System Interface Unit
The system interface unit (SIU) on the MPC801 integrates general-purpose features useful
in almost any 32-bit processor system, thus enhancing the performance provided by the
system integration module on the MC68360 QUICC device. Multiple bus port sizes are
supported and bus sizing allows 8-, 16-, and 32-bit peripherals and memory to exist in the
32-bit system bus mode. Data parity is supported using 4-bit data parity and the parity type
can be odd or even. The system interface unit also contains power management functions,
reset control, decrementer, timebase, and real-time clock.
The memory controller manages memories with a nonmultiplexed address bus using the
SRAM interface. Using the DRAM interface, the memory controller also manages memories
with a multiplexed address bus (DRAM, SRDRAM, and EDO). Both submodules support
glueless interface to 8-, 16-, and 32-bit wide memories. The memory controller supports up
to eight memory banks and can use address type matching to qualify the memory bank
accesses. Each bank can use either the SRAM or DRAM interface. The memory controller
provides four byte enable signals, one output enable signal, and one boot chip-select
available at reset.
The SRAM interface provides block sizes that vary between 32K to 64M. Each bank of
memory has 0 to 30 wait states (zero wait state means a two-clock access to external
SRAM). The DRAM interface supports 256K, 512K, 1M, 2M, 4M, 8M, 16M, 32M, or 64M
memory bank depths for all port sizes. The memory depth can be defined as 64K and 128K
for 8-bit memory or 128M and 256M for 32-bit memory. The DRAM controller supports page
mode access for successive transfers within bursts.
The MPC801 supports a glueless interface to one bank of DRAM, but external buffers are
required for additional memory banks. The refresh unit provides CAS
programmable refresh timer, disable refresh mode, and stacking for seven refresh cycles.
The DRAM interface uses a programmable state machine to support most memory
interfaces.
before RAS, a
1.2.3 The UART Controller
Each communication channel has a full-duplex universal asynchronous receiver/transmitter
(UART). The operating frequency for each receiver and transmitter can be selected
independently from the baud rate generator, counter/timer, or external clock. The transmitter
accepts parallel data from the core, converts it to a serial bitstream, inserts the appropriate
START, STOP, or optional PARITY bits, and then outputs a composite serial stream of data
on the TxD output pin. The receiver accepts the serial data on the RxD pin, converts it to
parallel format, checks for a START bit, STOP bit, PARITY bit (if any), or break condition,
and transfers an assembled character to the core during read operations.
1-6
MPC801 USER’S MANUAL
MOTOROLA
Introduction
1.2.4 The I2C
2
The I
C controller is a synchronous, multimaster bus that is used to connect several
®
Controller
integrated circuits on a board. It uses two wires to carry information between the integrated
2
circuits that are connected to the bus. The I
C controller consists of transmitter and receiver
sections, an independent baud rate generator, and a control unit. The transmitter and
receiver sections use the same clock that is derived from the I
2
C controller baud rate
generator in master mode and generated externally in slave mode.
1.2.5 The Serial Peripheral Interface Controller
The serial peripheral interface (SPI) is a full-duplex, synchronous, character-oriented
channel that supports a four-wire interface (receive, transmit, clock and slave select). The
serial peripheral interface block consists of transmitter and receiver sections, an
independent baud rate generator, and a control unit. The transmitter and receiver sections
use the same clock that is derived from the SPI baud rate generator in master mode and
generated externally in slave mode. During an serial peripheral interface transfer, data is
simultaneously transmitted and received.
1.3 POWER MANAGEMENT
The MPC801 supports a wide range of power management features, including full-on, doze,
sleep, deep sleep, and low-power stop. In full-on mode, the MPC801 processor is fully
powered with all internal units operating at full speed. A gear mode is provided that allows
the operating system to reduce the operational frequency of the processor. Doze mode
disables core functional units, except for the timebase, decrementer, phase locked loop,
memory controller, and real-time clock. Sleep mode disables everything, except the realtime clock and periodic interrupt timer, thus leaving the phase locked loop active for quick
wake-up. The deep sleep mode disables the phase locked loop for low-power, but at the
expense of a slower wake-up. Low-power stop disables all logic in the processor (except the
minimum logic required to restart the device) and lowers the power consumption, but it also
requires the longest wake-up time.
1
1.4 MPC801 APPLICATIONS
The MPC801 device is specifically designed to be a general-purpose, low-cost entry point
to the embedded PowerPC Family at Motorola. The device excels in applications that
require the performance of a single-issue PowerPC core with moderate amounts of data and
instruction cache. It can support alternate bus masters in addition to providing all the basic
features of glueless memory connections, but does not provide much in the way of serial
connectivity. Instead, it supplies simple UART serial channels as well as I
peripheral interface channels for onboard communication to other peripheral chips.
The MPC801 excels in low-power and portable applications because of its expansive
power-down modes. In addition, the normal operation current is low. The MPC801 is ideal
for applications where a significant portion of your added value is in peripherals or ASICs
and a low-cost general-purpose core is required. The programmable flexibility of the
memory controller ensures that the board design can accommodate future memory types
without hardware changes, thus enabling the ASIC to concentrate on other system goals.
MOTOROLA
MPC801 USER’S MANUAL
2
C and serial
1-7
Introduction
1
1.5 DIFFERENCES BETWEEN THE MPC801 AND MPC860
The MPC801 can be considered a subset of the standard MPC860 device. The following
modifications were made to the MPC860 to create the MPC801:
• The 4K instruction cache was reduced to 2K
• The 4K data cache was reduced to 1K
• The 32-bit instruction and data memory management units were reduced to eight TLB
entries each
• The 32-bit address bus was reduced to 26 bits
• PCMCIA support was eliminated
• All existing serial interface logic and their respective DMAs was replaced with two
UARTs, one I
modeled after the MC68328 DragonBall
2
C, and a serial peripheral interface (all non-DMA based). The UARTs are
™
device.
1.6 MPC801 GLUELESS SYSTEM DESIGN
A fundamental design goal of the MPC801 was to have a flexible interface to other system
components. Figure 1-2 illustrates a system configuration that offers one flash EPROM and
supports DRAM SIMM and one SRAM. Depending on the capacitance on the system bus,
external buffers may be required. From a logic standpoint, however, a glueless system is
maintained.
8-BIT BOOT
EPROM/FLASH
ADDRESS
CS0
GPL1/OE
WE(0:3)
DATA
WE(0)
ADDRESS
CE
OE
WE
DATA
1-8
DRAM
CS1
RD/WR
PARITY(0:3)
CS2
MPC801
ADDRESS
RAS
CAS(0:3)
W
DATA
PARITY(0:3)
SRAM
ADDRESS
CE
OE
WE
DATA
Figure 1-2. MPC801 System Configuration
MPC801 USER’S MANUAL
MOTOROLA
2
SECTION 2
EXTERNAL SIGNALS
This section contains brief descriptions of the MPC801 input and output signals in their
functional groups as illustrated in Figure 2-1.
VDDSYN/VSSSYN/VSSSYN1/VDDH/VDDL/VSS/KAPWR
SPISEL/PB[31]
SPICLK/PB[30]
SPIMOSI/PB[29]
SPIMISO/PB[28]
I2CSDA/PB[27]
I2CSCL/PB[26]
UGPIO1/PB[25]
UGPIO2/PB[24]
UCTS1/PB[23]
UCTS2/PB[22]
URXD1/PB[21]
URXD2/PB[20]
URTS1/PB[19]
URTS2/PB[18]
UTXD1/PB[17]
UTXD2/PB[16]
TMS
DSDI/TDI
DSCK/TCK
TRST
DSDO/TDO
AS
BADDR[28:30]
MODCK2/DSDO
MODCK1/STS
PTR/AT3
DSDI/IRQ5
LWP1/VF1
LWP0/VF0
IWP2/VF2
IWP(0:1)/VFLS[0:1]
AT2
DSCK/AT1
TEXP
EXTCLK
CLKOUT
XFC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
1
2
1
1
1
1
1
MPC801
26
1
1
1
1
1
1
1
1
1
1
1
1
32
4
1
1
1
1
2
1
8
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
A[6:31]
TSIZ0
TSIZ1
RD/WR
BURST
BDIP/GPLB5
TS
TA
TEA
BI
RSV/IRQ2
KR/RETRY/IRQ4
CR/IRQ3
D[0:31]
DP[0:3]/IRQ[3:6]
BR
BG
BB
FRZ/IRQ6
IRQ[0:1]
IRQ[7]
CS[0:7]
WE0/BS_AB0
WE1/BS_AB1
WE2/BS_AB2
WE3/BS_AB3
GPLA0/GPLB0
OE/GPLA1/GPLB1
GPLA[2:3]/GPLB[2:3]/CS[2:3]
UPWAITA/GPLA4
UPWAITB/GPLB4
GPLA5
PORESET
RSTCONF
HRESET
SRESET
XTAL
EXTAL
MOTOROLA
Figure 2-1. MPC801 External Signals
MPC801 USER’S MANUAL
2-1
External Signals
2.1 THE SYSTEM BUS SIGNALS
The MPC801 system bus signals consist of all the lines that interface with the external bus.
2
Many of these lines perform different functions, depending on how you assign them. The
following input and output signals are identified by their mnemonic name and each signal’s
pin number can be found in Figure 2-1.
Table 2-1. Signal Descriptions
PIN NAME PIN NUMBER DESCRIPTION
A[6-31] See Table 2-2
TSIZ0 C10 Transfer Size 0 —When accessing a slave in the external bus, this three-state signal is used (together
TSIZ1 B10 Transfer Size 1— This three-state signal is used by the bus master to indicate the number of operand
RD/WR
C4
BURST
BDIP
GPLB5
TS
for pin
breakout.
C3
Address Bus— This bidirectional three-state bus provides the address for the current bus cycle. A0 is
the most-significant signal for this bus. The bus is output when an internal master on the MPC801
initiates a transaction on the external bus. The MPC801 is connected to the 26 least-significant bits on
the bus.
The bus is input when an external master initiates a transaction on the bus and it is sampled internally
so the memory controller can control the accessed slave device.
with TSIZ1) by the bus master to indicate the number of operand bytes waiting to be transferred in the
current bus cycle.
This signal is input when an external master initiates a transaction on the bus and it is sampled
internally so the memory controller can control the accessed slave device.
bytes waiting to be transferred in the current bus cycle.
This signal is driven by the MPC801 when it is the owner of the bus. It is input when an external master
initiates a transaction on the bus and it is sampled internally so the memory controller can control the
accessed slave device.
Read Write —This three-state signal is driven by the bus master to indicate the direction of the bus’
data transfer. A logic one indicates a read from a slave device and a logic zero indicates a write to a
slave device.
This signal is driven by the MPC801 when it is the owner of the bus. It is input when an external master
initiates a transaction on the bus and is sampled internally so the memory controller can control the
accessed slave device.
E1
Burst Transaction —This three-state signal is driven by the bus master to indicate that the current
initiated transfer is a burst one.
This signal is driven by the MPC801 when it is the owner of the bus. It is input when an external master
initiates a transaction on the bus; this signal and is sampled internally so the memory controller can
control the accessed slave device.
Burst Data in Progress —When accessing a slave device in the external bus, the master on the bus
asserts this signal to indicate that the data beat in front of the current one is the one requested by the
master. This signal is negated prior to the expected last data beat of the burst transfer.
General-Purpose Line B5 —This signal is used by the memory controller when the user
programmable machine B (UPMB) takes control of the slave access.
B1
Transfer Start— This three-state signal is asserted by the bus master to indicate the start of a bus cycle
that transfers data to or from a slave device.
This signal is driven by the master only when it has gained ownership of the bus. Every master should
negate this signal before the bus relinquishes. A pull-up resistor should be connected to this signal to
prevent a slave device from detecting a spurious bus accessing it when no master is taking ownership
of the bus.
This signal is sampled by the MPC801 when it is not the owner of the external bus so the memory
controller can control the accessed slave device. It indicates that an external synchronous master
initiated a transaction.
2-2
MPC801 USER’S MANUAL
MOTOROLA
External Signals
Table 2-1. Signal Descriptions (Continued)
PIN NAME PIN NUMBER DESCRIPTION
TA
TEA
BI D3 Burst Inhibit —This bidirectional three-state signal indicates that the slave device addressed in the
RSV
IRQ2
KR
/RETRY
IRQ4
CR
IRQ3
D[0:31] See Table 2-2
DP0
IRQ
3
B2 Transfer Acknowledge —This bidirectional three-state signal indicates that the slave device
addressed in the current transaction has accepted the data transferred by the master (write) or has
driven the data bus with valid data (read). The signal behaves as an output when the memory controller
takes control of the transaction. the only exception occurs when the memory controller is controlling the
slave access by means of the gpcm and the corresponding option register is instructed to wait for an
external assertion of the transfer acknowledge line. every slave device should negate the ta signal after
the end of the transaction and immediately three-state it to avoid contentions on the line if a new
transfer is initiated addressing other slave devices. A pull-up resistor should be connected to this signal
to keep a master device from detecting the assertion of this signal when no slave is addressed in a
transfer or when the address detection for the addressed slave is slow.
A1 Transfer Error Acknowledge —This open-drain signal indicates that a bus error occurred in the
current transaction. It is driven asserted by the MPC801 when the bus monitor does not detect a bus
cycle termination within a reasonable amount of time. The assertion of TEA
the current bus cycle, thus ignoring the state of TA
current burst transaction is unable to support burst transfers. The signal behaves as an output when
the memory controller takes control of the transaction. When the MPC801 drives out the signal for a
specific transaction, it asserts or negates BI
the user in the appropriate control registers. It negates the signal after the end of the transaction and
immediately three-states it to avoid contentions if a new transfer is initiated addressing other slave
devices.
G4 Reservation —This three-state signal is output by the MPC801 in conjunction with the address bus to
indicate that the internal core initiated a transfer as a result of a
Interrupt Request 2 —This input is one of the eight external signals that can request (by means of the
internal interrupt controller) a service routine from the core.
I2
Kill Reservation —This input is used as a part of the storage reservation protocol when the MPC801
initiated a transaction as the result of a
Retry —This input signal is used by the slave device to indicate that it is unable to accept the
transaction. The MPC801 must relinquish ownership of the bus and initiate the transaction again after
winning the bus arbitration.
Interrupt Request 4 —This input signal is one of the eight external signals that can request (by means
of the internal interrupt controller) a service routine from the core. It should be noted that the interrupt
request signal that is sent to the interrupt controller is the logical AND of this signal (if defined to function
as IRQ4
) and the DP1/IRQ4 (if defined to function as IRQ4).
D1
Cancel Reservation —This input signal is used as a part of the storage reservation protocol.
Interrupt Request 3 —This input signal is one of the eight external signals that can request (by means
of the internal interrupt controller) a service routine from the core. It should be noted that the interrupt
request signal that is sent to the interrupt controller is the logical AND of this signal (if defined to function
as IRQ3
) and the DP0/IRQ3 if defined to function as IRQ3.
for pin
breakout
Data Bus —This bidirectional three-state bus provides the general-purpose data path between the
MPC801 and all other devices. Although the data path is a maximum of 32 bits wide, it can be
dynamically sized to support 8-, 16-, or 32-bit transfers. D0 is the most-significant bit of the data bus.
M5 Data Parity 0 —This bidirectional three-state signal provides parity generation and checking for the
data bus lane D[0:7] by transferring to a slave device initiated by the MPC801. The parity function can
be defined independently for each one of the addressed memory banks (if controlled by the memory
controller) and for the rest of the slaves sitting on the external bus.
Interrupt Request 3 —This input signal is one of the eight external signals that can request (by means
of the internal interrupt controller) a service routine from the core. It should be noted that the interrupt
request signal that is sent to the interrupt controller is the logical AND of this signal (if defined to function
as IRQ3
) and the CR/IRQ3 if defined to function as IRQ3.
.
during the transaction according to the value specified by
stwcx instruction.
causes the termination of
stwcx or lwarx instruction.
2
MOTOROLA
MPC801 USER’S MANUAL
2-3
2
External Signals
Table 2-1. Signal Descriptions (Continued)
PIN NAME PIN NUMBER DESCRIPTION
DP1
IRQ4
DP2
IRQ5
DP3
IRQ6
BR E3
BG
BB
FRZ
IRQ6
IRQ0 N15 Interrupt Request 0 —This input signal is one of the eight external signals that can request (by means
IRQ1
IRQ7
O5
O4
N4
D2
C2
N16 Interrupt Request 1 —This input signal is one of the eight external signals that can request (by means
M17 Interrupt Request 7 —This input signal is one of the eight external signals that can request (by means
Data Parity 1 —This bidirectional three-state signal provides parity generation and checking for the
data bus lane D[8:15] by transferring to a slave device initiated by the MPC801. The parity function can
be defined independently for each one of the addressed memory banks (if controlled by the memory
controller) and for the rest of the slaves on the external bus.
Interrupt Request 4 —This input is one of the eight external lines that can request (by means of the
internal interrupt controller) a service routine from the core. It should be noted that the interrupt request
signal that is sent to the interrupt controller is the logical AND of this signal (if defined to function as
IRQ4
) and the KR/RETRY/IRQ4 if defined to function as IRQ4.
Data Parity 2 —This bidirectional three-state signal provides parity generation and checking for the
data bus lane D[16:23] by transferring to a slave device initiated by the MPC801. The parity function
can be defined independently for each one of the addressed memory banks (if controlled by the
memory controller) and for the rest of the slaves on the external bus.
Interrupt Request 5 —This input signal is one of the eight external signals that can request (by means
of the internal interrupt controller) a service routine from the core. It should be noted that the interrupt
request signal that is sent to the interrupt controller is the logical AND of this signal (if defined to function
as IRQ6
) and the DSDI/IRQ5 if defined to function as IRQ5.
Data Parity 3 —This bidirectional three-state signal provides parity generation and checking for the
data bus lane D[24:31] by transferring to a slave device initiated by the MPC801. The parity function
can be defined independently for each one of the addressed memory banks (if controlled by the
memory controller) and for the rest of the slaves on the external bus.
Interrupt Request 6 —This input signal is one of the eight external signals that can request (by means
of the internal interrupt controller) a service routine from the core. It should be noted that the interrupt
request signal that is sent to the interrupt controller is the logical AND of this signal (if defined to function
as IRQ6
) and the FRZ/IRQ6 if defined to function as IRQ6.
Bus Request —This bidirectional signal is asserted low when a possible master is requesting
ownership of the bus. When the MPC801 is configured to operate with the internal arbiter, this signal
is configured as an input. However, when the MPC801 is configured to operate with an external arbiter,
this signal is configured as an output and asserted every time a new transaction is intended to be
initiated and no parking on the bus is granted.
Bus Grant —This bidirectional signal is asserted low when the arbiter of the external bus grants the
specific master ownership of the bus. When the MPC801 is configured to operate with the internal
arbiter, this signal is configured as an output and asserted every time the external master asserts the
BR
signal and its priority request is higher than any of the internal sources requiring the initiation of a
bus transfer. However, when the MPC801 is configured to operate with an external arbiter, this signal
is configured as an input.
Bus Busy —This bidirectional signal is asserted low by a master to show that it owns the bus. The
MPC801 asserts this signal after the bus arbiter grants it bus ownership and the BB
E2
Freeze —This output signal is asserted to indicate that the internal core is in debug mode.
Interrupt Request 6 —This input signal is one of the eight external signals that can request (by means
of the internal interrupt controller) a service routine from the core. It should be noted that the interrupt
request signal that is sent to the interrupt controller is the logical AND of this signal (if defined to function
as IRQ6
) and the DP3/IRQ6 (if defined to function as IRQ6.)
of the internal interrupt controller) a service routine from the core.
of the internal interrupt controller) a service routine from the core.
of the internal interrupt controller) a service routine from the core.
signal is negated.
2-4
MPC801 USER’S MANUAL
MOTOROLA
Table 2-1. Signal Descriptions (Continued)
PIN NAME PIN NUMBER DESCRIPTION
[0:7] See Table 2-2
CS
WE0
BS_AB0
WE1
BS_AB1
WE2
BS_AB2
WE3
BS_B3
GPLA0
GPLB0
OE
GPLA1
GPLB1
GPLA
[2:3]
GPLB
[2:3]
CS
[2:3]
for pin
breakout
A10 Write Enable 1 —This output signal is asserted when the MPC801 initiates a write access to an
B7 and C7 General-Purpose Lines 2 and 3 on UPMA
Chip Select 0–7—These output signals enable peripheral or memory devices at programmed
addresses if they are appropriately defined in the memory controller. CS0
global chip-select for the boot device.
C9
Write Enable 0 —This output signal is asserted when a write access to an external slave controlled by
the GPCM in the memory controller is initiated by the MPC801. WE0
contains valid data to be stored by the slave device.
Byte Select 0 on UPMA or UPMB
in the memory controller whenever you program it. In a read or write transfer, the signal is only asserted
if the data lane D[0:7] contains valid data.
external slave controlled by the GPCM in the memory controller. WE1
D[8:15] contains valid data to be stored by the slave device.
Byte Select 1 on UPMA or UPMB
in the memory controller whenever you program it. In a read or write transfer, the signal is only asserted
if the data lane D[8:15] contains valid data.
A9 Write Enable 2 —This output signal is asserted when the MPC801 initiates a write access to an
external slave controlled by the GPCM in the memory controller. WE2
D[16:23] contains valid data to be stored by the slave device.
Byte Select 2 on UPMA or UPMB
in the memory controller whenever you program it. In a read or write transfer, the signal is only asserted
if the data lane D[16:23] contains valid data.
C8
Write Enable 3 —This output signal is asserted when the MPC801 initiates a write access to an
external slave controlled by the GPCM in the memory controller. WE3
D[24:31] contains valid data to be stored by the slave device.
Byte Select 3 on UPMA or UPMB
in the memory controller whenever you program it. In a read or write transfer, the signal is only asserted
if the data lane D[24:31] contains valid data.
B8 General-Purpose Line 0 on UPMA
memory controller when an external transfer to a slave is controlled by the user programmable machine
A (UPMA).
General-Purpose Line 0 on UPMB
memory controller when an external transfer to a slave is controlled by the user programmable machine
B (UPMB).
A7 Output Enable —This output signal is asserted when the MPC801 initiates a read access to an external
slave controlled by the GPCM in the memory controller.
General-Purpose Line 1on UPMA
memory controller when an external transfer to a slave is controlled by the user programmable machine
A (UPMA).
General-Purpose Line 1 on UPMB
memory controller when an external transfer to a slave is controlled by the user programmable machine
B (UPMB).
UPMA in the memory controller when an external transfer to a slave is controlled by the user
programmable machine A (UPMA).
General-Purpose Lines 2 and 3 on UPMB
UPMB in the memory controller when an external transfer to a slave is controlled by the user
programmable machine B (UPMB).
Chip Select 2 and 3 —These output signals enable peripheral or memory devices at programmed
addresses if they are appropriately defined in the memory controller. The double drive capability for
CS2
and CS3 is independently defined for each signal in the SIUMCR.
—This output signal is asserted as required by the UPMA or UPMB
—This output signal is asserted as required by the UPMA or UPMB
—This output signal is asserted as required by the UPMA or UPMB
—This output signal is asserted as required by the UPMA or UPMB
—This output signal reflects the value specified in the UPMA in the
—This output signal reflects the value specified in the UPMB in the
—This output signal reflects the value specified in the UPMA in the
—This output signal reflects the value specified in the UPMB in the
—These output signals reflect the value specified in the
—These output signals reflect the value specified in the
External Signals
can be configured to be the
is asserted if the data lane D[0:7]
is asserted if the data lane
is asserted if the data lane
is asserted if the data lane
2
MOTOROLA
MPC801 USER’S MANUAL
2-5
2
External Signals
Table 2-1. Signal Descriptions (Continued)
PIN NAME PIN NUMBER DESCRIPTION
A2
UPWAITA
GPLA4
UPWAITB
GPLB
4
GPLA5
PORESET
RSTCONF
HRESET
SRESET
XTAL N1 This output signal is one of the connections to an external crystal for the internal oscillator circuitry.
EXTAL M1 This signal is one of the connections to an external crystal for the internal oscillator circuitry.
XFC O3
CLKOUT P5
EXTCLK L1
TEXP L2
DSCK/AT1 H4
IWP[0:1]
VFLS[0:1]
AT2 H2
M3
N2
M2
G1 and G2 Instruction Watchpoint 0-1 —These output signals report the detection of an instruction watchpoint in
User Programmable Machine Wait A
to an external slave is controlled by the UPMA in the memory controller.
General-Purpose Line 4 on UPMA
memory controller when an external transfer to a slave is controlled by the user programmable machine
A (UPMA).
A3
User Programmable Machine Wait B
to an external slave is controlled by the UPMB in the memory controller.
General-Purpose Line 4 on UPMB
memory controller when an external transfer to a slave is controlled by the
machine B (UPMB).
B3
General-Purpose Line 5 on UPMA
memory controller when an external transfer to a slave is controlled by the user programmable machine
A (UPMA). This signal can also be controlled by the UPMB.
Power -On Reset —When asserted, this input signal causes the MPC801 to enter the power-on reset
state.
Reset Configuration —This input signal is sampled by the MPC801 during the assertion of the
HRESET
signal. If it is asserted, the configuration mode is sampled in the form of the hard reset
configuration word driven on the data bus. When this signal is negated, the default configuration mode
is adopted by the MPC801. Notice that the initial base address of internal registers is determined in this
sequence.
Hard Reset —This open drain line, when asserted, causes the MPC801 external crystal to enter the
hard reset state.
L3
Soft Reset —This open drain line, when asserted, causes the MPC801 external crystal to enter the soft
reset state.
External Filter Capacitance —This input signal is the connection pin to an external capacitor filter for
the PLL circuitry.
Clock Out —This output signal is the clock system frequency.
External Clock —This input signal is the external input clock from an external source.
Timer Expired —This output signal reflects the status of the TEXPS bit in the PLPRCR in the CLOCK
interface.
Development Serial Clock —This input signal is the clock for the debug port interface.
Address Type 1 —This bidirectional three-state signal is driven by the MPC801 when it initiates a
transaction on the external bus. When the transaction is initiated by the internal core, it indicates if the
transfer is for problem or privilege state.
the program flow executed by the internal core.
Visible History Buffer Flushes Status
need program instructions flow tracking. They report the number of instructions flushed from the history
buffer in the internal core.
Address Type 2 —This bidirectional three-state signal is driven by the MPC801 when it initiates a
transaction on the external bus. When the transaction is initiated by the internal core, it indicates if the
transfer is instruction or data.
—This input signal is sampled as you need it when an access
—This output signal reflects the value specified in the UPMA in the
—This input signal is sampled as you need it when an access
—This output signal reflects the value specified in the UPMB in the
user programmable
—This output signal reflects the value specified in the UPMA in the
—These output signals are output by the MPC801 when you
2-6
MPC801 USER’S MANUAL
MOTOROLA
External Signals
Table 2-1. Signal Descriptions (Continued)
PIN NAME PIN NUMBER DESCRIPTION
IWP2
VF2
LWP0
VF0
LWP1
VF1
DSDI
IRQ5
PTR
AT3
MODCK1
STS
MODCK2
DSDO
BADDR[28:30] J1, I1, and H1 Burst Address —These output signals duplicate the value of A[28:29] when:
AS
PB[31]
SPISEL
PB[30]
SPICLK
F1
Instruction Watchpoint 2 —This output signal reports the detection of an instruction watchpoint in the
program flow executed by the internal core.
Visible Instruction Queue Flush Status
the MPC801 when you need program instructions flow tracking. VF
flushed from the instruction queue in the internal core.
F2
Load/Store Watchpoint 0 —This output signal reports the detection of a data watchpoint in the
program flow executed by the internal core.
Visible Instruction Queue Flushes Status
output by the MPC801 when you need program instructions flow tracking. VF reports the number of
instructions flushed from the instruction queue in the internal core.
G3 Load/Store Watchpoint 1 —This output signal reports the detection of a data watchpoint in the
program flow executed by the internal core.
Visible Instruction Queue Flushes Status
output by the MPC801 when you need program instructions flow tracking. VF reports the number of
instructions flushed from the instruction queue in the internal core.
I3
Development Serial Data Input —This input signal is the data in for the debug port interface.
Interrupt Request 5 —This input signal is one of the eight external signals that can request through the
internal interrupt controller, a service routine from the core. It should be noted that the interrupt request
signal that is sent to the interrupt controller is the logical AND of this signal (if defined to function as
IRQ5
) and the DP2/IRQ5 (if defined to function as IRQ5).
H3
Program Trace —This output signal is asserted by the MPC801 to indicate an instruction fetch is taking
place to allow program flow tracking.
Address Type 3 —This bidirectional three-state signal is driven by the MPC801 when it initiates a
transaction on the external bus. When the transaction is initiated by the internal core, it indicates if the
transfer is reserved for data transfers or a program trace indication for instructions fetch.
J3
Mode Clock 1 —This input signal is sampled at PORESET negation to configure the PLL/clock mode
of operation.
Special Transfer Start —This output signal is driven by the MPC801 to indicate the start of a
transaction on the external bus or to signal the beginning of an internal transaction in show cycle mode.
J2
Mode Clock 2 —This input signal is sampled at PORESET
of operation.
Development Serial Data Output
• An internal master in the MPC801 initiates a transaction on the external bus.
• An asynchronous external master initiates a transaction.
• A synchronous external master initiates a single beat transaction.
These signals are used by the memory controller to allow increments in the address lines that connect
to memory devices when a synchronous external or internal master initiates a burst transfer.
I4
Address Strobe —This input signal is driven by an external asynchronous master to indicate a valid
address on the A[6:31] signals. The memory controller in the MPC801 synchronizes this signal and
controls the memory device addressed under its control.
F16 General-Purpose I/O Port B Bit 31
—This is the serial peripheral interface slave select input pin.
SPISEL
G13 General-Purpose I/O Port B Bit 30
SPICLK —This is the serial peripheral interface output clock when it is configured as a master or serial
peripheral interface input clock when it is configured as a slave.
—This output signal, together with VF0 and VF1, is output by
—This output signal, combined with VF1 and VF2, is
—This output signal, combined with VF0 and VF2, is
—This output signal is the data out of the debug port interface.
—This is Bit 31 of the general-purpose I/O port B.
—This is Bit 30 of the general-purpose I/O port B.
x
reports the number of instructions
negation to configure the PLL/clock mode
2
MOTOROLA
MPC801 USER’S MANUAL
2-7
2
External Signals
Table 2-1. Signal Descriptions (Continued)
PIN NAME PIN NUMBER DESCRIPTION
PB[29]
SPIMOSI
PB[28]
SPIMISO
PB[27]
I2CSDA
PB[26]
I2CSCL
PB[25]
UGPIO1
PB[24]
UGPIO2
PB[23]
UCTS1
PB[22]
UCTS2
PB[21]
URXD1
PB[20]
URXD2
PB[19]
URTS1
PB[18]
URTS2
PB[17]
UTXD1
PB[16]
UTXD2
G15 General-Purpose I/O Port B Bit 29
SPIMOSI —This is the serial peripheral interface output data when it is configured as a master or serial
peripheral interface input data when it is configured as a slave.
G16 General-Purpose I/O Port B Bit 28
SPIMISO —This is the serial peripheral interface input data when it is configured as a master or serial
peripheral interface output data when it is configured as a slave.
H14 General-Purpose I/O Port B Bit 27
I2CSDA —This is the I
output.
H15 General-Purpose I/O Port B Bit 26
I2CSCL —This is the I
output.
J13 General-Purpose I/O Port B Bit 25
UGPIO1 —This is the general-purpose input/output pin of UART1. It can be configured as a general
input or output or it can serve as the source of the clock to the baud rate generator. It can also output
the bit clock at the selected baud rate.
J15 General-Purpose I/O Port B Bit 24
UGPIO2 —This is the general-purpose input/output pin of UART2. It can be configured as a general
input or output or it can serve as the source of the clock to the baud rate generator. It can also output
the bit clock at the selected baud rate.
K16 General-Purpose I/O Port B Bit 23
UCTS1
—This is an active low clear-to-send input of UART1 that is used to control the transmitter.
K15 General-Purpose I/O Port B Bit 22—
—This is an active low clear-to-send input of UART2 that is used to control the transmitter.
UCTS2
K14 General-Purpose I/O Port B Bit 21
URXD1 —This signal is the receive data serial input of UART1.
L16 General-Purpose I/O Port B Bit 20
URXD2 —This signal is the receive data serial input of UART2.
L15 General-Purpose I/O Port B Bit 19
URTS1
—This is an active low ready-to-send output from UART1 used to indicate that the receiver is
ready.
L14 General-Purpose I/O Port B Bit 18—This is Bit 18 of the general-purpose I/O port B.
URTS2
—This is an active low ready-to-send output from UART2 used to indicate that the receiver is
ready.
M16 General-Purpose I/O Port B Bit 17—This is Bit 17 of the general-purpose I/O port B.
UTXD1—This signal is the transmit data serial output from UART1.
M15 General-Purpose I/O Port B Bit 16—This is Bit 16 of the general-purpose I/O port B.
UTXD2—This signal is the transmit data serial output from UART1.
2
C serial data pin. It is bidirectional and should be configured as an open-drain
2
C serial clock pin. It is bidirectional and should be configured as an open-drain
—This is Bit 29 of the general-purpose I/O port B.
—This is Bit 28 of the general-purpose I/O port B.
—This is Bit 27 of the general-purpose I/O port B.
—This is Bit 26 of the general-purpose I/O port B.
—This is Bit 25 of the general-purpose I/O port B.
—This is Bit 24 of the general-purpose I/O port B.
—This is Bit 23 of the general-purpose I/O port B.
This is Bit 22 of the general-purpose I/O port B.
—This is Bit 21 of the general-purpose I/O port B.
—This is Bit 20 of the general-purpose I/O port B.
—This is Bit 19 of the general-purpose I/O port B.
2-8
MPC801 USER’S MANUAL
MOTOROLA
External Signals
Table 2-1. Signal Descriptions (Continued)
PIN NAME PIN NUMBER DESCRIPTION
Power Supply A8, J16, K1,
TCK
DSCK
TMS H13 Test Mode Select—This input signal controls the scan chain test mode operations. It should be
TDI
DSDI
TDO
DSDO
TRST
and P9
H16 Test Data Output—This three-state output signal is the data out of the JTAG interface.
VDDH—This signal is the power supply of the I/O buffers and certain parts of the clock control.
VDDSYN—This signal is the power supply of the PLL circuitry.
P3
VSSSYN—This signal is the power supply for the clock synthesizer.
P2
VSSSYN1—This signal is the power supply for the clock synthesizer.
P1
KAPWR—This signal is the power supply of the internal oscillator, real-time clock, periodic interrupt
O1
timer, decrementer, and timebase.
I15 Test Clock—This input signal is the clock of the JTAG interface.
Development Serial Clock—This input signal is the clock for the debug port interface.
powered through a pull-up resistor if unused.
I16 Test Data Input—This input signal is the data in for the JTAG interface.
Development Serial Data Input—This input signal is the data for the debug port interface.
Development Serial Data Output—This output signal is the data out of the debug port interface.
I17 Test Reset—This input signal is the asynchronous reset of the TAP machine on the JTAG interface.
2
MOTOROLA MPC801 USER’S MANUAL 2-9
2
External Signals
Table 2-2. Pin Breakout
PIN NAME PIN NUMBER
ADDRESS BUS PINS 6–31 A6 G17
A7 E16
A8 F15
A9 D16
A10 G15
A11 F17
A12 C16
A13 D15
A14 E17
A15 B15
A16 C15
A17 C14
A18 B12
A19 A15
A20 B17
A21 C13
A22 C11
A23 B13
A24 A14
A25 C12
A26 B11
A27 A16
A28 A12
A29 B16
A30 A13
A31 A11
2-10 MPC801 USER’S MANUAL MOTOROLA
Table 2-2. Pin Breakout (Continued)
PIN NAME PIN NUMBER
DATA BUS PINS 0–31 D0 O16
D1 P17
D2 P12
D3 P11
D4 P16
D5 P10
D6 P8
D7 P6
D8 N14
D9 O13
D10 N11
D11 P13
D12 P12
D13 O15
D14 M10
D15 N10
D16 M9
D17 O14
D18 O10
D19 N9
D20 O9
D21 N8
D22 O8
D23 N12
D24 O7
D25 N7
D26 M7
D27 P15
D28 N6
D29 O6
D30 N5
D31 M6
External Signals
2
MOTOROLA MPC801 USER’S MANUAL 2-11
2
External Signals
Table 2-2. Pin Breakout (Continued)
PIN NAME PIN NUMBER
CHIP SELECT PINS 0–7 CS0 B4
CS1 A4
CS2 C5
CS3 B5
CS4 A6
CS5 B6
CS6 C6
CS7 A5
2-12 MPC801 USER’S MANUAL MOTOROLA
SECTION 3
MEMORY MAP
The MPC801 internal memory resources are mapped within a contiguous block of 16K
storage. The location of this block within the global 4G real storage space can be mapped
on 64K resolution through an implementation specific special register called the internal
memory map register. Refer to Section 12 System Interface Unit and Appendix A Quick
Reference Guide to MPC801 Registers for more information. The following table defines
the internal memory map of the MPC801.
Table 3-1. MPC801 Internal Memory Map
INTERNAL
ADDRESS
GENERAL SYSTEM INTERFACE UNIT
000 SIUMCR SIU Module Configuration Register 32
004 SYPCR System Protection Control Register 32
008 RES Reserved —
00E SWSR Software Service Register 16
010 SIPEND SIU Interrupt Pending Register 32
014 SIMASK SIU Interrupt Mask Register 32
018 SIEL SIU Interrupt Edge Level Mask Register 32
01C SIVEC SIU Interrupt Vector Register 32
020 TESR Transfer Error Status Register 32
024 to 02F RES Reserved —
MNEMONIC NAME SIZE
3
UART1 CONTROLLER
040 CNTREG1 Control Register 16
044 BAUDREG1 Baud Control Register 16
048 GLOBREG1 Global Register 16
04C RXREG1 Receiver Register 16
050 TXREG1 Transmitter Register 16
054 RXREG1 Receiver Register (Special Read Mode) 16
058 to 05F RES Reserved —
MOTOROLA
MPC801 USER’S MANUAL
3-1
Memory Map
Table 3-1. MPC801 Internal Memory Map (Continued)
3
INTERNAL
ADDRESS
UART2 CONTROLLER
060 CNTREG2 Control Register 16
064 BAUDREG2 Baud Control Register 16
068 GLOBREG2 Global Register 16
06C RXREG2 Receiver Register 16
070 TXREG2 Transmitter Register 16
074 RXREG2 Receiver Register (Special Read Mode) 16
078 to 0FF RES Reserved —
MEMORY CONTROLLER
100 BR0 Base Register Bank 0 32
104 OR0 Option Register Bank 0 32
108 BR1 Base Register Bank 1 32
10C OR1 Option Register Bank 1 32
110 BR2 Base Register Bank 2 32
114 OR2 Option Register Bank 2 32
118 BR3 Base Register Bank 3 32
11C OR3 Option Register Bank 3 32
120 BR4 Base Register Bank 4 32
124 OR4 Option Register Bank 4 32
128 BR5 Base Register Bank 5 32
12C OR5 Option Register Bank 5 32
130 BR6 Base Register Bank 6 32
134 OR6 Option Register Bank 6 32
138 BR7 Base Register Bank 7 32
13C OR7 Option Register Bank 7 32
140 to 163 RES Reserved —
164 MAR Memory Address Register 32
168 MCR Memory Command Register 32
16C to 16F RES Reserved —
170 MAMR Machine A Mode Register 32
174 MBMR Machine B Mode Register 32
178 MSTAT Memory Status Register 16
MNEMONIC NAME SIZE
3-2
MPC801 USER’S MANUAL
MOTOROLA
Memory Map
Table 3-1. MPC801 Internal Memory Map (Continued)
INTERNAL
ADDRESS
17A MPTPR Memory Periodic Timer Prescaler 16
17C MDR Memory Data Register 32
2
I
C CONTROLLER
180 I2CER
184 I2CMR
188 I2CRD
18C I2CTD
190 I2MOD
194 I2ADD
198 I2BRG
19C I2COM
1A0 to 1AF RES Reserved —
SERIAL CONTROLLER
1B0 SECCOM Serial Controller Command Register 8
1B4 to 1BF RES Reserved —
MNEMONIC NAME SIZE
2
I
C Event Register
2
I
C Mask Register
2
I
C Receive Data Register
2
C Register
I
2
I
C Mode Register
2
I
C Address Register
2
I
C BRG Register
2
I
C Command Register
3
8
8
16
16
8
8
8
8
SERIAL PERIPHERAL INTERFACE
1C0 SPIER SPI Event Register 8
1C4 SPIMR SPI Mask Register 16
1C8 SPIRD SPI Receive Data Register 32
1CC SPITD SPI Transmit Data Register 32
1D0 SPMODE SPI Mode Register 16
1D4 SPCOM SPI Command Register 8
1D8 to 1DF RES Reserved —
PORT B
1E0 PBODR Port B Open-Drain Register 16
1E4 PBDAT Port B Data Register 16
1E8 PBDIR Port B Data Direction Register 16
1EC PBPAR Port B Pin Assignment Register 16
AF0 to 1FF RES Reserved —
MOTOROLA
MPC801 USER’S MANUAL
3-3
Memory Map
Table 3-1. MPC801 Internal Memory Map (Continued)
3
INTERNAL
ADDRESS
SYSTEM INTEGRATION TIMERS
200 TBSCR Timebase Status and Control Register 16
204 TBREFF0 Timebase Reference Register 0 32
208 TBREFF1 Timebase Reference Register 1 32
20C to 21F RES Reserved —
220 RTCSC Real-Time Clock Status and Control Register 16
224 RTC Real-Time Clock Register 32
228 RTSEC Real-Time Alarm Seconds 32
22C RTCAL Real-Time Alarm Register 32
230 to 23F RES Reserved —
240 PISCR Periodic Interrupt Status and Control Register 16
244 PITC Periodic Interrupt Count Register 32
248 PITR Periodic Interrupt Timer Register 32
24C to 27F RES Reserved —
CLOCKS AND RESET
280 SCCR System Clock Control Register 32
284 PLPRCR PLL, Low-Power and Reset Control Register 32
288 RSR Reset Status Register 32
28C to 2FF RES Reserved —
MNEMONIC NAME SIZE
SYSTEM INTEGRATION TIMERS KEYS
300 TBSCRK Timebase Status and Control Register Key 32
304 TBREFF0K Timebase Reference Register 0 Key 32
308 TBREFF1K Timebase Reference Register 1 Key 32
30C TBK Timebase and Decrementer Register Key 32
310 to 31F RES Reserved —
320 RTCSCK Real-Time Clock Status and Control Register Key 32
324 RTCK Real-Time Clock Register Key 32
328 RTSECK Real-Time Alarm Seconds Key 32
32C RTCALK Real-Time Alarm Register Key 32
3-4
MPC801 USER’S MANUAL
MOTOROLA
Table 3-1. MPC801 Internal Memory Map (Continued)
Memory Map
INTERNAL
ADDRESS
330 to 33F RES Reserved —
340 PISCRK Periodic Interrupt Status and Control Register Key 32
344 PITCK Periodic Interrupt Count Register Key 32
348 to 37F RES Reserved —
CLOCKS AND RESET KEYS
380 SCCRK System Clock Control Key 32
384 PLPRCRK PLL, Low-Power and Reset Control Register Key 32
388 RSRK Reset Status Register Key 32
38C to 3FF RES Reserved —
MNEMONIC NAME SIZE
3
MOTOROLA
MPC801 USER’S MANUAL
3-5
3
Memory Map
3-6
MPC801 USER’S MANUAL
MOTOROLA
SECTION 4
RESET
The reset block has a reset control logic that determines the cause of reset, synchronizes it
if necessary, and resets the appropriate logic modules. The memory controller, system
protection logic, interrupt controller, and parallel I/O pins are initialized only on hard reset.
Soft reset initializes the internal logic while maintaining the system configuration.
Table 4-1. Possible Reset Results
RESET EFFECT
RESET
SOURCE
Power-On Reset Yes Yes Yes Yes Yes Yes Yes
External Hard Reset
Loss-of-Lock
Software Watchdog
Check Stop
Debug Port Hard Reset
JTAG Reset
External Soft Reset
Debug Port Soft Reset
RESET
LOGIC AND
PLL
STATES
RESET
No Yes Yes Yes Yes Yes Yes
No No No No Yes Yes Yes
SYSTEM
CONFIG
RESET
CLOCK
MODULE
RESET
HRESET
PIN
DRIVEN
DEBUG
PORT
CONFIG
OTHER
INTERNAL
LOGIC
RESET
SRESET
PIN
DRIVEN
4.1 TYPES OF RESET
The MPC801 has several types of inputs to the reset logic:
4
• Power-on reset
• External hard reset
• Internal hard reset
— Loss of lock
— Software watchdog reset
— Checkstop reset
— Debug port hard reset
— JTAG reset
MOTOROLA
MPC801 USER’S MANUAL
4-1
Reset
• External soft reset
• Internal soft reset
— Debug port soft reset
All of these reset sources are fed into the reset controller and, depending on the source of
the reset, different actions are taken. The reset status register reflects the last source to
cause a reset.
4.1.1 Power-On Reset
4
Power-on reset is an active low input pin called PORESET
low-power mode, this pin should only be activated when a voltage in the keep alive power
(KAPWR) rail fails. When this pin is asserted, the MODCK bits are sampled and the
phase-locked loop multiplication factor and pitrtclk and tmbclk sources are changed to their
default values. When this pin is negated, internal MODCK values are unchanged. The
PORESET
assertion, the MPC801 enters the power-on reset state and stays there until the following
events occur:
pin should be asserted for a minimum of 3 microseconds. After detecting this
. In a system with power-down
• The internal PLL enters the lock state and the system clock is active
• The PORESET
When PORESET
SRESET
extension counter of 512 is reset,and the MODCK pins are sampled when POR pin is
negated. After the negation of PORESET
initiated HRESET
When the timer expires, which is usually after the 512 cycles, the configuration is sampled
from the data pins and the core stops driving the pins. An external pull-up resistor should
drive the HRESET
passes before the presence of an external (hard/soft) reset is tested. Refer to Section 4.3.1
Hard Reset for more information.
and HRESET are asserted by the core. When the MPC801 remains in POR, the
pin is negated
is asserted, the MPC801 enters the power-on reset (POR) state in which
or PLL lock, the core enters the state of internal
and continues driving the HRESET and SRESET pins for 512 cycles.
and SRESET pins high. After the pins are negated, a 16-cycle period
4.1.2 External Hard Reset
HRESET
external assertion of HRESET
HRESET
reset) is a bidirectional, active low I/O pin. The MPC801 can only detect an external
assertion of SRESET
also an open-collector type of pin.
When an external HRESET
for 512 cycles. When the timer expires, after 512 cycles, the configuration is sampled from
the data pins and the core stops driving the HRESET
resistor should drive the pins high and once they are negated, a 16-cycle period passes
before the presence of an external (hard/soft) reset is tested. Refer to Section 4.3.1 Hard
Reset for more information.
(hard reset) is a bidirectional, active low I/O pin. The MPC801 can only detect an
if it occurs while the MPC801 is not asserting reset. During
, SRESET is asserted. HRESET is an open-collector type of pin. SRESET (soft
if it occurs while the MPC801 is not asserting reset. The SRESET is
is asserted, the core starts driving the HRESET and SRESET
and SRESET pins. An external pull-up
4-2
MPC801 USER’S MANUAL
MOTOROLA
Reset
4.1.3 Internal Hard Reset
When the core finds a reason to assert HRESET,
pins for 512 cycles. When the timer expires, after the 512 cycles, the configuration is
sampled from data pins and the core stops driving the pins. An external pull-up resistor
should drive the HRESET
period passes before the presence of an external (hard/soft) reset is tested. Refer to
Section 4.3.1 Hard Reset for more information. The causes of internal hard reset are as
follows:
and SRESET pins high and once they are negated a 16-cycle
it starts driving the HRESET and SRESET
• Loss of lock
• Software watchdog reset
• Checkstop reset
• Debug port hard reset
• JTAG reset
4.1.3.1 LOSS OF LOCK. If the PLL detects a loss of lock, erroneous external bus operation
occurs if synchronous external devices use the core input clock. Erroneous operation could
also occur if devices with a PLL use the core clockout. This source of reset can be asserted
if the LOLRE bit in the PLL low-power and reset control register is set. The enabled PLL
loss-of-lock event generates an internal hard reset sequence.
4.1.3.2 SOFTWARE WATCHDOG RESET. After the core watchdog counts to zero, a
software watchdog reset is asserted. The enabled software watchdog event then generates
an internal hard reset sequence.
4.1.3.3 CHECKSTOP RESET. If the core enters a checkstop state and the checkstop reset
is enabled, the checkstop reset is asserted. The enabled checkstop event then generates
an internal hard reset sequence.
4.1.3.4 DEBUG PORT HARD RESET. When the development port receives a hard reset
request from the development tool, an internal hard reset sequence is generated. In this
case, the development tool must reconfigure the debug port. Refer to Section 18.3.3.1.2
Development Serial Data In for more information.
4
4.1.3.5 JTAG RESET. When the JTAG logic asserts the JTAG soft reset signal, an internal
soft reset sequence will be generated.
4.1.4 External Soft Reset
When an external SRESET
timer expires, after 512 cycles, the debug port configuration is sampled from the DSDI and
DSCK pins and the core stops driving the pin. An external pull-up resistor should drive it high
and once it is negated a 16-cycle period passes before the presence of an external soft reset
is tested.
MOTOROLA
is asserted, the core starts driving the SRESET pin. When the
MPC801 USER’S MANUAL
4-3
4
Reset
4.1.5 Internal Soft Reset
When the core finds a reason to assert SRESET,
the timer expires, after 512 cycles, the debug port configuration is sampled from the DSDI
and DSCK pins and the core stops driving the SRESET
should drive the pin high and once it is negated a 16-cycle period passes before the
presence of an external soft reset is tested. JTAG and the debug port cause an internal soft
reset.
4.1.5.1 DEBUG PORT SOFT RESET. When the development port receives a soft reset
request from the development tool, an internal soft reset sequence is generated. In this case
the development tool must reconfigure the debug port. Refer to Section 18.3.3.1.2
Development Serial Data In for more information.
it starts driving the SRESET pin. When
pin. An external pull-up resistor
4.2 RESET STATUS REGISTER
The 32-bit reset status register (RSR) is powered by the keep alive power supply. It is
memory-mapped into the MPC801 system interface unit register map and receives its
default reset values at power-on reset.
RSR
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD
RESET
R/W
BIT
FIELD
RESET
R/W
EHRS ESRS LLRS SWRS CSRS DBHRS DBSRS JTRS
00000000 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RESERVED
0
R/W
RESERVED
EHRS—External Hard Reset Status
This bit is cleared by a power-on reset. When an external hard reset event is detected, this
bit is set and remains that way until the software clears it. The EHRS bit can be negated by
writing a 1, but a write of zero has no effect on it.
0 = No external hard reset event occurred.
1 = An external hard reset event occurred.
ESRS—External Soft Reset Status
This bit is cleared by a power-on reset. When an external soft reset event is detected, this
bit is set and remains that way until the software clears it. The ESRS bit can be negated by
writing a 1, but a write of zero has no effect on it.
0 = No external soft reset event occurred.
1 = An external soft reset event occurred.
4-4
MPC801 USER’S MANUAL
MOTOROLA
Reset
LLRS—Loss-of-Lock Reset Status
This bit is cleared by a power-on reset. When a loss-of-lock event is enabled by the LOLRE
bit in the PLPRCR is detected, this bit is set and remains that way until the software clears
it. The LLRS bit can be negated by writing a 1, but a write of zero has no effect on it.
0 = No enabled loss-of-lock reset event occurred.
1 = An enabled loss-of-lock reset event occurred.
SWRS—Software Watchdog Reset Status
This bit is cleared by a power-on reset. When a software watchdog expire event occurs, this
bit is set and remains that way until the software clears it. The SWRS bit can be negated by
writing a 1, but a write of zero has no effect on it.
0 = No software watchdog reset event occurred.
1 = A software watchdog reset event occurred.
4
CSRS—Check Stop Reset Status
This bit is cleared by a power-on reset. When the core enters the checkstop state and the
checkstop reset is enabled by the CSR bit in the PLPRCR, this bit is set and remains that
way until the software clears it. The CSRS bit can be negated by writing a 1, but a write of
zero has no effect on it.
0 = No enabled checkstop reset event occurred.
1 = An enabled checkstop reset event occurred.
DBHRS—Debug Port Hard Reset Status
This bit is cleared by a power-on reset. When the debug port hard reset request is set, this
bit is set and remains that way until the software clears it. The DBHRS bit can be negated
by writing a 1, but a write of zero has no effect on it.
0 = No debug port hard reset request occurred.
1 = A debug port hard reset request occurred.
DBSRS—Debug Port Soft Reset Status
This bit is cleared by a power-on reset. When the debug port soft reset request is set, this
bit is set and remains that way until the software clears it. The DBSRS bit can be negated
by writing a 1, but a write of zero has no effect on it.
0 = No debug port soft reset request occurred.
1 = A debug port soft reset request occurred.
JTRS—JTAG Reset Status
This bit is cleared by a power-on reset. When the JTAG reset request is set, this bit is set
and remains that way until the software clears it. The JTRS bit can be negated by writing a
1, but a write of zero has no effect on it.
0 = No JTAG reset event occurred.
1 = A JTAG reset event occurred.
MOTOROLA
MPC801 USER’S MANUAL
4-5
4
Reset
Bits 8–31—Reserved
These bits are reserved and should be set to 0.
4.3 HOW TO CONFIGURE RESET
In normal operation, you can configure reset with a hard reset. However, to configure the
development port you should use a soft reset.
4.3.1 Hard Reset
When a hard reset event occurs, the MPC801 reconfigures its hardware system as well as
the development port configuration. The logical value of the bits that determine its initial
mode of operation are sampled either from the data bus or from an internal default constant
(D[0:31]=x’00000000). If, at sampling time, RSTCONF
sampled from the data bus. Otherwise, it is sampled from the internal default. While
HRESET
and RSTCONF are asserted, the MPC801 pulls the data bus low through a weak
resistor. You can overwrite this default by driving high to the appropriate bit (see Figure 4-1).
The hardware reset configuration scheme for PORESET
through 4-4. While the PORESET
input signal is being asserted, the core assumes the
default reset configuration that changes when PORESET
starts oscillating. In this last case, the hardware configuration is sampled every nine clock
cycles on the rising edge of the CLKOUT. The setup time required for the data bus is 15
cycles and the maximum rise time of HRESET
should be less than six clock cycles. Refer
to Section 4.3.2 Soft Reset for more information.
is asserted, the configuration is
assertion is shown in Figures 4-2
is negated or the CLKOUT signal
CONFIGURATION
WORD
4-6
MUX
DX (DATA LINE)
MPC801
Figure 4-1. Reset Configuration Basic Scheme
MPC801 USER’S MANUAL
HRESET
RSTCONF
MOTOROLA
CLKOUT
PORESET
INTPORESET
Reset
HRESET
RSTCONF
D[0:31]
CLKOUT
PORESET
INTPORESET
HRESET
RSTCONF
TSUP
DEFAULT
RSTCONF
CONTROLLED
Figure 4-2. Reset Configuration Sampling Scheme
For Short PORESET
Assertion
TSUP
4
D[0:31]
MOTOROLA
DEFAULT RSTCONF CONTROLLED
Figure 4-3. Reset Configuration Sampling Scheme
For Long PORESET
MPC801 USER’S MANUAL
Assertion
4-7
Reset
4
17
MAXIMUM TIME OF RESET RECOGNITION
DATA
SAMPLE
CONFIGURATION
DATA
SAMPLE
CONFIGURATION
4-8
12345678910111213141516
CLKOUT
HRESET
RSTCONF
MAXIMUM SETUP TIME OF RESET RECOGNITION
RESET CONFIGURATION WORD
DATA
MPC801 USER’S MANUAL
DATA
SAMPLE
CONFIGURATION
Figure 4-4. Reset Configuration Sampling Timing Requirements
MOTOROLA
Reset
4.3.1.1 HARD RESET CONFIGURATION WORD
The hard reset configuration word register is sampled from the data bus and default
of the bits.
HARD RESET CONFIGURATION WORD
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD EARB IP RES BDIS BPS RES ISB DBGC DBPC EBDF RES
RESET 00000000000
BIT
FIELD
RESET
EARB—External Arbitration
If this bit is set (1), external arbitration is assumed. If it is cleared (0), then internal arbitration
is performed. See Section 12.12.1.1 SIU Module Configuration Register for more
information.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RESERVED
0
4
—Initial Interrupt Prefix
IP
This bit defines the initial value of the MSR
the interrupt table location. If IP
sampled one, the MSR
IP
is zero (default), the MSR
initial value is zero. See Section 6.3.1.2.1 Machine State
immediately after reset. The MSR
IP
initial value is one, but if it is
IP
bit defines
IP
Register .
Bits 2, 6, and 15—Reserved
These bits are reserved and should be set to 0.
BPS—Boot Port Size
This field defines the port size of the boot device as shown in the following chart.
00 = 32-bit port size.
01 = 8-bit port size.
10 = 16-bit port size.
11 = Reserved.
ISB—Initial Internal Space Base Select
This field defines the initial value of the IMMR bits 0-15 and determines the base address of
the internal memory space.
00 = $00000000.
01 = $00F00000.
10 = $FF000000.
11 = $FFF00000.
MOTOROLA
MPC801 USER’S MANUAL
4-9
4
Reset
DBGC—Debug Pins Configuration
This field configures the functionality of the following pins.
0x = IWP[0:1]/VFLS[0:1] functions as IWP[0:1].
IWP2/VF2 functions as IWP2.
LWP0/VF0 functions as LWP0.
LWP1/VF1 functions as LWP1.
MODCK1/STS
functions as STS.
DSCK/AT1 functions as AT1.
DSDI/IRQ5
PTR
functions as IRQ5.
/AT3 functions as AT3.
MODCK2/DSDO functions as DSDO.
10 = Reserved.
11 = IWP[0:1]/VFLS[0:1] functions as VFLS[0:1].
IWP2/VF2 functions as VF2.
LWP0/VF0 functions as VF0.
LWP1/VF1 functions as VF1.
MODCK1/STS
functions as STS.
DSCK/AT1 functions as AT1.
DSDI/IRQ5
PTR
functions as IRQ5.
/AT3 functions as AT3.
MODCK2/DSDO functions as DSDO.
DBPC—Debug Port Pins Configuration
This field configures the following pins on which the development port is active.
00 = DSCK/AT1 functions as defined by DBGC
DSDI/IRQ5
PTR
functions as defined by DBGC
/AT3 functions as defined by DBGC
TCK/DSCK functions as DSCK
TDI/DSDI functions as DSDI
TDO/DSDO functions as DSDO
01 = DSCK/AT3 functions as defined by DBGC
DSDI/IRQ5
PTR
functions as defined by DBGC
/AT3 functions as defined by DBGC
TCK/DSCK functions as TCK
TDI/DSDI functions as TDI
TDO/DSDO functions as TDO
10 = Reserved.
11 = DSCK/AT1 functions as DSCK
DSDI/IRQ5
PTR
functions as DSDI
/AT3 functions as PTR
TCK/DSCK functions as TCK
TDI/DSDI functions as TDI
TDO/DSDO functions as TDO
4-10
MPC801 USER’S MANUAL
MOTOROLA
Reset
EBDF—External Bus Division Factor
These bits define the frequency division factor between GCLK1/GCLK2 and GCLK1_50/
GCLK2_50. CLKOUT is similar to GCLK2_50. The GCLK2_50 and GCLK1_50 are used by
the external system, the bus interface, and the memory controller to interface with the
external system. The EBDF bits are initialized during HRESET
using the hard reset
configuration mechanism.
CLES—Core Little-Endian Swap
If this bit is set (1), the little-endian swapper at the external bus interface is activated for core
accesses after reset. If it is cleared (0), the little-endian swapper at the is not activated for
core accesses after reset. See Section 14 Endian Modes for more information.
4.3.2 Soft Reset
When a soft reset event occurs, the MPC801 reconfigures the development port. Refer to
Section 18.3.2.2 Entering Debug Mode and Section 18.3.3.3.1 Clock Mode Selection for
more information.
4
MOTOROLA
MPC801 USER’S MANUAL
4-11
4
Reset
4-12
MPC801 USER’S MANUAL
MOTOROLA
SECTION 5
CLOCKS AND POWER CONTROL
The PowerQUICC has an on-chip oscillator, clock synthesizer, and low-power divider that
gives you a comprehensive set of choices for generating system clocks. They provide you
with many opportunities to save power and system cost without forcing you to sacrifice
flexibility or control. The main timing reference for the MPC801 can be a high frequency
crystal of 4MHz, a low frequency crystal of 32KHz, or an external frequency source at 4MHz
or the system frequency. The on-chip phase-locked loop (PLL) can multiply the output of the
crystal circuit up to the final system frequency. A crystal circuit consists of a parallel resonant
crystal, two capacitors, and two resistors. Notice that the values shown as example values
are based on inhouse designs and your circuit might require slightly different values to
operate properly. Crystals are typically much cheaper than similar speed oscillators, but
they may not be as stable since they are affected by parameters like trace length,
component quality, board layout, and MPC801 shrink level. For the most part, they are
usually stable, but it is impossible to guarantee that they will remain that way because the
MPC801 process may change or the external component may shift.
5
NOTE
The internal frequency of the MPC801 and the output of the
CLKO pins is dependent on the quality of the crystal
circuit and the multiplication factor used in the PLLCR.
The system operating frequency is generated through a programmable phase-locked loop
called the system PLL (SPLL). The SPLL is programmable in integer multiples of input
oscillator frequency to generate the internal operating frequency that should be at least
15MHz. It can be divided by a power of two to generate the system operating frequencies.
Another responsibility of the MPC801 and part of the clock section are the clocks to the
timebase, decrementer, real-time clock, and periodic interrupt counter. The oscillator,
timebase, decrementer, real-time clock, and periodic interrupt counter are all powered by
the keep alive power supply (KAPWR) that allows the counters to continue counting at
32KHz/4MHz, even when the main power to the MPC801 is off. While the power is off, the
periodic interrupt timer can be used to notify the integrated circuit power supply that power
should be sent to the system at specific intervals. This is the power-down wake-up feature.
When the core is not in power-down low-power mode, the keep alive power (KAPWR) is
powered to the same voltage value as that of the I/O buffers and logic. Therefore, if the
internal power supply is 2V and the I/O buffers and logic voltage are 3.3V, the KAPWR is
3.3)V. For more details refer to Section 5.1 The Clock Module and Section 5.10.1
÷
(2.9
Configuration . Figure 5-1 illustrates the clock unit’s functional block diagram.
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MPC801 USER’S MANUAL
5-1
Clocks and Power Control
5
EXTCLK
MODCK[1:2]
2:1
MUX
TBS
TBCLK
VDDSYN
XFC
SPLL
2:1 MUX
( /4 OR /16 )
OSCCLK
VCOOUT
LOCK
2:1 MUX
LOW
POWER
DIVIDERS
(1/2N)
CLOCK
DRIVERS
GCLK2
GCLK1/GCLK2
GCLKC1/GCLKC2
GCLK1_50/GCLK2_50
BRGCLK
SYNCCLK
5-2
CLOCK MODULE AND SYSTEM LOW POWER CONTROL
XTAL
EXTAL
MAIN CLOCK
OSCILLATOR
RTSEL
MUX
/4 OR /512
RTDIV
2:1
Figure 5-1. Clock Unit Block Diagram
MPC801 USER’S MANUAL
CLKOUT
DRIVER
TMBCLK
DRIVER
REAL-TIME CLOCK/PERIODIC
INTERRUPT TIMER
CLOCK AND DRIVER
CLKOUT
TMBCLK
PITRTCLK
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Clocks and Power Control
5.1 THE CLOCK MODULE
The MPC801 clock module consists of the main crystal oscillator, the SPLL, low-power
divider, clock generator/driver blocks, and clock module/system low-power control block.
The clock module and system low-power control block receives control bits from the system
clock control register, the PLL, the low-power and reset control register, and the reset status
register. To improve noise immunity, the charge pump and the VCO of the SPLL have their
own set of power supply pins (VDDSYN and VSSSYN), whereas KAPWR and VSS power
the following clock unit modules.
• Oscillator
• pitrtclk and tmbclk generation logic
•DB
• Decrementer
• Real-time clock
• Periodic interrupt timer
• System clock and reset control register (SCCR)
• PLL low-power and reset control register (PLLRCR)
• Reset status register (RSR)
5
All other circuits are powered by the normal supply pins—VDDH/VDDL and VSS. VDDH
feeds the I/O buffers and logic and VDDL supplies the internal chip logic to reduce system
power consumption. However, the power supply connected to VDDH should be at least as
big as the one connected to VDDL. The power supply for each block is listed in Table 5-1
and described in Section 5.9 Basic Power Structure .
Table 5-1. MPC801 Power Supply
VDDH VDDL VDDSYN KAPWR
I/O Pad Logic X
CLKOUT X
SPLL (Digital) X
Clock Block X
Internal Logic X
Clock Drivers X
SPLL (Analog) X
Main Oscillator X
SCCR, PLLRCR and RSR X
RTC, PIT, TB, and DEC X
NOTE: X denotes that the power supply is used.
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Clocks and Power Control
The following are the relationships between different power supplies:
10%
• VDDH = VDDSYN = 3.3V
• VDDH
• VDDH
• KAPWR
≥
≥
≥
VDDL
KAPWR
≥
2.2V
≥
2V in power-down mode
±
±
10%
VDDH - 0.4V at normal operation
The timing diagram for the internal clocks generated in the MPC801 is illustrated in
Figure 5-2.
5
GCLK1
GCLK2
GCLK1_50
(EBDF=00)
GCLK2_50
(EBDF=00)
CLKOUT
(EBDF=00)
GCLK1_50
(EBDF=01)
GCLK2_50
(EBDF=01)
CLKOUT
(EBDF=01)
T1
T2
5-4
T3
T4
Figure 5-2. MPC801 Clocks Timing Diagram
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MOTOROLA
Clocks and Power Control
GCLK1_50, GCLK2_50, and CLKOUT can have a lower frequency than GCLK1 and
GCLK2. This allows the external bus to operate at lower frequencies as controlled by the
EBDF bit in the SCCR. GCLK2_50 always rises simultaneously with GCLK2. If the MPC801
is working with DFNH = 0, GCLK2_50 has a 50% duty-cycle. With other values of DFNH or
DFNL, the duty-cycle is less than 50%. GCLK1_50 rises simultaneously with GCLK1, but
when the MPC801 is not in gear mode, the falling edge of GCLK1_50 occurs in the middle
of the high phase of GCLK2_50 and EBDF determines the division factor between
GCLK1/2 and GCLK1/2_50. See Figure 5-6 for more information.
To configure the clock source for the SPLL and clock drivers, the MODCK1 and MODCK2
pins are sampled on the rising edge of the PORESET
shown in the table below. MODCK1 specifies the input source to the SPLL and, combined
with MODCK2, specifies the multiplication factor (MF) at reset. If the pitrtclk and tmbclk
configuration and the SPLL multiplication factor must be unaffected in the power-down
low-power mode, the MODCK1 and MODCK2 pins should not be sampled on wake-up from
this mode. In this case, the PORESET
pin should remain negated while the HRESET pin is
asserted during the power-up wake-up stage.
pin. The configuration modes are
5
Table 5-2. Reset Clocks Source Configuration
MODCK [1:2] POR
00 0 513 4 4 Normal operation, PLL enabled.
01 0 5 512 4 Normal operation, PLL enabled.
11 0 5 512 4 Normal operation, PLL enabled.
10 0 1 512 16 Normal operation, PLL enabled.
— 1 — — — The configuration remains unchanged.
DEFAULT
MF + 1
AT POR
PITRTCLK
DIVISION
DEFAULTS
AT POR
TMBCLK
DIVISION
DEFAULTS
AT POR
SPLL OPTIONS
Main timing reference is freq
Main timing reference is freq
Main timing reference is freq
1:1 Mode (freq
clkout(max)
(OSCM)
(OSCM)
(EXTCLK)
= freq
osc(EXTCLK)
= 32 KHz.
= 4 MHz.
= 4 MHz.
)
When the MODCK1 bit is clear (0), the output of the oscillator with a 4MHz or 32MHz
frequency is the input of the SPLL, but when it is set, the external clock input (EXTCLK) is
selected. In all cases, the system clock frequency (freq
) can be reduced by the DFNH
gclk1
and DFNL bits in the SCCR. Notice that the maximum system clock frequency occurs when
the DFNH bits are set to $0. When the MODCK2 bit is set, a 4MHz clock is supplied as
oscclk, but when it is clear (0), the input frequency is either 32KHz (MODCK1=0) or the
maximum system frequency (MODCK1=1). The last case is 1:1 mode.
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Clocks and Power Control
If EXTCLK is the main timing reference (MODCK1=1 @POR) and the oscillator is the timing
reference to the real-time clock and periodic interrupt timer, the frequency of the oscillator
connected to oscillator should be in the 32KHz range. The TBS bit in the system clock and
reset control register (SCCR) can select the timebase clock to be either the SPLL input clock
or gclk2. The periodic interrupt timer and real-time clock frequency and source are specified
by the RTDIV and RTSEL bits in the SCCR. The values of the pitrtclk and tmbclk clock
divisions can be changed by the software. The RTDIV bit value in the SCCR defines the
division of pitrtclk. All possible combinations of the tmbclk divisions are listed in Table 5-3.
Table 5-3. tmbclk Divisions
TBS BIT IN SCCR MODCK1 AT RESET MF + 1 TMBCLK DIVISION
5
1——16
0 0—4
0 1 1, 2 16
01> 24
NOTE
The voltage on the MODCK1 and MODCK2 pins should always
be less than or equal to the VDDH power supply voltage
applied to the part.
5.2 ON-CHIP OSCILLATORS AND EXTERNAL CLOCK INPUT
The oscillator uses either a 3MHz
÷
5MHz (4MHz mode) or a 30KHz
mode) crystal to generate the PLL reference clock. When the oscillator output is the timing
reference to the system, PLL skew elimination between the XTAL, EXTAL, and CLKOUT
pins is not guaranteed.
NOTE
The internal frequency of the MPC801 and the output of the
CLKO pins is dependent on the quality of the crystal circuit and
multiplication factor used in the PLLCR. Please refer
to the sections on phase-lock loop for a description
of the PLL performance.
÷
50KHz (32KHz
The external clock input receives a clock from an external source. The clock frequency can
÷
be either in the range of 3MHz
5MHz or it should be at the system frequency of at least
15MHz (1:1 mode). When the external clock input is the timing reference to the system, PLL
±
skew elimination between the EXTCLK and CLKOUT pins is less than
5-6
MPC801 USER’S MANUAL
1ns.
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Clocks and Power Control
For normal operation, at least one clock source should be active, but you can also configure
both clock sources to be active. In this configuration, EXTCLK provides the oscclk and
oscillator provides the pitrtclk. The input of an unused timing reference should be grounded.
5.3 THE SYSTEM PHASE-LOCKED LOOP
The system PLL performs frequency multiplication and skew elimination and allows the
processor to operate at a high internal clock frequency using a low frequency clock input,
which is a feature with two immediate benefits. Lower frequency clock input reduces the
overall electromagnetic interference generated by the system and oscillating at different
frequencies reduces the cost by eliminating the need to add another oscillator to the system.
The system PLL block diagram is illustrated in Figure 5-3.
XFC
OSCCLK
FEEDBACK
PHASE
COMPARATOR
CLOCK
DELAY
UP
DOWN
CHARGE
PUMP
VDDSYN / VSSSYN
VCO
MULT. FACTOR
MF[0:11]
VCOOUT
Figure 5-3. System PLL Block Diagram
5.3.1 Multiplying the Frequency
The PLL can multiply the input frequency by any integer between 1 and 4,096. The
multiplication factor can be changed by changing the value of the MF bits in the PLL
low-power and reset control register. Even though you can program any integer value from
1 to 4,096, the resulting VCO output frequency must be in the range specified in Section 20
Electrical Characteristics . As defined in Table 5-5, the multiplication factor is set to a
predetermined value during power-on reset.
5.3.2 Eliminating Skew
The PLL is capable of eliminating the skew between the external clock entering the core, the
internal clock phases, and the CLKOUT pin. Therefore, the PLL is useful for tightening
synchronous timings. Skew elimination is only active when the PLL is enabled and
programmed with a multiplication factor of 1 or 2 (MF=0 or 1) and the timing reference to the
system PLL is the external clock input EXTAL. With PLL disabled, the clock skew can be
much larger.
5
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MPC801 USER’S MANUAL
5-7
5
Clocks and Power Control
5.3.3 Operating the PLL Block
The reference signal is sent to the phase comparator that controls the up and down direction
of the charge pump driving the voltage across the external filter capacitor. The direction
selected depends on whether the feedback signal phase lags or leads the reference signal.
The output of the charge pump drives the VCO whose output frequency is divided down and
fed back to the phase comparator for comparison with oscclk. The MF values (0 to 4,095)
are mapped to multiplication factors of 1 to 4,096. Also, when the PLL is operating in 1:1
mode, the multiplication factor is 1(MF=0) and the PLL output frequency is twice the
maximum system frequency. This double frequency is required to generate the GCLK1 and
GCLK2 clocks. Refer to the block diagram in Figure 5-3 for details.
On initial system power-up after keep alive power is lost, power-on reset should be asserted
by the external logic for 3 microseconds after a valid level is reached on the KAPWR supply.
Whenever power-on reset is asserted, the MF bits are set according to Table 5-2 and the
DFNH and DFNL bits in the SCCR are set to the value of 0 ( ÷ 1), respectively. This value
then programs the SPLL to generate the default system frequency of approximately
16.7MHz for a 32KHz input frequency and 20MHz for a 4MHz input frequency.
5.4 THE LOW-POWER DIVIDER
The output of the PLL is sent to a low-power divider block that generates all other clocks in
normal operation, but divides the output frequency of the VCO before it generates the
SYNCCLK, SYNCCLKS, BRGCLK, and general system clocks sent to the rest of the
MPC801. GCLK1C and GCLK2C are the system timing references for the PowerPC core as
well as the instruction and data caches and memory management units. GCLK1 and GCLK2
are the system timing references for all other modules. GCLK1_50 and GCLK2_50 can
operate at a frequency of half the GCLK1 and GCLK2 frequency. The frequency ratio
between GCLK1/2 and GCLK1/2_50 is determined by the EBDF bit in the SCCR.
The purpose of the low-power divider block is to allow you to reduce and restore the
operating frequencies of different sections of the MPC801 without losing the PLL. Using the
low-power divider block, full chip operation can be obtained at a lower frequency. This
feature is called slow-go or gear mode. The selection and speed of the slow-go mode can
be changed at any time and the changes occur immediately. The low-power divider block is
controlled in the SCCR and its default state is to divide all clocks by one. So, for a 40MHz
system, the SYNCCLK, SYNCCLKS, BRGCLK, and general system clocks are each
40MHz.
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Clocks and Power Control
5.5 INTERNAL CLOCK SIGNALS
The internal logic of the MPC801 uses 9 internal clock signals:
• General system clocks—GCLK1C, GCLK2C, GCLK1, GCLK2, GCLK1_50,
and GCLK2_50
• Baud rate generator clock—BRGCLK
• Synchronization clocks—SYNCCLK and SYNCCLKS
The MPC801 also generates an external clock signal called CLKOUT. The PLL
synchronizes these clock signals to each other.
5.5.1 The General System Clocks
The general system clocks—GCLK1C, GCLK2C, GCLK1, GCLK2, GCLK1_50, and
GCLK2_50—are the basic clocks supplied to all modules and submodules on the MPC801.
GCLK1C and GCLK2C are supplied to the PowerPC core, data and instruction caches, and
memory management units and they can be stopped when the core enters the doze
low-power mode. GCLK1 and GCLK2 are supplied to the system interface unit, clock
module, and communication modules.
The external bus clock GCLK2_50 is the same as CLKOUT. The general system clock
defaults to VCO/2 = 40MHz, assuming a 40MHz system frequency. In slow-go mode, the
frequency of the general system clock can be dynamically changed with the SCCR. See
Figure 5-4 for details.
VCO/2 (50 MHZ)
DFNH DIVIDER
DFNL DIVIDER
DFNH
DFNL
Figure 5-4. General System Clocks Select
The general system clock frequency can be switched between different values. The highest
operational frequency can be achieved when the system clock frequency is determined by
DFNH and DFNH=0. The general system clock can be operated at a low or high frequency.
Low is defined by the DFNL bits of the SCCR and high is defined by the DFNH bits.
NORMAL
GENERAL SYSTEM
CLOCK
LOW POWER
5
Software can change the frequency of the general system clock on-the-fly. The general
system clock can be forced to switch to its low frequency. However, in some applications, a
high frequency is required during certain periods. For example, interrupt routines require a
higher performance than a low frequency operation provides, but they consume less power
than a maximum frequency operation provides.
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5
Clocks and Power Control
The MPC801 is capable of automatically switching between low and high frequency
operation whenever one of the following conditions exist:
• A pending interrupt from the interrupt controller occurs. This option is maskable by the
PRQEN bit in the SCCR.
• The POW bit in the core’s machine state register is clear. This option is maskable by
the PRQEN bit in the SCCR.
When none of these conditions exist and the CSRC bit of the PLL low-power reset control
register is set, the general system clock automatically switches back to the low frequency.
When the general system clock is divided, its duty-cycle is changed. One phase remains the
same (12.5ns @ 40MHz) while the other becomes longer. Notice that CLKOUT no longer
has a 50% duty cycle when the general system clock is divided. The CLKOUT waveform is
the same as that of GCLK2_50.
GCLK1 DIVIDE BY 1
GCLK2 DIVIDE BY 1
GCLK1 DIVIDE BY 2
GCLK2 DIVIDE BY 2
GCLK1 DIVIDE BY 4
GCLK2 DIVIDE BY 4
Figure 5-5. Divided System Clocks Timing Diagram
The frequency for system clocks GCLK1and GCLK2 is:
FREQsys
FREQsysmax
---------------------------------------------------------------------- -=
DFNH
2
()
DFNL 1+
or 2
()
The frequency for clocks GCLK1_50 and GCLK2_50 is:
FREQsysmax
FREQ50
---------------------------------------------------------------------- -
=
DFNH
2
()
DFNL 1+
or 2
()
---------------------------
×
EBDF 1+
1
5-10
MPC801 USER’S MANUAL
MOTOROLA
GCLK1
GCLK2
GCLK1_50
(EBDF=00)
GCLK2_50
(EBDF=00)
CLKOUT
(EBDF=00)
GCLK1_50
(EBDF=01)
Clocks and Power Control
5
GCLK2_50
(EBDF=01)
CLKOUT
(EBDF=01)
Figure 5-6. MPC801 Clocks For DFNH = 1 or DFNL = 0 Timing Diagram
5.5.2 The Baud Rate Generator Clock
The baud rate generator clock (BRGCLK ) is used by the communication modules and the
memory controller refresh counter. It defaults to VCO/2 = 40MHz, assuming a 40MHz
system frequency. The purpose of BRGCLK is to allow the communication modules to
continue operating at a fixed frequency, even when the rest of the MPC801 is operating at
a reduced frequency. The baud rate generator clock frequency is:
FREQbrg
FREQsysmax
-------------------------------------------=
×
2 DFBRG
()
2
5.5.3 The Synchronization Clocks
The synchronization clock (SYNCCLK) is used by the serial synchronization circuitry in the
serial ports of the communication modules and includes the serial interface, serial
communication controllers, and serial management controllers. It synchronizes externally
generated clocks before they are used internally. SYNCCLK defaults to VCO/2 = 40MHz,
assuming a 40MHz system frequency. The SYNCCLK is used by the serial interface internal
logic.
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Clocks and Power Control
The purpose of SYNCCLK is to allow the communication modules to continue operating at
a fixed frequency, even when the rest of the MPC801 is operating at a reduced frequency.
Thus, the SYNCCLK allows you to maintain the serial synchronization circuitry at the
preferred rate, while lowering the general system clock to the lowest possible rate. However,
SYNCCLK must always have a frequency at least as high as the general system clock
frequency, be at least two times the preferred serial clock rate, and at least two and half
times the preferred serial clock rate if the timeslot assigner in the serial interface is used.
The SYNC clock frequency is:
5
FREQsync
FREQsysmax
---------------------------------------------- -=
×
2 DFSYNC
()
2
The CLKOUT is the same as GCLK2_50. It defaults to VCO/2 = 40MHz, assuming a 40MHz
system frequency. The SCCR controls whether it drives full strength, half strength, or is
disabled. Disabling or decreasing the strength of CLKOUT can reduce power consumption,
noise, and electromagnetic interference on the printed circuit board. When the PLL is
acquiring lock, the CLKOUT signal is disabled and remains in the low state.
5.6 THE PHASE-LOCKED LOOP PINS
The following pins are dedicated to PLL operation.
NOTE
The internal frequency of the MPC801 and the output of the
CLKO pins is dependent on the quality of the crystal circuit and
the MF bits of the PLPRCR. Please refer to the sections on
phase-lock loop for details about PLL performance.
VDDSYN—Drain Voltage
The VDD pin is dedicated to analog PLL circuits. The voltage should be well-regulated and
the pin should be provided with an extremely low-impedance path to the VDD power rail.
F capacitor located as close as possible
VDDSYN should be bypassed to VSSSYN by a 0.1
to the chip package.
µ
VSSSYN—Source Voltage
The VSS pin is dedicated to analog PLL circuits. It should be provided with an extremely low
µ
impedance path to ground and bypassed to VDDSYN by a 0.1
F capacitor located as close
as possible to the chip package. It is recommended that you also bypass VSSSYN to
VDDSYN with a 0.01uF capacitor as close as possible to the chip package.
VSSSYN1—Source Voltage 1
The VSS pin is dedicated to the analog PLL circuits. It should be provided with an extremely
low-impedance path to ground.
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Clocks and Power Control
XFC—External Filter Capacitor
This pin connects to the off-chip capacitor for the PLL filter. One terminal of the capacitor is
connected to XFC and the other is connected to VDDSYN.
NOTE
30M Ω is the minimum parasitic resistance value that ensures
proper PLL operation when connected in parallel
with the XFC capacitor.
Table 5-4. XFC Capacitor Values
MINIMUM CAPACITANCE MAXIMUM CAPACITANCE UNIT
MF < = 4 XFC = MF * 425 - 125 XFC = MF * 590 - 175 pF
5
MF > 4 XFC = MF * 520 XFC = MF * 920 pF
5.7 CONTROLLING THE SYSTEM CLOCK
The system phase-loop lock has a 32-bit control register that is powered by keep alive
power. This system clock and reset control register (SCCR) is memory-mapped into the
MPC801 system interface unit register map.
SCCR
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD
BIT
FIELD
Bits 0, 3–5, and 9—Reserved
These bits are reserved and should be set to 0.
COM—Clock Output Mode
These bits control the output buffer strength of the CLKOUT pin. When both bits are set, the
CLKOUT pin is held in the high (1) state. These bits can be dynamically changed without
generating spikes on the CLKOUT pin. If the CLKOUT pin is not connected to external
circuits, both bits (disabling CLKOUT) should be set to minimize noise and power
dissipation. The COM bits are cleared by a hard reset.
RES COM RESERVED TBS RTDIV RTSEL RES PRQEN RESERVED EBDF RES
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RES DFSYNC DFBRG DFNL DFNH RESERVED
00 = Clock output enabled full-strength output buffer.
01 = Clock output enabled half-strength output buffer.
10 = Reserved.
11 = Clock output disabled.
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5
Clocks and Power Control
TBS—Timebase Source
This bit determines the clock source that drives the timebase and decrementer.
0 = TB frequency source is the crystal oscillator frequency divided by 4 or 16.
1 = TB frequency source is the system clock divided by 16.
RTDIV—Real-Time Clock Divide
This bit indicates if the clock to the real-time clock and periodic interrupt timer is additionally
divided by 128. At power-on reset this bit is cleared if both MODCK[1] and MODCK[2] are
zeros. Otherwise, it is set.
0 = The real-time clock and periodic interrupt timer are divided by 4.
1 = The real-time clock and periodic interrupt timer are divided by 512.
RTSEL—Real-Time Clock Circuit Input Source Select
This bit specifies the input source to the real-time clock. At power-on reset, this bit receives
the value of the MODCK[1] bit.
0 = The real-time clock and periodic interrupt timer are divided by 4.
1 = The real-time clock and periodic interrupt timer are divided by 512.
PRQEN—Power Management Request Enable
This bit specifies whether or not the general system clock returns to the high frequency
defined by DFNH while there is a pending interrupt from the interrupt controller or POW bit
in the machine state register is clear. This bit is cleared by power-on or hard reset.
0 = The system remains in the lower frequency defined by DFNL even if there is a
pending interrupt from the interrupt controller or POW bit in the machine state
register is cleared.
1 = The system switches to high frequency defined by DFNH when there is a pending
interrupt from the interrupt controller or POW bit in the machine state register is
cleared.
Bits 11–12 and 15–16—Reserved
These bits are reserved and should be set to 0.
EBDF—External Bus Division Factor
These bits define the frequency division factor between GCLK1/GCLK2 and GCLK1_50/
GCLK2_50. CLKOUT is similar to GCLK2_50. The GCLK2_50 and GCLK1_50 are used by
the external master, bus interface, and memory controller to interface with the external
system. These bits are initialized during HRESET
using the hard reset configuration
mechanism.
00 = CLKOUT is GCLK2 divided by 1.
01 = CLKOUT is GCLK2 divided by 2.
1x = Reserved.
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Clocks and Power Control
DFSYNC—Division Factor for the SYNCCLK
These bits define the SYNCCLK and SYNCCLKS frequencies. Changing the value of these
bits does not result in a loss-of-lock condition. These bits are cleared by the power-on or
hard reset.
00 = Divide by 1 (normal operation).
01 = Divide by 4.
10 = Divide by 16.
11 = Divide by 64.
DFBRG—Division Factor for the BRGCLK
These bits define the BRGCLK frequency. Changing the value of these bits does not result
in a loss-of-lock condition. These bits are cleared by the power-on or hard reset.
00 = Divide by 1 (normal operation).
01 = Divide by 4.
10 = Divide by 16.
11 = Divide by 64.
5
DFNL—Division Factor Lowest Frequency
These bits are required for two reasons—to reduce the general system clock to a frequency
lower than that which can be obtained in the DFNH bits and to automatically switch between
the DFNL and DFNH rates. These bits are cleared by the power-on or hard reset.
These bits can be loaded with the preferred divide value and the CSRC bit must be set to
change the frequency. Changing the value of these bits does not result in a loss-of-lock
condition. These bits are cleared by system reset.
000 = Divide by 2.
001 = Divide by 4.
010 = Divide by 8.
011 = Divide by 16.
100 = Divide by 32.
101 = Divide by 64.
110 = Reserved.
111 = Divide by 256.
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Clocks and Power Control
DFNH—Division Factor High Frequency
Changing the value of these bits does not result in a loss-of-lock condition. These bits are
cleared by power-on or hard reset. These bits can be loaded at any time to change the
general system clock rate.
000 = Divide by 1.
001 = Divide by 2.
010 = Divide by 4.
011 = Divide by 8.
100 = Divide by 16.
101 = Divide by 32.
110 = Divide by 64.
111 = Reserved.
Bits 27–31—Reserved
These bits are reserved and should be set to 0.
5.8 PLL LOW-POWER AND RESET CONTROL REGISTER
The 32-bit PLL low-power and reset control register (PLPRCR) is powered by a keep alive
power supply. This register is memory-mapped into the MPC801 serial interface unit register
map.
PLPRCR
BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FIELD
BIT 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
FIELD
SPLSS TEXPS RES TMIST RES CSRC LPM CSR LOLRE FIOPD RESERVED
MF—Multiplication Factor
The output of the voltage control oscillator (VCO) is divided to generate the feedback signal
that goes to the phase comparator. The MF bits control the value of the divider in the SPLL
feedback loop. The phase comparator determines the phase shift between the feedback
signal and the reference clock. This difference results in an increase or decrease in the VCO
output frequency.
The MF bits can be read and written at any time. Changing the MF bits causes the SPLL to
lose lock. All clocks are disabled until PLL reaches lock condition. The normal reset value
for the DFNH bits is $0 or divided by one. When the PLL is operating in 1:1 mode, the
multiplication factor is set to 1 (MF=0). See Table 5-2 for details.
MF RESERVED
SPLSS—System PLL Lock Status Sticky
This bit is not affected by hard reset. An out-of-lock indication sets the SPLSS bit and it
remains set until the software clears it. At power-on reset, the state of the SPLSS bit is zero.
5-16
MPC801 USER’S MANUAL
MOTOROLA
Clocks and Power Control
The SPLSS bit is negated by writing a 1 (writing a zero has no effect). The SPLSS bit is not
affected by zero because of a software-initiated loss of lock, which is defined as an
multiplication factor change or entering deep sleep and power-down modes.
0 = SPLL has remained in lock.
1 = SPLL has gone out of lock at least once, but not because of a change with the
PLLEN or MF bits.
TEXPS—Timer Expired Status
This bit is set by a reset. If it is enabled, TEXPS is asserted when the periodic timer expires,
the real-time clock alarm sets, timebase clock alarm is set, or the decrementer interrupt
occurs. The bit stays set until the software clears it. TEXPS is negated by writing a 1 (writing
a zero has no effect). When TEXPS is set, the TEXP external signal is asserted and when
it is reset, the TEXP external signal is negated.
0 = TEXP is negated.
1 = TEXP is asserted.
TMIST—Timers Interrupt Status
This bit is cleared at reset and is set when either the real-time clock, periodic interrupt timer,
timebase, or decrementer interrupt occurs. It is cleared by writing a 1 (writing a zero has no
effect). The system clock frequency remains at a high frequency value defined by the DFNH
bits if the TMIST bit is set. The clock frequency remains high if the CSRC bit in the PLPRCR
is set and there are no conditions for switching to normal low mode.
5
0 = No timer expiration event is detected.
1 = A timer expiration event is detected.
CSRC—Clock Source
This bit specifies the bit that determines the general system clock—DFNH or DFNL. Setting
this bit switches the general system clock to the DFNL value needed to enter slow-go
low-power mode. Clearing this bit switches the general system clock to the DFNH value.
CSRC is cleared at hard reset.
0 = General system clock is determined by the DFNH value
1 = General system clock is determined by the DFNL value
LPM—Low-Power Modes
These bits are encoded to provide one normal operating mode and four low-power modes.
In normal and doze modes, the system can be in the high state defined by the DFNH bits or
in the low state defined by the DFNL bits. The normal high operating mode is the state out
of reset. This is also the state the bits defer to when the low-power mode exit signal arrives.
In addition, there are four low-power modes—doze, sleep, deep sleep, and power-down.
Table 5-5 provides more details on these bits.
MOTOROLA MPC801 USER’S MANUAL 5-17
Clocks and Power Control
Table 5-5. MPC801 Low-Power Modes
5
OPERATION
MODE
Normal High
LPM=00 Active
Normal Low
(“Gear”)
LPM=00
Doze High
LPM=01
Doze Low
LPM=01
Sleep
LPM=10
Deep Sleep
LPM=11
TEXPS=1
Power-Down
LPM=11
TEXPS=0
SPLL CLOCKS
Full
Freq. div
DFNH
2
Full
Active
Active
Active
Active Not
Active
Active
Not
Not
Freq. div
DFNL+1
2
Full
Freq. div
DFNH
2
Full
Freq. div
DFNL+1
2
Active
Not
Active
Not
Active
WAKE-UP
METHOD
Software
Interrupt
Interrupt
Interrupt
Interrupt 3-4 Maximum System clocks <10 mW Enabled: RTC, PIT,
Interrupt <500 Oscillator Cycles
Interrupt <500 Oscillator Cycles + Power
RETURN TIME FROM WAKE-UP
EVENT TO NORMAL HIGH
——
or
Asynchronous Interrupts:
3-4 Maximum System Cycles
Synchronous Interrupts:
3-4 Actual System Cycles
16 msec-32 KHz
125
µ
sec-4 MHz
Supply Wake-Up
(PwSp_Wake+ 16 msec) @ 32 KHz
MPC801 POWER
CONSUMPTION
AT 50MHZ
×
20 mWatt+
DFNH
1/2
Watt
×
20 mWatt+
(DFNL+1)
1/2
Watt
×
20mWatt+
DFNH
0.4/2
Watt
×
20 mWatt+
(DFNL+1)
TBD
Watt
µ
A,
°
C
0.4/2
32 KHz- ~10
KAPWR = 3.0 V
Temperature=50
FUNCTIONALITY
Full Functions Not In
Use Are Shut Off
Enabled: RTC, PIT,
and MEMC,
Disabled: Extended
Core
TB, and DEC
Table 5-5 describes all possible transfers between low-power modes. The MPC801 enters
a low-power mode by setting the LPM bits appropriately. This can only be done in one of the
normal modes and not in the doze mode. Exiting from low-power modes occurs through an
asynchronous or synchronous interrupt. An enabled asynchronous interrupt clears the LPM
bits, but does not change the PLPRCR
bit. The asynchronous interrupt is responsible
CSRC
for exiting from normal, low doze high, low, and sleep modes to normal high mode. The
asynchronous interrupt sources are:
• Asynchronous wake-up interrupt from the interrupt controller
• Real-time clock, periodic interrupt timer, timebase, or decrementer interrupts (if
enabled)
5-18 MPC801 USER’S MANUAL MOTOROLA
Clocks and Power Control
SOFTWARE *
SOFTWARE *
SOFTWARE *
SOFTWARE *
SOFTWARE *
SOFTWARE *
NORMAL LOW
LPM=00, CSRC=1
DOZE LOW
LPM=01, CSRC=1
DOZE HIGH
LPM=01, CSRC=0/1
SLEEP MODE
LPM=10, CSRC=0
DEEP SLEEP MODE
LPM=11, CSRC=0,
TEXPS=1
POWER DOWN MODE
LPM=11, CSRC=0,
TEXPS=0**
INTERRUPT
WAKE-UP: 3-4 SYSFREQ
CLOCKS
ASYNCHRONOUS
INTERRUPTS
WAKE-UP: 3-4 SYSFREQMAX
CLOCKS
ASYNC. WAKE-UP OR REAL-TIME CLOCK,
PERIODIC INTERRUPT TIMER, TIMEBASE,
OR DECREMENTER I INTERRUPT
WALK-UP: 500 INPUT
FREQUENCY CLOCKS
REAL-TIME CLOCK, PERIODIC INTERRUPT
TIMER, TIMEBASE, OR DECREMENTER
INTERRUPT FOLLOWED
BY EXTERNAL HARD RESET
OR EXTERNAL HARD RESET
5
NORMAL
HIGH MODE
LPM=00
CSRC=0/1
SOFTWARE *
HARD RESET
* SOFTWARE IS ACTIVE ONLY IN NORMAL HIGH/LOW MODES
** TEXPS RECEIVES THE ZERO VALUE BY WRITING ONE. WRITING A ZERO HAS NO EFFECT ON TEXPS.
*** THE SWITCH FROM NORMAL HIGH TO NORMAL LOW IS ENABLED ONLY IF THE CONDITIONS TO ASYNCHRONOUS
INTERRUPT ARE CLEARED
Figure 5-7. MPC801 Low-Power Modes Flowchart
MOTOROLA MPC801 USER’S MANUAL 5-19
5
Clocks and Power Control
The system responds quickly to an asynchronous interrupt. The wake-up time from normal
low, doze high/low, and sleep mode due to an asynchronous interrupt is only 3
to 4 clocks
of maximum system frequency. In a 40MHz system, this wake-up takes 75ns to 100ns. The
asynchronous wake-up interrupt from the interrupt controller is level sensitive. Therefore, it
is negated only after the cause of the interrupt in the interrupt controller is cleared. The
real-time clock, periodic interrupt timer, timebase, or decrementer interrupts set status bits
in the PLPRCR. The clock module views this interrupt as a pending asynchronous interrupt
as long as the TMIST bit is set. Therefore, the TMIST status bit should be cleared before
entering any low-power mode other than normal high mode.
The wake-up time due to synchronous interrupt sources from the interrupt controller is
measured in actual system clocks. It takes 2 to 4 system clocks from the interrupt event
before the system reaches normal high mode. In a 50MHz system where DFNL=111
(divided by 256), the wake-up time is 12.8 to 25.6µs. In normal and doze modes, if the
PLPRCR
bit is set, the system toggles between low frequency (defined by the DFNL
CSRC
bit) and high frequency (defined by DFNL/DFNH) states. The conditions to switch from
normal low mode to normal high state are:
• A pending interrupt from an interrupt controller must occur
• The POW bit in the machine state register must be cleared (normal mode)
If none of these conditions exist, the PLPRCR
bit is set, the asynchronous interrupt
CSRC
status bits are reset, and the system switches back to normal low mode. A pending interrupt
from the interrupt controller transfers the system from doze mode to normal high mode. An
exit from deep sleep mode is caused by:
• An asynchronous wake-up interrupt from the interrupt controller
• Real-time clock, periodic interrupt timer, timebase, or decrementer interrupts (if
enabled)
In deep sleep mode, the PLL is disabled and the wake-up time from this mode is a maximum
of 500 PLL input frequency clocks. In 1:1 mode the wake-up time can be up to 1,000 PLL
input frequency clocks. If the PLL input frequency is 32KHz the wake-up time is less than
15.6ms and if it is 4MHz the wake-up time is less then 125µs.
An exit from power-down mode is accomplished with a hard reset that should be asserted
by external logic in response to the TEXPS bit and TEXP pin assertion. The TEXPS bit is
asserted by an enabled real-time clock, periodic interrupt timer, timebase, or decrementer
interrupt. The hard reset takes longer than the time it takes the power supply to wake up, in
addition to the time it takes the PLL to lock. Hard reset assertion when the TEXPS bit and
TEXP pin are clear, sets the bit and the pin values, thus causing an exit from power-down
low-power mode. For more details on power-down mode, refer to Section 5.10.1
Configuration.
5-20 MPC801 USER’S MANUAL MOTOROLA
Clocks and Power Control
NOTE
The chip is only allowed to enter deep sleep low-power mode
and power-down mode if the main timing reference
is a 32KHz crystal oscillator.
CSR—Checkstop Reset Enable
If this bit is set, an automatic reset is generated when the core signals that it has entered
checkstop mode, unless debug mode is enabled at reset. If the bit is clear and debug mode
is not enabled, then the system interface unit does nothing when a checkstop signal is
received from the core. However, if debug mode is enabled, then the part enters debug
mode when entering checkstop mode. In this case, the core does not assert the checkstop
signal to the reset circuitry.
0 = The checkstop condition does not cause automatic reset.
1 = The checkstop condition causes automatic reset.
LOLRE—Loss of Lock Reset Enable
This bit specifies the manner in which the clocks handle a loss of lock indication. When this
bit is clear, a hard reset is not asserted if a loss of lock indication occurs. However, when it
is set, a hard reset is asserted when a loss-of-lock indication occurs.
0 = Loss of lock does not cause reset.
1 = Loss of lock causes reset.
5
FIOPD—Force I/O Pull Down
This bit indicates whether the address and data external pins are driven by an internal
pull-down device at sleep and deep sleep low-power modes. When this bit is set and the
chip is either in sleep or deep sleep low-power mode, the A and D external pins are driven
to zero. When this bit is set and the chip is not in sleep or deep sleep low-power modes (or
when FIOPD is cleared), the A and D external pins are unaffected.
0 = The address and data pins are not driven by an internal pull-down device.
1 = The address and data pins are driven by an internal pull-down device.
MOTOROLA MPC801 USER’S MANUAL 5-21
5
Clocks and Power Control
5.9 BASIC POWER STRUCTURE
The MPC801 provides a wide range of possibilities for power supply connection.
Figure 5-9 illustrates the different power supply sources for each one of the basic units on
the chip. For more details about the relationships between the power supplies, refer to
Section 5.1 The Clock Module.
The I/O buffers, logic, and clock block are fed by a 3.3V power supply that allows them to
function in a TTL-compatible range of voltages. The internal logic can be fed by a 3.3 or 2V
source allowing a considerable reduction in power consumption. The PLL is fed by a 3.3V
power supply (VDDSYN) to achieve a high stability in its output frequency. The oscillator,
real-time clock, periodic interrupt timer, timebase, or decrementer are all fed by the KAPWR
rail, thus allowing the external power supply unit to disconnect all other subunits at
low-power deep sleep mode. The TEXP pin (fed by the same rail) can switch between
sources using the external power supply unit.
I / O
INTERNAL LOGIC
VDDL
PLL
VDDSYN
OSCILLATOR,
PERIODIC INTERRUPT
TIMER, TIMEBASE,
REAL-TIME CLOCK,
AND DECREMENTER
CLOCK CONTROL
Figure 5-8. MPC801 Basic Power Supply Configuration
TEXP
KAPWR
VDDH
5-22 MPC801 USER’S MANUAL MOTOROLA
Clocks and Power Control
5.10 KEEP ALIVE POWER
5.10.1 Configuration
An example of a switching scheme for an optimized low-power system is illustrated in
Figure 5-9.
SW1
MAIN POWER
VDDSYN
SUPPLY
3.3 V 2.0 V
SW2
SW3
2.4-3.3V
BACKUP
POWER
SUPPLY
MPC801
VDDH
VDDL
KAPWR
TEXP
SWITCH
LOGIC
Figure 5-9. External Power Supply Scheme (2.0 V Internal Voltage)
SW1 and SW2 can be unified in one switch if VDDSYN and VDDH are supplied by the same
source. If VDDL is fed with 3.3V, SW2 and SW3 can be combined into one switch. The TEXP
signal, if enabled, is asserted by the MPC801 when the real-time clock or timebase time
value matches the value programmed in its associated alarm register or when the periodic
interrupt timer or decrementer decrements their value to zero. The TEXP signal is negated
when writing to the TEXPS status bit with the corresponding data bit being 1. The KAPWR
power supply feeds the oscillator. The condition for main crystal oscillator stability is that the
power supply value changes slowly. The maximum slope of the KAPWR power supply
should be less than 1.7V/mS for a 32KHz input frequency. An exponential model of voltage
change on the KAPWR rail should ensure that
τ > 20/freq
oscm
.
5
MOTOROLA MPC801 USER’S MANUAL 5-23
5
Clocks and Power Control
5.10.2 The Key Mechanism
All the registers defined in the system integration, decrementer, timebase timers, and the
clocks and reset of Table 3-1 are powered by the KAPWR supply. When power-down mode
is entered, the value stored in these registers is preserved when the main power supply is
disconnected. If this requirement is not met, data loss can occur in these registers. To
reduce the possibility of data loss, the MPC801 includes a key mechanism that ensures data
retention on locked registers. While a register is locked, all writes are ignored and a machine
check exception is generated.
Each of the registers in the KAPWR region has a key that can be in an open or locked state.
At power-on reset, all keys are in the open
Each key also has an address in the internal memory map. A 0x55CCAA33 write to this
location changes the key to the open
the key to the locked state.
POWER-ON RESET
state, except for the real-time clock registers.
state. Writing any other data to this location changes
OPEN
WRITE TO THE KEY OTHER VALUE
LOCKED
WRITE TO THE KEY0X55CCAA33
Figure 5-10. Key Mechanism Diagram
The key registers for the system integration timer and the clock and reset registers are
defined in Table 3-1.
5-24 MPC801 USER’S MANUAL MOTOROLA
SECTION 6
THE POWERPC CORE
The core is the module of the MPC801 where the PowerPC
It has the functionality of the PowerPC branch and fixed-point processors, in addition to all
the PowerPC user mode instructions (with the exception of the floating-point instructions)
and all the registers associated with them. It also contains part of the development support
features of the MPC801, including breakpoint and watchpoint support, program flow tracking
data generation, and debug mode operation in which the chip is controlled by the
development support system through the debug port module.
This section describes the functional specifications of the core. It is based on a document
called the
architecture of the PowerPC in great detail.
PowerPC Family: The Programming Environment (MPCFPE/D)
NOTE
As needed, this manual only contains references to
those documents and does not duplicate any
information already specified there.
™
architecture is implemented.
that explains the
6.1 FEATURES
The following list provides the main features of the MPC801 core:
• 32-bit PowerPC Architecture
• Single-Issue Integer Machine
• Variable Pipeline Depth Architecture Tailored to Instruction Complexity
• Out-of-Order Execution Termination
• Branch Prediction for Prefetch
• 32 × 32 Bit General-Purpose Register File
• Precise Exception Model
• Extensive Debug/Testing Support
6
MOTOROLA
MPC801 USER’S MANUAL
6-1
The PowerPC Core
6.1.1 Basic Structure of the Core
To accomplish its tasks, the core is divided into the following subunits:
• Sequencer Unit —Consists of the branch processor, the instruction prefetch queue,
and the interrupt handling mechanism. It controls some data structures within the
register unit.
• Register Unit —Consists of all the user-visible registers, the register’s scoreboard
mechanism, and a history of previous operations to allow for a precise interrupt model.
This module is physically split so that each data structure is implemented near the area
where it is used.
• Fixed-Point Unit —Consists of all fixed-point instruction implementations, except load/
store. This module is subdivided into the following two execution units:
— IMUL/IDIV—Fixed-point multiply and divide instruction implementations
— ALU/BFU—Fixed-point logic, add, and subtract instruction implementations, as well
6
as the bit field instructions.
• Load/Store Unit —Consists of all load and store instructions, except floating-point
processor load and store.
6.1.2 Instruction Flow Within the Core
When fetched, instructions enter the instruction queue, thus enabling branch folding by
allowing out-of-order branch execution. Nonbranch instructions reaching the top of the
instruction queue are issued to the execution units. Instructions can be flushed from the
instruction queue when an exception on a previous instruction, interrupt, or miss-predicted
fetch occurs.
All instructions, including branches, enter the history buffer along with processor state
information that can be affected by the instruction’s execution. This information is used to
enable out-of-order completion of instructions together with precise exception handling.
When exceptions or interrupts occur, instructions can be flushed or recovered from the
machine. The instruction queue is always flushed when the history buffer is recovered. An
instruction retires from the machine after it finishes executing without exception and all
preceding instructions are retired from the machine. Figure 6-1 illustrates the core’s
microarchitecture.
6-2
MPC801 USER’S MANUAL
MOTOROLA
The PowerPC Core
INSTRUCTION CACHE /INSTRUCTION MMU INTERFACE DATA CACHE / DATA MMU INTERFACE
CORE
SEQUENCER
CONTROL BUS
WRITEBACK BUS
(2 SLOTS / CLOCK)
SOURCE BUSES
(4 SLOTS / CLOCK)
NEXT ADDRESS
GENERATION
CONTR
REGS
(32 X 32)
Figure 6-1. Core Block Diagram
RETIRE
GPR
BRANCH
UNIT
HISTORY
IMUL /
IDIV
WRITEBACK
INSTRUCTION
QUEUE
ALU /GPR
BFU
L-ADDR
LDST
ADDR
EXECUTION UNITS
L-DATA
6
LDST
FIX
DATA
INSTRUCTION QUEUE
MOTOROLA
HISTORY BUFFER
Figure 6-2. Instruction Flow Conceptual Diagram
ISSUE
FETCH
MPC801 USER’S MANUAL
BRANCH
UNIT
6-3
The PowerPC Core
6.1.3 Basic Instruction Pipeline
Figure 6-3 illustrates basic instruction pipeline timing.
6
FETCH
DECODE
READ + EXECUTE
WRITEBACK
L ADDRESS DRIVE
L DATA
LOAD WRITEBACK
BRANCH DECODE
BRANCH EXECUTE
i1 i3i2
i1 i2
i1 i2
i1 i2
i1
LOADSTORE
i1
i1
i1
Figure 6-3. Basic Instruction Pipeline Timing Diagram
6.2 THE SEQUENCER UNIT
The instruction sequencer is the heart of the core. It centrally controls the data flow between
execution units and register files. The sequencer implements the basic instruction pipeline,
fetches instructions from the memory system, issues them to available execution units, and
maintains a state history so it can back up the machine if an exception occurs. In addition,
the sequencer unit implements all branch processor instructions, including flow control and
condition register instructions. The sequencer data path is illustrated in Figure 6-4.
6.2.1 Flow Control
Flow control operations are expensive to execute because they disrupt normal instruction
pipeline flow. A change in program flow creates bubbles in the pipeline because of the time
it takes to fetch the newly targeted instruction stream. In typical code, with 4 or 5 sequential
instructions between branches, the machine could waste up to 25% of its execution
bandwidth waiting on branch latency.
6-4
MPC801 USER’S MANUAL
MOTOROLA
The PowerPC Core
INSTRUCTION MEMORY SYSTEM
32
INSTRUCTION BUFFER
32
INSTRUCTION
PREFETCH
QUEUE (4)
32
READ / WRITE
BUSES
INSTRUCTION ADDRESS GENERATOR
CC UNIT
EXECUTION UNITS AND REGISTERS FILES
BRANCH
CONDITION
EVALUATION
Figure 6-4. Sequencer Data Path
To execute branches in parallel with the execution of sequential instructions, the sequencer
maintains an instruction prefetch queue that is four instructions deep. In an ideal situation,
a sequential instruction would be issued every clock, even when branches are present in the
code. This is referred to as branch folding. The instruction prefetch queue also eliminates
stalls caused by long latency instruction fetches and all instructions are fetched into the
instruction prefetch queue, but only sequential instructions are issued to the execution units
when they reach the head of the queue. The reason branches enter the queue is for
watchpoint marking (refer to Section 18 Development Support for details). Since
branches do not prevent the issue of sequential instructions unless they come in pairs, the
performance impact of entering branches in the instruction prefetch queue is negligible.
6
In addition to branch folding, the core implements a branch reservation station and static
branch prediction so branches can issue as early as possible. The reservation station allows
a branch instruction to issue even before its condition is ready. With the branch issued and
out of the way, instruction prefetch can continue while the branch operand is being
computed and the condition evaluated. Static branch prediction determines the instruction
stream to be prefetched while the branch is being resolved. When the branch operand
becomes available, it is forwarded to the branch unit and the condition is evaluated.
MOTOROLA
MPC801 USER’S MANUAL
6-5
The PowerPC Core
Branch instructions whose condition is unavailable and forced to issue to the reservation
station are predicted and these branches, which later turn out to have followed the wrong
path, are mispredicted. Branch instructions that issue with source data already available are
unpredicted and those instructions fetched under a predicted branch are fetched
conditionally. The core ignores conditionally prefetched instructions fetched under a
mispredicted branch.
Table 6-1. Branch Prediction Policy
6
BRANCH TYPE
BC With Negative Offset Taken Fall Through
BC With Positive Offset Fall Through Taken
BCLR or BCCTR (lk or ctr) Address Ready Fall Through Taken
BCLR or BCCTR (lk or ctr) Address Not Ready Wait Wait
B (Unconditional Branch) Taken Taken
DEFAULT
PREDICTION (Y=0)
MODIFIED
PREDICTION (Y=1)
6.2.2 Issuing Instructions
The sequencer attempts to issue a sequential instruction on each clock whenever possible.
However, for an instruction to issue, the execution unit must be available and the required
source data is available and no other executing instruction targets the same destination
register. The sequencer informs the execution units of the instruction’s existence on the
instruction bus. The execution units then decode the instruction, interrogate the register unit,
and inform the sequencer that it accepts the instruction for execution.
6.2.3 Interrupts
The core interrupts can be generated when an exception occurs. An exception results when
an instruction is executed or an asynchronous external event occurs. There are five
exception sources in the MPC801:
• External interrupt request
• Certain memory access conditions
• Internal errors, such as an attempt to execute an unimplemented opcode or
floating-point arithmetic overflow
• Trap instructions
• Internal exceptions
6-6
MPC801 USER’S MANUAL
MOTOROLA
The PowerPC Core
Interrupt handling is transparent to user mode code. The core uses the same mechanism to
handle all types of exceptions. When a user mode instruction experiences an exception, the
machine is placed into privileged state and control is transferred to a software exception
handler routine located at some offset within a memory-based vector table.
Each interrupt generated in the machine transfers control to a different address in the vector
table. For more information on initializing the base address of the vector table, refer to
Table 6-13 as well as the PowerPC definition of the machine state register. When the
exception has been handled, the handler can resume execution of the user program without
the knowledge that such an event ever occurred.
As specified in
PowerPC Family: The Programming Environment
, the core implements a
precise interrupt model. An interrupt usually occurs under one of the following conditions:
• No instruction that logically follows the faulting instruction in the code stream has
started executing.
• All instructions preceding the faulting instruction have completed with respect to the
executing processor.
• The precise location (address) of the faulting instruction is known to the exception
handler.
• The instruction causing the exception may not have started executing (“before
interrupt”), could be partially completed, or has completed (“after interrupt”) depending
on the interrupt and instruction types. See Table 6-2 for details.
In any case, a partially completed instruction is restartable and can be reexecuted after the
interrupt is handled. This precise exception model can simplify and speed up exception
processing because the software does not have to manually save the machine’s internal
pipeline states, unwind the pipelines, or cleanly terminate the faulting instruction stream. Nor
does it have to reverse the process to resume execution of the faulting stream.
6
MOTOROLA
MPC801 USER’S MANUAL
6-7
The PowerPC Core
Table 6-2. “Before” and “After” Interrupts
6
INTERRUPT TYPE
Hard Reset Any NA Undefined
System Reset Any Before Next Instruction to Execute
Machine Check Interrupt Any Before Faulting Instruction
Implementation Specific Instruction / Data TLB Miss / Error Interrupts Any Before Faulting Fetch or Load/Store
Other Asynchronous Interrupts (Noninstruction Related Interrupts) Any Before Next Instruction to Execute
Alignment Interrupt Load / Store Before Faulting Instruction
Privileged Instruction Any Privileged
Trap tw, twi Before Faulting Instruction
System Call Interrupt sc After Next Instruction to Execute
Trace Any After Next Instruction to Execute
Debug I- Breakpoint Any Before Faulting Instruction
Debug L- Breakpoint Load / Store After Faulting Instruction + 4
Implementation Dependent Software Emulation Interrupt NA Before Faulting Instruction
Floating Point Unavailable Floating Point Before Faulting Instruction
INSTRUCTION
TYPE
Instruction
BEFORE /
AFTER
Before Faulting Instruction
CONTENTS OF SRR0
6.2.4 Precise Exception Model Implementation
To achieve maximum performance, many pieces of the instruction stream are concurrently
processed by the core, regardless of the sequence specified by the executing program.
Instructions execute in parallel and are completed out of order. The hardware works hard to
ensure that this out-of-order operation never has any effect besides the one specified by the
program. This is most difficult to safeguard when an interrupt occurs after instructions that
logically follow the faulting instruction or have already completed. At the time of an interrupt,
the machine state becomes visible to other processes and, therefore, must be in the
appropriate architecturally specified condition. The core takes care of this in the hardware
by automatically backing up the machine to the instruction that caused the interrupt. By
doing it, the core implements a precise exception model. This is, of course, assuming the
instruction that caused the exception has not already begun when the interrupt occurs.
To recover from an interrupt, a history buffer is used. This buffer is a FIFO queue that
records the relevant machine state at the time of each instruction issue. When issued,
instructions are placed on the tail of the queue and they percolate to the head of the queue
while they are executing. Instructions remain in the queue until they finish executing and all
preceding instructions have completed to a point where no exception can be generated. In
the core, such a condition is fulfilled by waiting for full completion. In the event of an
exception, the machine state necessary to recover the architectural state is available. As
instructions finish executing, they are released (retired) from the queue and the buffer
storage is reclaimed for new instructions entering the queue.
6-8
MPC801 USER’S MANUAL
MOTOROLA
The PowerPC Core
An exception can be detected at any time during instruction execution and is recorded in the
history buffer when the instruction finishes execution. The exception is not recognized until
the faulting instruction reaches the head of the history queue, but once the exception is
recognized, an interrupt process begins. The queue is reversed and the machine is restored
to its state at the time the instruction is issued. Machine state is restored at a maximum rate
of two floating-point and two fixed-point instructions per clock.
QUEUE
HEAD
RETIRED
INSTRUCTIONS
ISSUED
INSTRUCTIONS
QUEUE
TAIL
HISTORY BUFFER QUEUE
COMPLETED INSTRUCTIONS
WRITEBACK
Figure 6-5. History Buffer Queue
To correctly restore the architectural state, the history buffer must record the value of the
destination prior to instruction execution. The destination of a store instruction, however, is
in memory and it is not practical, from a performance standpoint, to always read memory
before writing it. Therefore, stores issue immediately to store buffers, but do not update
memory until all previous instructions have completed execution without exception (the
store has reached the head of the history buffer).
The history buffer has enough storage to hold six instructions worth of state, but no more
than four fixed-point instructions. The other two instructions can be condition code or branch
instructions. In the event of a long latency instruction, it is possible (if a data dependency
does not occur first) for issued instructions to fill up the history buffer. If so, instruction issue
waits until the long latency operation (blocking retirement) finishes.
6
The following types of instructions can potentially cause the history buffer to fill up:
• Floating-point arithmetic instructions
• Integer divide instructions
• Instructions that affect/use resources external to the core
MOTOROLA
MPC801 USER’S MANUAL
6-9
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