MOTOROLA MPC801 User Guide
查询XPC801ZP25供应商
PowerPC
™
MPC801
Integrated Microprocessor
for Embedded Systems
User’s Manual
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is a registered trademark of Motorola, Inc. PowerPC
™
is a registered
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C is a trademark
TABLE OF CONTENTS
Paragraph Page
Number Title Number
Section 1
Introduction
1.1 Features ...............................................................................................1-1
1.2 MPC801 Architecture ...........................................................................1-4
1.2.1 The Embedded PowerPC Core ..................................................1-5
1.2.2 The System Interface Unit ..........................................................1-6
1.2.3 The UART Controller ..................................................................1-6
1.2.4 The I
1.2.5 The Serial Peripheral Interface Controller ..................................1-7
1.3 Power Management .............................................................................1-7
1.4 MPC801 Applications ...........................................................................1-7
1.5 Differences Between the MPC801 and MPC860 .................................1-8
1.6 MPC801 Glueless System Design .......................................................1-8
2
C
Controller ....................................................................... 1-7
Section 2
External Signals
2.1 The System Bus Signals ......................................................................2-2
Section 3
Memory Map
Section 4
Reset
4.1 Types of Reset .....................................................................................4-1
4.1.1 Power-On Reset .........................................................................4-2
4.1.2 External Hard Reset ...................................................................4-2
4.1.3 Internal Hard Reset ....................................................................4-3
4.1.3.1 Loss of Lock ....................................................................4-3
4.1.3.2 Software Watchdog Reset ..............................................4-3
4.1.3.3 Checkstop Reset ............................................................4-3
4.1.3.4 Debug Port Hard Reset ..................................................4-3
4.1.3.5 JTAG Reset ....................................................................4-3
4.1.4 External Soft Reset ....................................................................4-3
4.1.5 Internal Soft Reset ......................................................................4-4
4.1.5.1 Debug Port Soft Reset ....................................................4-4
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4.2 Reset Status Register ..........................................................................4-4
4.3 How to Configure Reset .......................................................................4-6
4.3.1 Hard Reset .................................................................................4-6
4.3.2 Soft Reset ................................................................................4-11
Section 5
Clocks and Power Control
5.1 The Clock Module ................................................................................5-3
5.2 On-Chip Oscillators and External Clock Input ......................................5-6
5.3 The System Phase-Locked Loop .........................................................5-7
5.3.1 Multiplying the Frequency ..........................................................5-7
5.3.2 Eliminating Skew ........................................................................5-7
5.3.3 Operating the PLL Block ............................................................5-8
5.4 The Low-Power Divider ........................................................................5-8
5.5 Internal Clock Signals ..........................................................................5-9
5.5.1 The General System Clocks ......................................................5-9
5.5.2 The Baud Rate Generator Clock ..............................................5-11
5.5.3 The Synchronization Clocks .....................................................5-11
5.6 The Phase-Locked Loop Pins ............................................................5-12
5.7 Controlling The System Clock ............................................................5-13
5.8 PLL Low-Power and Reset Control Register .....................................5-16
5.9 Basic Power Structure ........................................................................5-22
5.10 Keep Alive Power ...............................................................................5-23
5.10.1 Configuration ............................................................................5-23
5.10.2 The Key Mechanism ................................................................5-24
Section 6
The PowerPC Core
6.1 Features ...............................................................................................6-1
6.1.1 Basic Structure of the Core ........................................................6-2
6.1.2 Instruction Flow Within the Core ................................................6-2
6.1.3 Basic Instruction Pipeline ...........................................................6-4
6.2 The Sequencer Unit .............................................................................6-4
6.2.1 Flow Control ...............................................................................6-4
6.2.2 Issuing Instructions ....................................................................6-6
6.2.3 Interrupts ....................................................................................6-6
6.2.4 Precise Exception Model Implementation ..................................6-8
6.2.5 Processing An Interrupt ............................................................6-11
6.2.6 Serialization ..............................................................................6-12
6.2.7 The External Interrupt ..............................................................6-13
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6.2.7.1 Latency .........................................................................6-13
6.2.8 Interrupt Ordering .....................................................................6-13
6.3 The Register Unit ...............................................................................6-15
6.3.1 The Control Registers ..............................................................6-15
6.3.1.1 Physical Location of Special Registers .........................6-19
6.3.1.2 Bit Assignment of the Control Registers .......................6-20
6.3.1.3 Initializing the Control Registers ...................................6-24
6.4 The Fixed-Point Unit ...........................................................................6-24
6.4.1 Updating XER with Divide Instructions .....................................6-24
6.5 The Load/Store Unit ...........................................................................6-25
6.5.1 Load/Store Instruction ..............................................................6-26
6.5.2 Synchronizing Load/Store Instructions .....................................6-27
6.5.3 Instructions Issued to the Data Cache .....................................6-27
6.5.4 Issuing Store Instruction ...........................................................6-27
6.5.5 Nonspeculative Load Instructions ............................................6-28
6.5.6 Executing Unaligned Instructions .............................................6-28
6.5.7 Little-Endian Mode Support ......................................................6-29
6.5.8 Atomic Update Primitives .........................................................6-29
6.5.9 Instruction Timing .....................................................................6-29
6.5.10 Stalling Storage Control Instructions ........................................6-30
6.5.11 Accessing Off-Core Special Registers .....................................6-30
6.5.12 Storage Control Instructions .....................................................6-30
6.5.13 Exception Processing ...............................................................6-31
6.5.13.1 Using DAR, DSISR, and BAR .......................................6-31
Section 7
PowerPC Architecture Compliance
7.1 PowerPC User Instruction Set Architecture (Book I) ............................7-1
7.1.1 Computation Modes ...................................................................7-1
7.1.2 Reserved Fields .........................................................................7-1
7.1.3 Classes of Instructions ...............................................................7-1
7.1.4 Exceptions ..................................................................................7-2
7.1.5 The Branch Processor ................................................................7-2
7.1.6 Fetching Instructions ..................................................................7-2
7.1.7 Branch Instructions .....................................................................7-2
7.1.7.1 Invalid Branch Instruction Forms ....................................7-2
7.1.7.2 Branch Prediction ...........................................................7-2
7.1.8 The Fixed-Point Processor .........................................................7-2
7.1.8.1 Move To/From System Register Instructions ..................7-3
7.1.8.2 Fixed-Point Arithmetic Instructions .................................7-3
7.1.9 The Load/Store Processor .........................................................7-3
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7.1.9.1 Fixed-Point Load and Store With Update Instructions ....7-3
7.1.9.2 Fixed-Point Load and Store Multiple Instructions ...........7-3
7.1.9.3 Fixed-Point Load String Instructions ...............................7-3
7.1.9.4 Storage Synchronization Instructions .............................7-3
7.1.9.5 Optional Instructions .......................................................7-3
7.1.9.6 Little-Endian Byte Ordering ............................................7-4
7.2 PowerPC Virtual Environment Architecture (Book II) ...........................7-4
7.2.1 Storage Model ............................................................................7-4
7.2.1.1 Memory Coherence ........................................................7-4
7.2.1.2 Atomic Update Primitives ...............................................7-4
7.2.2 The Effect of Operand Placement on Performance ...................7-4
7.2.3 The Storage Control Instructions ...............................................7-5
7.2.3.1 Instruction Cache Block Invalidate (icbi) .........................7-5
7.2.3.2 Instruction Synchronize (isync) .......................................7-5
7.2.3.3 Data Cache Block Touch (dcbt) ......................................7-5
7.2.3.4 Data Cache Block Touch for Store (dcbtst) ....................7-5
7.2.3.5 Data Cache Block Set to Zero (dcbz) .............................7-5
7.2.3.6 Data Cache Block Store (dcbst) .....................................7-5
7.2.3.7 Data Cache Block Invalidate (dcbi) ................................7-5
7.2.3.8 Data Cache Block Flush (dcbf) .......................................7-5
7.2.3.9 Enforce In-Order Execution of I/O (eieio) .......................7-6
7.2.4 Timebase ...................................................................................7-6
7.3 PowerPC Operating Environment Architecture (Book III) ....................7-6
7.3.1 The Branch Processor ...............................................................7-6
7.3.1.1 Branch Processor Registers ...........................................7-6
7.3.1.2 Branch Processor Instructions ........................................7-6
7.3.2 The Fixed-Point Processor .........................................................7-6
7.3.2.1 Special-Purpose Registers .............................................7-6
7.3.3 Storage Model ............................................................................7-7
7.3.3.1 Address Translation ........................................................7-7
7.3.4 Reference and Change Bits .......................................................7-7
7.3.5 Storage Protection .....................................................................7-7
7.3.6 Storage Control Instructions .......................................................7-7
7.3.6.1 Data Cache Block Invalidate (dcbi) ................................7-7
7.3.6.2 TLB Invalidate Entry (tlbie) .............................................7-7
7.3.6.3 TLB Invalidate All (tlbia) ..................................................7-8
7.3.6.4 TLB Synchronize (tlbsync) ..............................................7-8
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7.3.7 Interrupts ....................................................................................7-8
7.3.7.1 Classes ...........................................................................7-8
7.3.7.2 Processing ......................................................................7-8
7.3.7.3 Definitions .......................................................................7-8
7.3.7.4 Partially Executed Instructions ......................................7-17
7.3.8 Timer Facilities .........................................................................7-17
7.3.9 Optional Facilities and Instructions ...........................................7-17
Section 8
Instruction Execution Timing
8.1 Instruction Execution Timing Examples ...............................................8-4
8.1.1 Data Cache Load .......................................................................8-4
8.1.2 Writeback ...................................................................................8-5
8.1.2.1 Writeback Arbitration ......................................................8-5
8.1.2.2 Private Writeback Bus Dedicated for Load .....................8-6
8.1.3 Fastest External Load (Data Cache Miss) ..................................8-7
8.1.4 A Full History Buffer ...................................................................8-8
8.1.5 Branch Folding ...........................................................................8-9
8.1.6 Branch Prediction .....................................................................8-10
Section 9
Instruction Cache
9.1 Features ...............................................................................................9-1
9.2 Programming the Instruction Cache .....................................................9-4
9.2.1 Instruction Cache Control and Status Register ..........................9-4
9.2.2 Instruction Cache Address Register ...........................................9-5
9.2.3 Instruction Cache Data Port Register .........................................9-6
9.3 How the Instruction Cache Works ........................................................9-6
9.3.1 Instruction Cache Hit ..................................................................9-6
9.3.2 Instruction Cache Miss ...............................................................9-6
9.3.3 Instruction Fetch On A Predicted Path .......................................9-7
9.4 Instruction Cache Commands ..............................................................9-7
9.4.1 Instruction Cache Block Invalidate .............................................9-8
9.4.2 Invalidate All Instruction Cache ..................................................9-8
9.4.3 Load & Lock ...............................................................................9-8
9.4.4 Unlock Line .................................................................................9-9
9.4.5 Unlock All ...................................................................................9-9
9.4.6 Instruction Cache Inhibit .............................................................9-9
9.4.7 Instruction Cache Read ............................................................9-10
9.4.8 Instruction Cache Write ............................................................9-11
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9.5 Restrictions ........................................................................................9-11
9.6 Instruction Cache Coherency .............................................................9-11
9.7 Updating Code And Memory Region Attributes .................................9-11
9.8 Reset Sequence .................................................................................9-12
9.9 Debug Support ...................................................................................9-12
9.9.1 Fetching Instructions From the Development Port ...................9-12
Section 10
Data Cache
10.1 Features .............................................................................................10-1
10.2 Organization of the Data Cache .........................................................10-2
10.3 Programming the Data Cache ............................................................10-3
10.3.1 PowerPC Architecture Instructions ..........................................10-3
10.3.1.1 PowerPC User Instruction Set Architecture ..................10-3
10.3.1.2 PowerPC Virtual Environment Architecture ..................10-3
10.3.1.3 PowerPC Operating Environment Architecture ............10-3
10.3.2 Implementation Specific Operations ........................................10-3
10.3.3 Special Registers of the Data Cache .......................................10-3
10.3.3.1 Data Cache Control and Status Register .....................10-4
10.3.3.2 Data Cache Address Register ......................................10-6
10.3.3.3 Reading the Cache Structures .....................................10-6
10.3.3.4 Data Cache Data Register ............................................10-7
10.4 Operating the Data Cache .................................................................10-7
10.4.1 Data Cache Read .....................................................................10-7
10.4.2 Data Cache Write .....................................................................10-8
10.4.2.1 Copyback Mode ............................................................10-8
10.4.2.2 Writethrough Mode .......................................................10-9
10.4.3 Data Cache-Inhibited Accesses ...............................................10-9
10.4.4 Data Cache Freeze ..................................................................10-9
10.4.5 Data Cache Coherency ..........................................................10-10
10.5 Controlling the Data Cache ..............................................................10-10
10.5.1 Flushing and Invalidating .......................................................10-10
10.5.2 Disabling ................................................................................10-10
10.5.3 Locking ...................................................................................10-10
10.5.4 Storage Control Instructions in the Data Cache .....................10-11
10.5.4.1 dcbi, dcbst, dcbf And dcbz Instructions ......................10-11
10.5.4.2 Touch ..........................................................................10-11
10.5.4.3 Storage Synchronization and Reservation .................10-11
10.5.5 Reading the Data Cache Structures ......................................10-11
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Section 11
Memory Management Unit
11.1 Features .............................................................................................11-1
11.2 Address Translation ...........................................................................11-2
11.2.1 Translation Lookaside Buffer Operation ...................................11-2
11.3 Protection ...........................................................................................11-3
11.4 Storage Attributes ...............................................................................11-4
11.4.1 Reference and Change Bit Updates .........................................11-4
11.4.2 Storage Control ........................................................................11-4
11.5 Translation Table Structure ................................................................11-4
11.5.1 Level One Descriptor ................................................................11-8
11.5.2 Level Two Descriptor ................................................................11-9
11.6 Memory Management Unit Programming Model ..............................11-10
11.6.1 Configuration Registers ..........................................................11-10
11.6.1.1 Instruction MMU Control Register ...............................11-10
11.6.1.2 MI_AP Register ...........................................................11-11
11.6.1.3 Data MMU Control Register ........................................11-12
11.6.1.4 MD_AP Register .........................................................11-13
11.6.1.5 CASID Register ..........................................................11-14
11.6.2 Tablewalk Registers ...............................................................11-14
11.6.2.1 M_TWB Register ........................................................11-14
11.6.2.2 M_TW Register ...........................................................11-15
11.6.2.3 MI_EPN Register ........................................................11-15
11.6.2.4 MI_TWC Register .......................................................11-16
11.6.2.5 MI_RPN Register ........................................................11-17
11.6.2.6 MD_EPN Register ......................................................11-18
11.6.2.7 Data MMU Tablewalk Control Register ......................11-19
11.6.2.8 MD_RPN Register ......................................................11-20
11.6.3 Instruction Debug Registers ...................................................11-22
11.6.3.1 MI_DCAM Register .....................................................11-22
11.6.3.2 MI_DRAM0 Register ...................................................11-23
11.6.3.3 MI_DRAM1 Register ...................................................11-24
11.6.4 Data Debug Registers ............................................................11-25
11.6.4.1 MD_DCAM Register ...................................................11-25
11.6.4.2 MD_DRAM0 Register .................................................11-26
11.6.4.3 MD_DRAM1 Register .................................................11-27
11.7 Interrupts ..........................................................................................11-29
11.7.1 Implementation Specific Instruction TLB Miss ........................11-29
11.7.2 Implementation Specific Data TLB Miss .................................11-29
11.7.3 Implementation Specific Instruction TLB Error .......................11-29
11.7.4 Implementation Specific Data TLB Error ................................11-29
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11.8 Manipulating the TLB .......................................................................11-30
11.8.1 Reloading the TLB .................................................................11-30
11.8.1.1 Translation Reload Examples .....................................11-31
11.8.2 Controlling the TLB Replacement Counter ............................11-32
11.8.3 Invalidating the TLB ...............................................................11-32
11.8.4 Loading the Reserved TLB Entries ........................................11-32
11.9 Requirements For Accessing The Memory Management
Unit Control Registers ......................................................................11-32
Section 12
System Interface Unit
12.1 Features .............................................................................................12-2
12.2 System Configuration and Protection .................................................12-2
12.3 Configuring the System ......................................................................12-4
12.3.1 Configuring the Interrupt ..........................................................12-4
12.3.2 Priority of the Interrupt Sources ...............................................12-5
12.3.2.1 Programming the Interrupt Controller ...........................12-6
12.3.2.2 SIU Interrupt Mask Register .........................................12-7
12.3.2.3 SIU Interrupt Edge Level Mask Register ......................12-8
12.3.2.4 SIU Interrupt Vector Register .......................................12-9
12.4 The Bus Monitor ...............................................................................12-10
12.5 The PowerPC Decrementer .............................................................12-10
12.6 The PowerPC Timebase ..................................................................12-11
12.7 The Real-Time Clock .......................................................................12-11
12.8 The Periodic Interrupt Timer ............................................................12-12
12.9 The Software Watchdog Timer ........................................................12-13
12.10 Freeze Operation .............................................................................12-15
12.10.1 Low-Power Stop Operation ....................................................12-15
12.11 Multiplexing the System Interface Unit Pins .....................................12-16
12.12 Programming the System Interface Unit ..........................................12-17
12.12.1 System Configuration and Protection Registers ....................12-17
12.12.1.1 SIU Module Configuration Register ............................12-17
12.12.1.2 Internal Memory Map Register ...................................12-20
12.12.1.3 System Protection Control Register ...........................12-21
12.12.1.4 Software Service Register ..........................................12-22
12.12.1.5 Transfer Error Status Register ....................................12-22
12.12.2 System Timer Registers .........................................................12-23
12.12.2.1 Decrementer Register ................................................12-23
12.12.2.2 Timebase Register .....................................................12-24
12.12.2.3 Timebase Reference Register ....................................12-24
12.12.2.4 Timebase Control and Status Register .......................12-25
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12.12.2.5 Real-Time Clock Status and Control Register ............12-26
12.12.2.6 Real-Time Clock Register ...........................................12-27
12.12.2.7 Real-Time Clock Alarm Register ................................12-27
12.12.2.8 Periodic Interupt Status and Control Register ............12-27
12.12.2.9 Periodic Interrupt Timer Count Register .....................12-28
12.12.2.10 Periodic Interrupt Timer Register ................................12-29
Section 13
External Bus Interface
13.1 Features .............................................................................................13-1
13.2 Transfer Signals .................................................................................13-2
13.2.1 Control Signals .........................................................................13-3
13.3 Signal Descriptions .............................................................................13-4
13.4 Operations on the Bus ........................................................................13-8
13.4.1 Basic Transfer Protocol ............................................................13-8
13.4.2 Single Beat Transfers ...............................................................13-8
13.4.2.1 Single Beat Read Flow .................................................13-9
13.4.2.2 Single Beat Write Flow ...............................................13-12
13.4.3 Burst Transfers .......................................................................13-16
13.4.4 The Burst Mechanism ............................................................13-16
13.4.5 Transfer Alignment and Packaging ........................................13-25
13.4.6 Arbitration Phase Signals .......................................................13-27
13.4.6.1 Bus Request ...............................................................13-28
13.4.6.2 Bus Grant ....................................................................13-28
13.4.6.3 Bus Busy .....................................................................13-29
13.4.7 Address Transfer Phase-Related Signals ..............................13-32
13.4.7.1 Transfer Start ..............................................................13-32
13.4.7.2 Address Bus ...............................................................13-32
13.4.7.3 Transfer Attributes ......................................................13-32
13.4.8 Termination Signals ................................................................13-35
13.4.8.1 Transfer Acknowledge ................................................13-35
13.4.8.2 Burst Inhibit .................................................................13-35
13.4.8.3 Transfer Error Acknowledge .......................................13-35
13.4.8.4 Protocol for Termination Signals .................................13-35
13.4.9 Storage Reservation Protocol ................................................13-37
13.4.10 Exception Control Cycles .......................................................13-40
13.4.10.1 RETRY ........................................................................13-40
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Section 14
Endian Modes
14.1 Little-Endian System Features ...........................................................14-2
14.2 Big-Endian System Features .............................................................14-4
14.3 PowerPC Little-Endian System Features ...........................................14-4
14.4 Setting the Endian Mode Of Operation ..............................................14-5
Section 15
Memory Controller
15.1 Features .............................................................................................15-1
15.2 Basic Architecture ..............................................................................15-3
15.2.1 Registers Associated with the Memory Controller ...................15-6
15.2.1.1 8-, 16-, and 32-Bit Port Size Configuration ...................15-7
15.2.1.2 Write-Protect Configuration ..........................................15-7
15.2.1.3 Address and Address Space Checking ........................15-7
15.2.1.4 Parity Generation and Checking ...................................15-7
15.2.1.5 Transfer Error Acknowledge Generation ......................15-7
15.2.2 The General-Purpose Chip-Select Machine ............................15-7
15.2.2.1 Programmable Wait State configuration .....................15-13
15.2.2.2 Extended Hold Time on Read Accesses ....................15-13
15.2.2.3 Global Chip-Select Operation .....................................15-15
15.2.2.4 SRAM interface ..........................................................15-16
15.2.2.5 GPCM External Asynchronous Master Support .........15-17
15.2.3 User-Programmable Machines ..............................................15-19
15.2.3.1 RAM Word Structure and Timing Specification ..........15-25
15.2.3.2 CS Signals ..................................................................15-28
15.2.3.3 Byte Select Signals .....................................................15-29
15.2.3.4 General-Purpose Signals ...........................................15-30
15.2.3.5 Loop Control Signal ....................................................15-31
15.2.3.6 Exception Handling .....................................................15-31
15.2.3.7 Address Control Signals .............................................15-32
15.2.3.8 The Disable Timer Mechanism ...................................15-35
15.2.3.9 Transfer Acknowledge And Data Sample Control ......15-36
15.2.3.10 The WAIT Mechanism ................................................15-36
15.2.3.11 Location of UPM Start Addresses ..............................15-39
15.2.3.12 Example DRAM Interface ...........................................15-39
15.2.3.13 Extended Data-Out Interface Example .......................15-52
15.3 External Master Support ..................................................................15-59
15.4 Programming the Memory Controller ...............................................15-68
15.4.1 Memory Status Register .........................................................15-68
15.4.2 Memory Periodic Timer Prescaler Register ...........................15-69
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15.4.3 Base Register .........................................................................15-70
15.4.4 Option Register ......................................................................15-72
15.4.5 Machine A Mode Register ......................................................15-75
15.4.6 Machine B Mode Register ......................................................15-78
15.4.7 Memory Command Register ..................................................15-82
15.4.8 Memory Data Register ...........................................................15-84
15.4.9 Memory Address Register ......................................................15-84
Section 16
Serial Communication Modules
16.1 The UART Controllers ........................................................................16-1
16.2 Features .............................................................................................16-2
16.3 Serial Interface Signals ......................................................................16-2
16.3.1 Sub-Block Description ..............................................................16-3
16.3.1.1 The Transmitter ............................................................16-3
16.3.1.2 The Receiver ................................................................16-5
16.3.1.3 The Baud Rate Generator ............................................16-8
16.3.1.4 The Global Controller Interface .....................................16-8
16.4 The Serial Controller ........................................................................16-15
16.4.1 Programming the Serial Controller .........................................16-15
16.4.1.1 Serial Controller Command Register ..........................16-15
16.4.2 The Serial Peripheral Interface ...............................................16-15
16.4.2.1 Features ......................................................................16-16
16.4.2.2 Clocking and Pin Functions ........................................16-17
16.4.2.3 SPI Transmission and Reception Process .................16-18
16.4.2.4 Programming the Serial Peripheral Interface ..............16-20
16.4.3 The I
16.4.3.1 Features ......................................................................16-27
16.4.3.2 Clocking and Pin Functions ........................................16-28
16.4.3.3 I
16.4.3.4 Programming the I
16.5 The Parallel I/O Port .........................................................................16-35
16.5.1 Features .................................................................................16-35
16.5.2 Port B Pin Functions ...............................................................16-35
16.5.3 The Port B Registers ..............................................................16-37
16.5.3.1 Port B Open-Drain Register ........................................16-37
16.5.3.2 Port B Data Register ...................................................16-37
16.5.3.3 Port B Data Direction Register ....................................16-38
16.5.3.4 Port B Pin Assignment Register .................................16-38
2
C Controller ...................................................................16-26
2
C Controller Transmission and Reception Process...16-28
2
C Controller ..................................16-30
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TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
Section 17
Data Alignment
Section 18
Development Support
18.1 Program Flow Tracking ......................................................................18-1
18.1.1 Basic Operation ........................................................................18-2
18.1.1.1 The Internal Hardware ..................................................18-2
18.1.1.2 Special Case of Queue Flush Information ....................18-4
18.1.1.3 Program Trace In Debug Mode ....................................18-5
18.1.1.4 Sequential Instructions Marked As Indirect Branch ......18-5
18.1.1.5 The External Hardware .................................................18-5
18.1.1.6 Benefits of Compression ..............................................18-7
18.1.2 Controlling the Instruction Fetch Show Cycle ..........................18-8
18.2 Watchpoint And Breakpoint Generation .............................................18-8
18.2.1 Internal Watchpoints and Breakpoints .....................................18-9
18.2.1.1 Features .....................................................................18-11
18.2.1.2 Restrictions .................................................................18-12
18.2.1.3 Byte And Half-Word Working Modes ..........................18-12
18.2.1.4 Context Dependent Filter ............................................18-14
18.2.1.5 Ignore First Match Option ...........................................18-14
18.2.1.6 Generating Compare Types .......................................18-15
18.2.2 Basic Watchpoint/Breakpoint Operation ................................18-16
18.2.2.1 Instruction Support .....................................................18-16
18.2.2.2 Load/Store Support ....................................................18-17
18.2.2.3 Counter Support .........................................................18-18
18.2.2.4 Trap Enable Programming .........................................18-20
18.3 Development System Interface ........................................................18-20
18.3.1 Trap Enable Mode ..................................................................18-22
18.3.2 Debug Mode ...........................................................................18-22
18.3.2.1 Debug Mode Enable vs. Debug Mode Disable ...........18-24
18.3.2.2 Entering Debug Mode .................................................18-24
18.3.2.3 CheckStop State And Debug Mode ............................18-27
18.3.2.4 Saving the Machine State in Debug Mode .................18-27
18.3.2.5 Running in Debug Mode .............................................18-28
18.3.2.6 Exiting Debug Mode ...................................................18-28
18.3.3 The Development Port ...........................................................18-28
18.3.3.1 The Development Port Pins ........................................18-29
18.3.3.2 Development Port Registers .......................................18-30
18.3.3.3 Development Port Serial Communications .................18-31
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Paragraph Page
Number Title Number
18.4 The Software Monitor Debugger ......................................................18-40
18.4.1 Freeze Indication ....................................................................18-41
18.5 Programming the Development Support Registers ..........................18-41
18.5.1 Protecting the Development Port Registers ...........................18-41
18.5.2 Development Port Registers ..................................................18-42
18.5.2.1 Comparator A–D Value Register ................................18-42
18.5.2.2 Comparator E–F Value Register .................................18-42
18.5.2.3 Comparator G–H Value Register ................................18-42
18.5.2.4 Breakpoint Address Register ......................................18-42
18.5.2.5 Instruction Support Control Register ...........................18-43
18.5.2.6 Load/Store Support Comparators Control Register ....18-46
18.5.2.7 Load/Store Support AND–OR Control Register ..........18-48
18.5.2.8 Breakpoint Counter A Value and Control Register .....18-50
18.5.2.9 Breakpoint Counter B Value and Control Register .....18-51
18.5.3 Debug Mode Registers ...........................................................18-51
18.5.3.1 Interrupt Cause Register .............................................18-51
18.5.3.2 Debug Enable Register ...............................................18-53
18.5.4 Development Port Data Register ............................................18-55
Section 19
IEEE 1149.1 Test Access Port
19.1 The TAP Controller .............................................................................19-3
19.2 The Boundary Scan Register .............................................................19-4
19.3 The Instruction Register ...................................................................19-17
19.3.1 The External Test Instruction .................................................19-18
19.3.2 The sample/preload Instruction ..............................................19-18
19.3.3 The bypass Instruction ...........................................................19-18
19.3.4 The clamp Instruction .............................................................19-19
19.3.5 The hi-z Instruction .................................................................19-19
19.4 MPC801 Restrictions ........................................................................19-19
19.5 Nonscan Chain Operation ................................................................19-19
19.6 Motorola MPC801 BSDL Description ...............................................19-19
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TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
Section 20
Electrical Characteristics
20.1 Maximum Ratings (GND = 0V) ..........................................................20-1
20.2 Thermal Characteristics .....................................................................20-2
20.3 Power Considerations ........................................................................20-2
20.3.1 Layout Practices .......................................................................20-3
20.4 DC Electrical Specifications (V
20.5 MPC801 AC Electrical Specifications Control Timing ........................20-5
20.6 IEEE 1149.1 Electrical Specifications ..............................................20-26
Section 21
Communication Electrical Characteristics
= 3.0 – 3.6V) .................................20-4
CC
21.1 PIO AC Electrical Specifications ........................................................21-1
21.2 UART BRG Clock AC Electrical Specifications ..................................21-2
21.3 UART—External Clock AC Electrical Specifications ..........................21-3
21.4 UART—Internal Clock AC Electrical Specifications ...........................21-3
21.5 SPI Master AC Electrical Specifications .............................................21-5
21.6 SPI Slave AC Electrical Specifications ...............................................21-6
2
21.7 I
21.8 I
C AC Electrical Specifications–SCL < 100kHz ................................21-8
2
C AC Electrical Specifications–SCL > 100kHz ................................21-8
Section 22
Mechanical Specifications
22.1 Ordering Information ..........................................................................22-1
22.2 Pin Assignments – PBGA-Top View ..................................................22-2
22.3 Package Dimensions–Plastic Ball Grid Array (PBGA) .......................22-3
Section 23
Terminology
Appendix A
Quick Reference Guide to MPC801 Registers
A.1 Core Control Registers .........................................................................A-1
A.2 Internally Mapped Registers ................................................................A-4
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TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
AppendixB
Applications
B.1 MPC801 Basic Initialization ................................................................. B-1
B.1.1 Programming the UPM .............................................................. B-2
B.1.2 MPC801 MMU/Cache Example ................................................ B-5
B.1.2.1 Basic MMU and Cache Concept .................................... B-5
B.1.2.2 General Concept ............................................................ B-5
B.1.3 Memory Management Unit ........................................................ B-6
B.1.3.1 Memory Protection ....................................................... B-10
B.1.3.2 MMU Example ............................................................. B-10
B.1.4 M_TWB MMU TABLEWALK BASE REGISTER ..................... B-12
B.1.5 MI_CTR Instruction MMU Control Register ............................. B-12
B.1.6 Mx_AP Instruction/Data Access Protection Register .............. B-13
B.1.7 MD_CTR Data MMU Control Register .................................... B-14
B.1.8 Level One Descriptor Format Register .................................... B-15
B.1.9 Level Two Descriptor 1K Resolution Format Register ............ B-18
B.1.10 Level Two Descriptor 4K Resolution Format Register ............ B-20
B.2 Configuring the MPC801 Memory Controller .................................... B-26
B.2.1 General Configuration ............................................................. B-27
B.2.2 SRAM Configuration ................................................................ B-27
B.2.3 EPROM Configuration ............................................................. B-31
B.2.4 DRAM Configuration ............................................................... B-34
B.3 Porting to the PowerQUICC .............................................................. B-43
B.4 Using the PowerPC Core .................................................................. B-44
B.5 Bit Labeling ........................................................................................ B-44
B.5.1 Code Portability ....................................................................... B-44
B.6 Cache ................................................................................................ B-44
B.6.1 Cache Performance Impact ..................................................... B-44
B.6.2 Data Coherency ...................................................................... B-45
B.6.3 Debugging ............................................................................... B-45
B.7 Memory Management Unit ................................................................ B-45
B.8 Real-Time Operating Systems .......................................................... B-45
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xx
LIST OF ILLUSTRATIONS
Figure Page
Number Title Number
1-1. MPC801 Block Diagram ........................................................................1-4
1-2. MPC801 System Configuration .............................................................1-8
2-1. MPC801 External Signals .....................................................................2-1
4-1. Reset Configuration Basic Scheme .......................................................4-6
4-2. Reset Configuration Sampling Scheme For Short PORESET
Assertion ...............................................................................................4-7
4-3. Reset Configuration Sampling Scheme For Long PORESET
Assertion ...............................................................................................4-7
4-4. Reset Configuration Sampling Timing Requirements ...........................4-8
5-1. Clock Unit Block Diagram ......................................................................5-2
5-2. MPC801 Power Supply .........................................................................5-3
5-3. MPC801 Clocks Timing Diagram ..........................................................5-4
5-4. System PLL Block Diagram ...................................................................5-7
5-5. General System Clocks Select ..............................................................5-9
5-6. Divided System Clocks Timing Diagram .............................................5-10
5-7. MPC801 Clocks For DFNH = 1 or DFNL = 0 Timing Diagram ............5-11
5-8. MPC801 Low-Power Modes Flowchart ...............................................5-19
5-9. MPC801 Basic Power Supply Configuration .......................................5-22
5-10. External Power Supply Scheme (2.0 V Internal Voltage) ....................5-23
5-11. Key Mechanism Diagram ....................................................................5-24
6-1. Core Block Diagram ..............................................................................6-3
6-2. Instruction Flow Conceptual Diagram ...................................................6-3
6-3. Basic Instruction Pipeline Timing Diagram ............................................6-4
6-4. Sequencer Data Path ............................................................................6-5
6-5. History Buffer Queue .............................................................................6-9
6-6. Load/Store Unit Functional Block Diagram .........................................6-26
6-7. Number of Bus Cycles Needed For Unaligned, Single Register
Fixed-Point Load/Store Instructions ....................................................6-28
6-8. Number of Bus Cycles Needed For String Instruction Execution .......6-30
MPC801 USER’S MANUAL
MOTOROLA
LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
8-1. Example of a Data Cache Load ............................................................8-4
8-2. Example of a Writeback Arbitration .......................................................8-5
8-3. Another Example of a Writeback Arbitration .........................................8-5
8-4. Example of a Private Writeback Bus Load ............................................8-6
8-5. Example of an External Load ................................................................8-7
8-6. Example of a Full History Buffer ............................................................8-8
8-7. Example of Branch Folding ...................................................................8-9
8-8. Example of Branch Prediction .............................................................8-10
9-1. Instruction Cache Organization .............................................................9-2
9-2. Cache Data Path Block Diagram ...........................................................9-3
10-1. Data Cache Organization ....................................................................10-2
11-1. Effective to Real Address Translation For 4K Pages ..........................11-3
11-2. Two Level Translation Table When MD_CTR(TWAM) = 1 .................11-5
11-3. Two Level Translation Table When MD_CTR(TWAM) = 0 .................11-6
12-1. System Configuration and Protection Logic ........................................12-3
12-2. MPC801 Interrupt Structure ................................................................12-4
12-3. Interrupt Table Handling Example .......................................................12-9
12-4. RTC Block Diagram ...........................................................................12-12
12-5. Periodic Interrupt Timer Block Diagram ............................................12-12
12-6. Software Watchdog Timer Service State Diagram ............................12-14
12-7. Software Watchdog Timer Block Diagram ........................................12-15
13-1. Input Sample Window .........................................................................13-2
13-2. MPC801 Bus Signals ..........................................................................13-3
13-3. Basic Transfer Protocol .......................................................................13-8
13-4. Simplified Diagram of a Single Beat Read Cycle ................................13-9
13-5. Single Beat Read Cycle–Basic Timing–Zero Wait States .................13-10
13-6. Single Beat Read Cycle–Basic Timing–One Wait State ...................13-11
13-7. Simplified Flow Diagram of a Single Beat Write Cycle ......................13-12
13-8. Single Beat Write Cycle–Basic Timing–Zero Wait States .................13-13
13-9. Single Beat Write Cycle–Basic Timing–One Wait State ....................13-14
13-10. Single Beat–32-Bit Data–Write Cycle–16-Bit Port Size Basic
Timing ................................................................................................13-15
13-11. Simplified Flow Diagram Of A Burst Read Cycle ..............................13-17
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LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
13-12. Burst-Read Cycle–32-Bit Port Size–Zero Wait State ........................13-18
13-13. Burst-Read Cycle–32-Bit Port Size–One Wait State .........................13-19
13-14. Burst-Read Cycle–32-Bit Port Size–Wait States Between Beats .....13-20
13-15. Burst-Read Cycle–16-Bit Port Size–One Wait State Between
Beats ................................................................................................. 13-21
13-16. Simplified Flow Diagram of a Burst Write Cycle ................................13-22
13-17. Burst Write Cycle–32-Bit Port Size–Zero Wait States .......................13-23
13-18. Burst-Inhibit Cycle–32-Bit Port Size ..................................................13-24
13-19. Internal Operand Representation ......................................................13-25
13-20. Interface To Different Port Size Devices ...........................................13-26
13-21. Bus Arbitration Flowchart ..................................................................13-28
13-22. Basic Connection of the Master Signal .............................................13-29
13-23. Bus Arbitration Timing Diagram ........................................................13-30
13-24. Internal Bus Arbitration State Machine ..............................................13-31
13-25. Termination Signals Protocol Basic Connection ...............................13-36
13-26. Termination Signals Protocol Timing Diagram ..................................13-37
13-27. Reservation On A Local Bus .............................................................13-38
13-28. Reservation On Multilevel Bus Hierarchy ..........................................13-39
13-29. Retry Transfer Timing–Internal Arbiter ..............................................13-41
13-30. Retry Transfer Timing–External Arbiter .............................................13-42
13-31. Retry On Burst Cycle ........................................................................13-43
14-1. General MPC801 System Diagram .....................................................14-2
15-1. Memory Controller Block Diagram ......................................................15-2
15-2. MPC801 Simple System Configuration ...............................................15-4
15-3. Memory Controller Machine Selection ................................................15-5
15-4. Memory Controller Basic Operation ....................................................15-6
15-5. MPC801 GPCM–Memory Devices Interface .......................................15-8
15-6. MPC801 GPCM–Memory Device Basic Timing
(ACS = 00,TRLX = 0) ..........................................................................15-9
15-7. MPC801 GPCM–Peripheral Device Interface .....................................15-9
15-8. MPC801 GPCM–Peripheral Device Basic Timing
(ACS = 10, ACS = 11,TRLX = 0) ......................................................15-10
15-9. MPC801 GPCM–Relaxed Timing–Read Access
(ACS = 10, ACS = 11, SCY = 1, TRLX =1) .......................................15-11
15-10. MPC801 GPCM–Relaxed Timing–Write Access
(ACS = 10, ACS = 11, SCY = 0, CSNT = 0, TRLX =1) .....................15-11
15-11. MPC801 GPCM–Relaxed Timing–Write Access
(ACS = 10, ACS = 11, SCY = 0, CSNT = 1, TRLX =1) .....................15-12
xxii
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MOTOROLA
LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
15-12. MPC801 GPCM–Relaxed Timing–Write Access
(ACS = 00, SCY = 0, CSNT = 1, TRLX =1 ........................................15-12
15-13. MPC801 Consecutive Accesses Write
After Read–(ORx-EHTR = 0) ............................................................15-13
15-14. MPC801 Consecutive Accesses Write
After Read–(ORx-EHTR = 1) ............................................................15-14
15-15. MPC801 Consecutive Accesses Read After Read From
Different Banks–(ORx-EHTR = 1) .....................................................15-14
15-16. MPC801 Consecutive Accesses Read After Read From
Same Bank– (ORx-EHTR = 1) ..........................................................15-15
15-17. MPC801–Simple 128K SRAM Configuration ....................................15-16
15-18. MPC801–Asynchronous External Master Configuration For
GPCM–Handled Memory Devices ....................................................15-17
15-19. Asynchronous Master GPCM–Memory Devices
Basic Timing (TRLX = 0) ...................................................................15-18
15-20. General Description of a UPM ...........................................................15-19
15-21. Memory Periodic Timer Request Block Diagram ..............................15-20
15-22. Memory Controller UPM Clock Scheme
(For System_To CLKOUT Division Factor 1–EBDF = 00) ................15-21
15-23. Memory Controller UPM Clock Scheme
(For System_To CLKOUT Division Factor 2–EBDF = 01) ................15-21
15-24. UPM Signals Timing Example
(For System_To CLKOUT Division Factor 1–EBDF = 00) ................15-22
15-25. UPM Signals Timing Example
(For System_To CLKOUT Division Factor 2–EBDF = 01) ................15-23
15-26. UPM External Signal Generation ......................................................15-24
15-27. RAM Word Structure .........................................................................15-25
15-28. CS Signal Control Model ...................................................................15-28
15-29. Byte Select Control Model .................................................................15-29
15-30. UPM Data Handling In Read Accesses .............................................15-36
15-31. UPM Wait Mechanism Timing For Internal and External
Synchronous Masters 1........................................................................5-38
15-32. UPM Wait Mechanism Timing For An External Asynchronous
Master ...............................................................................................15-39
15-33. MPC801–DRAM Interface Connection ..............................................15-40
15-34. Address Start Pointers of the UPM RAM Array .................................15-41
15-35. Single Beat Read Access To Page Mode DRAM ..............................15-43
15-36. Single Beat Write Access To Page Mode DRAM ..............................15-44
15-37. Burst Read Access To Page Mode DRAM (No LOOP) .....................15-45
15-38. Burst Read Access To Page Mode DRAM (LOOP) ..........................15-46
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LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
15-39. Burst Write Access To Page Mode DRAM (No LOOP) .....................15-47
15-40. Refresh Cycle (CBR) To Page Mode DRAM ....................................15-48
15-41. Exception Cycle ................................................................................15-49
15-42. Page Mode DRAM Burst Read Access
(Data Sampling on Falling Edge of CLKOUT) ...................................15-51
15-43. EDO Interface Connection ................................................................15-52
15-44. Single Beat Read Access To Page Mode DRAM With Extended
Data-Out ............................................................................................15-53
15-45. Single Beat Write Access To Page Mode DRAM With Extended
Data-Out ............................................................................................15-54
15-46. Burst Read Access To Page Mode DRAM With Extended
Data-Out ............................................................................................15-55
15-47. Burst Write Access To Page Mode DRAM With Extended
Data-Out ............................................................................................15-56
15-48. Refresh Cycle (CBR) To Page Mode DRAM With Extended
Data-Out ............................................................................................15-57
15-49. Exception Cycle For Page Mode DRAM With Extended
Data-Out ............................................................................................15-58
15-50. Synchronous External Master Basic Access (GPCM Controlled) .....15-62
15-51. Asynchronous External Master Basic Access (GPCM Controlled) ...15-63
15-52. Synchronous External Master–MPC801–DRAM Device
Typical Configuration ........................................................................15-64
15-53. Synchronous External Master–Burst Read Access To Page
Mode DRAM ......................................................................................15-65
15-54. Asynchronous External Master–MPC801–DRAM Device
Typical Configuration ........................................................................15-66
15-55. Asynchronous External Master–Read Access To Page Mode
DRAM ................................................................................................15-67
15-56. Blank Worksheet for a UPM ..............................................................15-85
16-1. UART Block Diagram ..........................................................................16-1
16-2. SPI Block Diagram ............................................................................16-16
16-3. SPI Transfer Format with CP = 0 ......................................................16-21
16-4. SPI Transfer Format with CP = 1 ......................................................16-22
2
16-5. I
xxiv
C Controller Block Diagram ............................................................16-27
MPC801 USER’S MANUAL
MOTOROLA
LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
18-1. Watchpoints and Breakpoint Support ................................................18-10
18-2. Partially Supported Watchpoints/Breakpoint Example ......................18-14
18-3. Instruction Support General Structure ...............................................18-16
18-4. Load/Store Support General Structure ..............................................18-19
18-5. Relationship Between the Core and Debug Mode ............................18-21
18-6. Debug Mode Logic Implementation ...................................................18-23
18-7. Debug Mode Reset Configuration Timing Diagram ...........................18-25
18-8. Development Port/BDM Connector Pinout Options ..........................18-30
18-9. Asynchronous Clocked Serial Communications Timing Diagram .....18-33
18-10. Synchronous Self-Clocked Serial Communications Timing
Diagram ............................................................................................. 18-34
18-11. Enabling Clock Mode Following Reset Timing Diagram ...................18-35
18-12. Example of Download Procedure Code ............................................18-39
18-13. Slow Download Procedure Loop .......................................................18-40
18-14. Fast Download Procedure Loop ........................................................18-40
19-1. Test Logic Block Diagram ...................................................................19-2
19-2. TAP Controller State Machine .............................................................19-3
19-3. Output Pin Cell (O.Pin) ........................................................................19-4
19-4. Observe-Only Input Pin Cell (I.Obs) ....................................................19-4
19-5. Output Control Cell (IO.CTL) ...............................................................19-5
19-6. General Arrangement of Bidirectional Pin Cells ..................................19-5
19-7. Bypass Register ................................................................................19-18
20-1. External Clock Timing Diagram .........................................................20-10
20-2. Synchronous Output Signals Timing Diagram ..................................20-11
20-3. Synchronous Active Pull-Up And Open-Drain Outputs Signals
Timing Diagram .................................................................................20-12
20-4. Synchronous Input Signals Timing Diagram .....................................20-12
20-5. Input Data In Normal Case Timing Diagram .....................................20-13
20-6. Input Data Timing When Controlled By The UPM In The
Memory Controller .............................................................................20-13
20-7. External Bus Read Timing Diagram
(GPCM Controlled–ACS = ‘00’) .........................................................20-14
20-8. External Bus Read Timing Diagram
(GPCM Controlled–TRLX = ‘0’ ACS = ‘10’) .......................................20-14
20-9. External Bus Read Timing Diagram
(GPCM Controlled–TRLX = ‘0’ ACS = ‘11’) .......................................20-15
20-10. External Bus Read Timing Diagram
(GPCM Controlled–TRLX = ‘1’, ACS = ‘10’, ACS = ‘11’) ...................20-15
MOTOROLA
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LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
20-11. External Bus Write Timing Diagram
(GPCM Controlled–TRLX = ‘0’, CSNT = ‘0’) .....................................20-16
20-12. External Bus Write Timing Diagram
(GPCM Controlled–TRLX = ‘0’, CSNT = ‘1’) .....................................20-16
20-13. External Bus Write Timing Diagram
(GPCM Controlled–TRLX = ‘1’, CSNT = ‘1’) .....................................20-17
20-14. External Bus Timing Diagram (UPM Controlled Signals) ..................20-18
20-15. Asynchronous UPWAIT Asserted Detection In
UPM Handled Cycles Timing Diagram ..............................................20-19
20-16. Asynchronous UPWAIT Negated Detection In
UPM Handled Cycles Timing Diagram ..............................................20-19
20-17. Synchronous External Master Access Timing Diagram
(GPCM Handled ACS = ‘00’) ............................................................20-20
20-18. Asynchronous External Master Memory Access Timing Diagram
(GPCM Controlled–ACS = ’00’) ........................................................20-20
20-19. Asynchronous External Master Timing Diagram
(Control Signals Negation Time) .......................................................20-21
20-20. Interrupt Detection Timing Diagram
for External Level-Sensitive Lines .....................................................20-21
20-21. Interrupt Detection Timing Diagram
for External Edge-Sensitive Lines .....................................................20-22
20-22. Debug Port Clock Input Timing Diagram ...........................................20-22
20-23. Debug Port Timing Diagram ..............................................................20-23
20-24. Reset Timing Diagram (Configuration From Data Bus) ....................20-24
20-25. Reset Timing Diagram–MPC801 Data Bus Weak Drive
During Configuration .........................................................................20-25
20-26. Reset Timing Diagram–Debug Port Configuration ............................20-25
20-27. JTAG Test Clock Input Timing Diagram ............................................20-26
20-28. JTAG–Test Access Port Timing Diagram .........................................20-27
20-29. JTAG–TRST Timing Diagram ...........................................................20-27
20-30. Boundary Scan (JTAG) Timing Diagram ...........................................20-28
21-1. Parallel I/O Data-In/Data-Out Timing Diagram ....................................21-1
21-2. Baud Rate Generator from UART–Timing ..........................................21-2
21-3. UART Receive ....................................................................................21-4
21-4. UART Transmit ...................................................................................21-4
21-5. SPI Master (CP=0) ..............................................................................21-5
21-6. SPI Master (CP=1) ..............................................................................21-6
21-7. SPI Slave (CP=0) ................................................................................21-7
21-8. SPI Slave (CP=1) ................................................................................21-7
2
21-9. I
xxvi
C Bus Timing ....................................................................................21-9
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LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
B-1. General System Configuration ........................................................... B-27
B-2. SRAM Read Timing Analysis ............................................................. B-30
B-3. SRAM Write Timing Analysis ............................................................. B-30
B-4. EPROM 1 Wait State Read ................................................................ B-32
B-5. UPM Signal Timings ........................................................................... B-35
B-6. UPM RAM Configuration .................................................................... B-36
B-7. DRAM 3-Cycle Read .......................................................................... B-38
B-8. DRAM 3-Cycle Write .......................................................................... B-41
B-9. Burst Read Access ............................................................................. B-42
B-10. Write Burst Access ............................................................................. B-43
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LIST OF TABLES
Table Page
Number Title Number
2-1. Signal Descriptions ................................................................................2-2
2-2. Pin Breakout ........................................................................................2-10
3-1. MPC801 Internal Memory Map .............................................................3-1
4-1. Possible Reset Results .........................................................................4-1
5-1. Reset Clocks Source Configuration ......................................................5-5
5-2. tmbclk Divisions .....................................................................................5-6
5-3. XFC Capacitor Values .........................................................................5-13
5-4. MPC801 Low-Power Modes ................................................................5-18
6-1. Branch Prediction Policy .......................................................................6-6
6-2. “Before” and “After” Interrupts ...............................................................6-8
6-3. Special Ports to the Machine State Register Bits ................................6-11
6-4. Interrupt Latency .................................................................................6-11
6-5. Detection Order of Instruction-Related Interrupts ................................6-14
6-6. Interrupt Priorities Mapping .................................................................6-14
6-7. Standard Special-Purpose Registers ..................................................6-15
6-8. Standard Timebase Register Mapping ................................................6-16
6-9. Additional Special-Purpose Registers .................................................6-16
6-10. Other Control Registers .......................................................................6-18
6-11. Encoding of Special Registers Located Outside the Core ..................6-19
6-12. Address of Special Registers Located Outside the Core ....................6-19
6-13. Load/Store Instructions Timing ............................................................6-30
6-14. DAR, BAR, and DSISR Value Summary .............................................6-31
7-1. Offset of First Instruction by Interrupt Type ...........................................7-8
8-1. Instruction Execution Timing .................................................................8-1
9-1. IC_ADR Bits Functionality for the Cache Read Command .................9-10
9-2. IC_DAT Bit Layout When Reading a Tag ............................................9-11
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LIST OF TABLES (Continued)
Table Page
Number Title Number
10-1. DC_ADR Bit Functionality for Reading the Cache ..............................10-6
10-2. DC_DAT Bit Layout For Reading a Tag ..............................................10-7
11-1. Number of Effective Address Bits Replaced By Real Address Bits .....11-7
11-2. Number of Identical Entries Required in the Level One Table ............11-7
11-3. Number of Identical Entries Required in the Level Two Table ............11-7
11-4. Level One (Segment) Descriptor Format ............................................11-8
11-5. Level Two (Page) Descriptor Format ..................................................11-9
12-1. Priority of System Interface Unit Interrupt Sources .............................12-5
12-2. Multiplexing Control ...........................................................................12-16
12-3. Standard Timebase Register Mapping ..............................................12-24
13-1. MPC801 System Interface Unit Signals ..............................................13-4
13-2. Data Bus Requirements For Read Cycles ........................................13-26
13-3. Data Bus Contents for Write Cycles ..................................................13-27
13-4. BURST/TSIZE Encoding ...................................................................13-33
13-5. Definitions of Address Types .............................................................13-34
13-6. Termination Signal Protocol ..............................................................13-36
14-1. PowerPC Little-Endian Effective Address Modification For
Individually Aligned Scalar ..................................................................14-1
14-2. Endian Mode Programming For Core Data Structures .......................14-1
14-3. Little-Endian Program/Data Path Between the Register and
32-Bit Memory .....................................................................................14-3
14-4. Little-Endian Program/Data Path Between the Register and
16-Bit Memory .....................................................................................14-3
14-5. Little-Endian Program/Data Path Between the Register and
8-Bit Memory .......................................................................................14-4
15-1. Boot Bank Field Values After Reset ..................................................15-16
15-2. UPM RAM Word ................................................................................15-25
15-3. Byte Select Enable Function .............................................................15-30
15-4. Loop Field For UPM Service Requests .............................................15-31
15-5. Address Multiplexing .........................................................................15-32
15-6. AMA/AMB Definition For DRAM Interfaces .......................................15-33
15-7. UPM Start Address Locations ...........................................................15-39
15-8. UPM RAM Word Bit Field Example ...................................................15-40
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LIST OF TABLES (Continued)
Table Page
Number Title Number
15-9. UPM RAM Word Bit Field Example ...................................................15-50
15-10. EDO Connection Field Value Example .............................................15-52
15-11. GPL5 Signal Behavior .......................................................................15-60
16-1. Typical Baud Rates of Asynchronous Communication .....................16-13
16-2. Port B Pin Assignment ......................................................................16-36
18-1. VF Pin Encoding .................................................................................18-4
18-2. Detecting the Trace Buffer Starting Point ............................................18-7
18-3. Fetch Show Cycle Control ...................................................................18-8
18-4. Instruction Watchpoints Programming Options .................................18-17
18-5. Load/Store Data Events ....................................................................18-18
18-6. Load/Store Watchpoint Programming Options ..................................18-18
18-7. Checkstop State and Debug Mode ...................................................18-27
18-8. Trap Enable Data Shifted Into Development Port Shift Register ......18-36
18-9. Debug Port Command Shifted Into the Development Port
Shift Register .....................................................................................18-36
18-10. Status/Data Shifted Out of the Development Port
Shift Register .....................................................................................18-37
18-11. Debug Instructions/Data Shifted Into the Development Port
Shift Register .....................................................................................18-38
18-12. Development Support Register Protection ........................................18-41
19-1. Boundary Scan Bit Definition ..............................................................19-6
19-2. Instruction Decoding .........................................................................19-17
20-1. Bus Operation Timing .........................................................................20-6
20-2. Interrupt Timing .................................................................................20-21
20-3. Debug Port Timing ............................................................................20-22
20-4. Reset Timing .....................................................................................20-23
20-5. JTAG Timing .....................................................................................20-26
A-1. Standard Special-Purpose Registers ....................................................A-2
A-2. Standard Timebase Register Mapping ..................................................A-2
A-3. Added Special-Purpose Registers ........................................................A-3
A-4. Other Control Registers ........................................................................A-4
A-5. MPC801 Internal Memory Map .............................................................A-5
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MPC801 USER’S MANUAL
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LIST OF TABLES (Continued)
Table Page
Number Title Number
B-1. Read Single Beat–RSSA ...................................................................... B-3
B-2. Write Single Beat–WSSA ..................................................................... B-3
B-3. Read Burst Cycle–RBSA ...................................................................... B-3
B-4. Write Burst Cycle–WBSA ..................................................................... B-3
B-5. Refresh Cycle–RBSA ........................................................................... B-4
B-6. Exception Cycle–ECSA ........................................................................ B-4
B-7. Physical Memory Map Example ......................................................... B-11
B-8. MMU Register .................................................................................... B-11
B-9. Option Register .................................................................................. B-28
B-10. Base Register ..................................................................................... B-28
B-11. UPM Word Structure .......................................................................... B-34
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1
SECTION 1
INTRODUCTION
The MPC801 PowerPC
™
Quad Integrated Communications Controller (PowerQUICC) is a
versatile one-chip integrated microprocessor and peripheral combination that can be used
in a variety of controller applications. It is a low-cost version of the MPC860 that provides an
effective price/performance solution across a wide range of applications. The MPC801, like
the MPC860, combines a high-performance PowerPC core with a multifaceted system
integration package. Unless otherwise specified, the PowerQUICC unit will be referred to as
the MPC801 in this manual.
The MPC801 is a PowerPC-based derivative of Motorola’s MC68360 Quad Integrated
™
Communications Controller (QUICC
). The CPU on the MPC801 is a 32-bit PowerPC
implementation that incorporates memory management units and instruction and data
caches. The memory controller has been enhanced, thus enabling the MPC801 to support
any type of memory, including high performance memories and newer dynamic random
access memories (DRAMs).
The purpose of this manual is to describe the operation of all the MPC801 functionality with
concentration on the I/O functions. Additional details on the MPC801 can be found in the
PowerPC architectural specifications.
1.1 FEATURES
The following list summarizes the main features of the MPC801:
• PowerPC Single-Issue Integer Core Performs Branch Folding and Prediction with
Conditional Prefetch, but Without Conditional Execution
• Precise Exception Model
• Extensive System Development Support
— On-chip watchpoints and breakpoints
— Program flow tracking
— On-chip emulation (OnCE) development interface
• High Performance (52K Dhrystone 2.1 MIPS @40MHz, 3.3V, 1.3W Total Power)
• Low Power (3.3V Operation with 5V TTL Compatibility)
• MPC8XX PowerPC System Interface, Including a Periodic Interrupt Timer, a Bus
Monitor, and Real-Time Clocks
• Fully Static Design (0-40MHz Operation)
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