MOTOROLA MMSF10N02Z Technical data

10N02Z

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SEMICONDUCTOR TECHNICAL DATA

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Medium Power Surface Mount Products

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EZFETs are an advanced series of power MOSFETs which
utilize Motorola’s High Cell Density HDTMOS process and contain
monolithic back–to–back zener diodes. These zener diodes
provide protection against ESD and unexpected transients. These
miniature surface mount MOSFETs feature low R
logic level performance. They are capable of withstanding high
energy in the avalanche and commutation modes and the
drain–to–source diode has a very low reverse recovery time.
EZFET devices are designed for use in low voltage, high speed
switching applications where power efficiency is important.

• Zener Protected Gates Provide Electrostatic Discharge Protection

• Low R

Provides Higher Efficiency and Extends Battery Life

DS(on)

• Logic Level Gate Drive — Can Be Driven by Logic ICs

• Miniature SO–8 Surface Mount Package — Saves Board Space

• Diode Exhibits High Speed, With Soft Recovery

• I

Specified at Elevated Temperature

DSS

• Mounting Information for SO–8 Package Provided

DS(on)

and true



Motorola Preferred Device

SINGLE TMOS

POWER MOSFET

10 AMPERES

20 VOLTS

R



D

CASE 751–05, Style 12

G

S

Source
Source
Source

Gate

DS(on)

= 0.015 OHM

SO–8

1

8

Drain

2

7

Drain

3

6

Drain

4

5

Drain

Top View

MAXIMUM RATINGS

Drain–to–Source Voltage V
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
Gate–to–Source Voltage — Continuous V
Drain Current — Continuous @ TA = 25°C

Drain Current — Continuous @ TA = 70°C
Drain Current — Single Pulse (tp ≤ 10 µs)

Total Power Dissipation @ TA = 25°C (1) P
Operating and Storage Temperature Range TJ, T
Thermal Resistance — Junction to Ambient R
Maximum T emperature for Soldering T

(1) When mounted on 1 inch square FR–4 or G–10 board (VGS = 4.5 V, @ 10 Seconds)

(TJ = 25°C unless otherwise noted)

Rating

Symbol Value Unit

DSS

DGR

GS

I

D

I

D

I

DM

D

θJA

L

stg

20 Vdc
20 Vdc

± 12 Vdc

10

7.0
80

2.5 Watts

– 55 to 150 °C

50 °C/W

260 °C

Adc

Apk

DEVICE MARKING ORDERING INFORMATION

Device Reel Size Tape Width Quantity

MMSF10N02ZR2 13″ 12 mm embossed tape 2500 units

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

Preferred devices are Motorola recommended choices for future use and best overall value.

Designer’s, HDTMOS and EZFET are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trade­mark of the Bergquist Company.

REV 2

Motorola TMOS Power MOSFET Transistor Device Data

 Motorola, Inc. 1997

1

MMSF10N02Z

)

f = 1.0 MHz)

(

DD

,

D

,

(

DS

,

D

,

)

dIS/dt = 100 A/µs)

ELECTRICAL CHARACTERISTICS

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (3)

(VGS = 0 Vdc, ID = 0.25 mAdc)
T emperature Coef ficient (Positive)

Zero Gate Voltage Drain Current

(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125°C)

Gate–Body Leakage Current (VGS = ± 12 Vdc, VDS = 0 Vdc) I

ON CHARACTERISTICS

Gate Threshold Voltage (Cpk ≥ 2.0) (3)

(VDS = VGS, ID = 0.25 mAdc)
Threshold Temperature Coefficient (Negative)

Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (3)

(VGS = 4.5 Vdc, ID = 10 Adc)
(VGS = 2.7 Vdc, ID = 5.0 Adc)

Forward Transconductance (VDS = 9.0 Vdc, ID = 5.0 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance
Transfer Capacitance

SWITCHING CHARACTERISTICS

Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time t
Gate Charge

SOURCE–DRAIN DIODE CHARACTERISTICS

Forward On–Voltage

Reverse Recovery Time

Reverse Recovery Storage Charge Q

(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.

(1)

Cpk =

(TA = 25°C unless otherwise noted)

(VDS = 10 Vdc, VGS = 0 Vdc,

(2)

(VDD = 10 Vdc, ID = 5.0 Adc,

(IS = 10 Adc, VGS = 0 Vdc, TJ = 125°C)

Max limit – Typ

3 x SIGMA

f = 1.0 MHz

VGS = 4.0 Vdc, RG = 10 Ω)

(VDS = 16 Vdc, ID = 10 Adc,

VGS = 4.0 Vdc)

(IS = 10 Adc, VGS = 0 Vdc)

(IS = 10 Adc, VGS = 0 Vdc,

dI

/dt = 100 A/µs

V

(BR)DSS

I

DSS

GSS

V

GS(th)

R

DS(on)

FS

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

f

Q
Q
Q
Q

V

SD

t

rr

t

a

t

b

RR

20
—

—
—

— 0.6 1.5 µAdc

0.5
—

—
—

11 14 — Mhos

— 1 150 1225 pF
— 775 810
— 375 480

— 65 75 ns
— 360 440
— 325 640
— 575 860

T
1
2
3

— 26 32 nC
— 2.5 —
— 13 —
— 9.0 —

—
—

— 765 —
— 240 —
— 530 —
— 8.7 — µC

—
17

—
—

0.72

2.86

13
16

0.83

0.68

—
—

10

100

1.1
—

15
19

1.2
—

Vdc

mV/°C

µAdc

Vdc

mV/°C

mΩ

Vdc

ns

2

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

MMSF10N02Z

20
18
16
14
12
10

8
6

, DRAIN CURRENT (AMPS)

D

I

4
2
0

0 0.4 1.6 2

VGS = 12V

4.5 V

0.80.2 1.4 1.810.6

VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

2.7 V

1.9 V

1.8 V

1.7 V

1.6 V

1.5 V

TJ = 25°C

1.2

Figure 1. On–Region Characteristics

0.03
ID = 10 A

0.025

0.02

0.015

TJ = 25

14

VDS ≥ 10 V

TJ = 25°C

12

10

8

6

, DRAIN CURRENT (AMPS)

4

D

I

2

0

0.50

VGS, GATE–T O–SOURCE VOLTAGE (VOLTS)

100°C

25°C

TJ = –55°C

1 1.5 2 2.5

Figure 2. Transfer Characteristics

0.03
TJ = 25°C

°

C

0.025

0.02

VGS = 2.7 V

0.015

0.01

0.005

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

0

DS(on)

R

3456789101112

2

VGS, GATE–T O–SOURCE VOLT AGE (VOLTS)

Figure 3. On–Resistance versus

Gate–to–Source V oltage

1.6
VGS =4.5 V

1.4

ID = 5 A

1.2

1

0.8

0.6

0.4

0.2

, DRAIN–TO–SOURCE RESIST ANCE (NORMALIZED)

0
–50 0 50 100 150

DS(on)

R

TJ, JUNCTION TEMPERATURE (°C)

7

4.5 V

13 15

0.01

0.005

, DRAIN–TO–SOURCE RESIST ANCE (OHMS)

0

DS(on)

135 911

R

ID, DRAIN CURRENT (AMPS)

Figure 4. On–Resistance versus Drain Current

and Gate Voltage

10000

, LEAKAGE (nA)
I

1257525–25

VGS = 0 V

1000

100

10

1

DSS

0.1

0.01
0 5 10 15 17.5

VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

TJ = 125°C

100°C

25°C

12.57.5

202.5

Figure 5. On–Resistance Variation

with Temperature

Motorola TMOS Power MOSFET Transistor Device Data

Figure 6. Drain–to–Source Leakage Current

versus V oltage

3

MMSF10N02Z

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter­mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat­ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I

) can be made from a rudimentary analysis of

G(A V)

the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a resis­tive load, VGS remains virtually constant at a level known as
the plateau voltage, V

. Therefore, rise and fall times may

SGP

be approximated by the following:
tr = Q2 x RG/(VGG – V
tf = Q2 x RG/V

GSP

GSP

)

where
VGG = the gate drive voltage, which varies from zero to V

GG

RG = the gate drive resistance
and Q2 and V

are read from the gate charge curve.

GSP

During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val­ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

t

d(off)

= RG C
= RG C

In [VGG/(VGG – V

iss

In (VGG/V

iss

GSP

)]

GSP

)

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off–state condition when cal­culating t
on–state when calculating t

and is read at a voltage corresponding to the

d(on)

d(off)

.

At high switching speeds, parasitic circuit elements com­plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func­tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea­sure and, consequently , is not specified.

The resistive switching time variation versus gate resis­tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op­erated into an inductive load; however, snubbing reduces
switching losses.

2000

1500

C

iss

1000

C, CAPACITANCE (pF)

500

0

0812

4

VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

C

oss

C

rss

T

J

VGS = 0 V

16

Figure 7. Capacitance Variation

= 25

°C

2061014218

4

Motorola TMOS Power MOSFET Transistor Device Data

MMSF10N02Z

8

6

4

Q1

V

DS

QT

V

Q2

GS

16
14

12
10
8

6

1000

100

t, TIME (ns)

VDD = 10 V
ID = 5 A
VGS = 4 V
TJ = 25

°

C

t

d(off)

t

d(on)

t

f
t

r

4

°

C

2

0

, GATE–T O–SOURCE VOLT AGE (VOLTS)

GS

V

2

0

Q3

0510

Qg, TOTAL GATE CHARGE (nC)

15

ID = 10 A
TJ = 25

20 25

Figure 8. Gate–T o–Source and Drain–To–Source

V oltage versus Total Charge

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse re­covery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.

System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier de­vice, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.

The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ring­ing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

DS

V

10

1 10010

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

di/dts. The diode’s negative di/dt during ta is directly con­trolled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode charac­teristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.

Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse re­covery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise gen­erated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

12

VGS = 0 V
TJ = 25

°

10

8

6

4

, SOURCE CURRENT (AMPS)

S

2

I

0

C

VSD, SOURCE–TO–DRAIN VOL TAGE (VOLTS)

Figure 10. Diode Forward V oltage versus Current

Motorola TMOS Power MOSFET Transistor Device Data

0.5 0.6 0.7

0.40.30.20.10

0.8 0.9

5

MMSF10N02Z

di/dt = 300 A/µs

, SOURCE CURRENT

S

I

Figure 11. Reverse Recovery T ime (trr)

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves de­fine the maximum simultaneous drain–to–source voltage
and drain current that a transistor can handle safely when
it is forward biased. Curves are based upon maximum
peak junction temperature and a case temperature (TC)
of 25°C. Peak repetitive pulsed power limits are deter-
mined by using the thermal response data in conjunction
with the procedures discussed in AN569, “Transient
Thermal Resistance – General Data and Its Use.”

Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (V
transition time (tr, tf) does not exceed 10 µs. In addition

) is exceeded, and that the

DSS

Standard Cell Density

t

rr

High Cell Density

t

rr

t

b

t

a

t, TIME

the total power averaged over a complete switching cycle
must not exceed (T

J(MAX)

– TC)/(R

θJC

).

A power MOSFET designated E–FET can be safely
used in switching circuits with unclamped inductive
loads. For reliable operation, the stored energy from cir­cuit inductance dissipated in the transistor while in ava­lanche must be less than the rated limit and must be
adjusted for operating conditions differing from those
specified. Although industry practice is to rate in terms of
energy, avalanche energy capability is not a constant.
The energy rating decreases non–linearly with an in­crease of peak current in avalanche and peak junction
temperature.

100

10

1

, DRAIN CURRENT (AMPS)

D

I

0.1

0.1

VGS = 11 V
SINGLE PULSE
TC = 25

°

C

dc

VDS, DRAIN–TO–SOURCE VOL TAGE (VOLTS)

10 ms

R

LIMIT

DS(on)

THERMAL LIMIT
PACKAGE LIMIT

1

1 ms

10

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

100

6

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

1

D = 0.5

0.2

0.1

0.1

0.01

THERMAL RESISTANCE

Rthja(t), EFFECTIVE TRANSIENT

0.001

1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01

0.05

0.02

0.01

SINGLE PULSE

t, TIME (s)

Figure 13. Thermal Response

di/dt

I

S

t

a

t

rr

t

b

MMSF10N02Z

1.0E+02 1.0E+03

TIME

t

p

0.25 I

S

I

S

Figure 14. Diode Reverse Recovery Waveform

Motorola TMOS Power MOSFET Transistor Device Data

7

MMSF10N02Z

INFORMATION FOR USING THE SO–8 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface

between the board and the package. With the correct pad
geometry, the packages will self–align when subjected to a
solder reflow process.

0.041

1.04

0.208

5.28

0.015

0.38

SO–8 POWER DISSIP ATION

The power dissipation of the SO–8 is a function of the input
pad size. This can vary from the minimum pad size for
soldering to the pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by T
temperature of the die, R
device junction to ambient; and the operating temperature, TA.
Using the values provided on the data sheet for the SO–8
package, PD can be calculated as follows:

PD =

The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into

, the maximum rated junction

J(max)

, the thermal resistance from the

θJA

T

J(max)

R

θJA

– T

A

0.126

3.20

0.0256

0.65

inches

mm

the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this case
is 2.5 Watts.

PD =

150°C – 25°C

= 2.5 Watts

50°C/W

The 50°C/W for the SO–8 package assumes the
recommended footprint on a glass epoxy printed circuit board
to achieve a power dissipation of 2.5 Watts using the footprint
shown. Another alternative would be to use a ceramic
substrate or an aluminum core board such as Thermal Clad.
Using board material such as Thermal Clad, the power
dissipation can be doubled using the same footprint.

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.

• Always preheat the device.

• The delta temperature between the preheat and soldering

should be 100°C or less.*

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.

8

• The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

• When shifting from preheating to soldering, the maximum

temperature gradient shall be 5°C or less.

• After soldering has been completed, the device should be

allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied during

cooling.

* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of control
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones and a figure
for belt speed. T aken together , these control settings make up
a heating “profile” for that particular circuit board. On
machines controlled by a computer, the computer remembers
these profiles from one operating session to the next. Figure
16 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems, but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
type of solder used, and the type of board or substrate material
being used. This profile shows temperature versus time. The

MMSF10N02Z

line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/in­frared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177–189°C. When this type of
furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.

200

150

100

50°C

STEP 1

PREHEA T

ZONE 1
“RAMP”

°

C

DESIRED CURVE FOR HIGH
MASS ASSEMBLIES

°

C

°

C

TIME (3 TO 7 MINUTES TOTAL)

STEP 2

VENT

“SOAK”

150°C

Figure 15. T ypical Solder Heating Profile

STEP 3

HEATING

ZONES 2 & 5

“RAMP”

160

100°C

DESIRED CURVE FOR LOW
MASS ASSEMBLIES

STEP 4

HEATING

ZONES 3 & 6

“SOAK”

°

C

SOLDER IS LIQUID FOR
40 TO 80 SECONDS

°

C

140

(DEPENDING ON
MASS OF ASSEMBLY)

STEP 5

HEATING

ZONES 4 & 7

“SPIKE”

170°C

T

MAX

STEP 6

VENT

STEP 7

COOLING

205

°

TO 219°C
PEAK AT
SOLDER JOINT

Motorola TMOS Power MOSFET Transistor Device Data

9

MMSF10N02Z

P ACKAGE DIMENSIONS

C

A

A1

D

58

0.25MB

E

1

B

e

H

4

M

h

X 45

_

q

C

A

SEATING
PLANE

0.10

L

B

SS

A0.25MCB

CASE 751–05

SO–8

ISSUE S

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.

2. DIMENSIONS ARE IN MILLIMETERS.

3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.

MILLIMETERS

DIM MIN MAX

A 1.35 1.75

A1 0.10 0.25

B 0.35 0.49
C 0.18 0.25
D 4.80 5.00
E

3.80 4.00

1.27 BSCe

H 5.80 6.20
h

0.25 0.50

L 0.40 1.25

0 7

q

STYLE 12:

PIN 1. SOURCE

2. SOURCE

3. SOURCE

4. GATE

5. DRAIN

6. DRAIN

7. DRAIN

8. DRAIN

__

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

Mfax is a trademark of Motorola, Inc.

How to reach us:
USA/EUROPE /Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1,

P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488
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INTERNET: http://motorola.com/sps

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Motorola TMOS Power MOSFET Transistor Device Data

MMSF10N02Z/D