Motorola MCM72JG32SG66, MCM72JG64SG66 Datasheet
MCM72JG32•MCM72JG64
1
MOTOROLA FAST SRAM
Advance Information
256K and 512K Pipelined
BurstRAM Sedcondary Cache
Module for Pentium
The MCM72JG32 and MCM72JG64 are designed to provide a burstable, high
performance, 256K/512K L2 cache for the Pentium microprocessor in conjunction with Intel’s Triton chip set. The modules are configured as 32K x 64 and
64K x 64 bits in a 160 pin card edge memory module. Each module uses four of
Motorola’s 5 V 32K x 18 or 64K x 18 BurstRAMs and one Motorola 5 V 32K x 8
FSRAM for the tag RAM.
Bursts can be initiated with either address status processor (ADSP
) or cache
address status (CADS
). Subsequent burst addresses are generated internal to
the BurstRAM by the cache burst advance (CADV
) input pin.
Write cycles are internally self timed and are initiated by the rising edge of the
clock (CLK0, CLK1) input. Eight write enables are provided for byte write control.
PD0 – PD4 map into the Triton chip set for auto–configuration of the cache
control.
Module family pinout supports 5 V and 3.3 V components. It is recommended
that all power supplies be connected.
These cache modules are plug and pin compatible with the
MCM64AF32SG15, a 256K byte asynchronous module also designed for the
Pentium microprocessor in conjunction with Intel’s Triton chip set.
• Pentium–Style Burst Counter on Chip
• Pipelined Data Out
• 160 Pin Card Edge Module
• Address Pipeline Supported by ADSP
Disabled with Ex
• All Cache Data and Tag I/Os are TTL Compatible
• Three State Outputs
• Byte Write Capability
• Fast Module Clock Rates: 66 MHz
• Fast SRAM Access Times:15 ns for Tag RAM
9 ns for Data RAMs
• Decoupling Capacitors for Each Fast Static RAM
• High Quality Multi–Layer FR4 PWB with Separate Power and Ground
Planes
• I/Os are 3.3 V Compatible on Data RAMs
• Burndy Connector, Part Number: CELP2X80SC3Z48
• Series 20 Ω Resistors for Noise Immunity
BurstRAM is a trademark of Motorola.
Pentium is a trademark of Intel Corp.
This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice.
160–LEAD CARD
EDGE
CASE 1113A–01
TOP VIEW
80
43
42
1
Order this document
by MCM72JG32/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM72JG32/D
MCM72JG32
MCM72JG64
REV 1
5/95
Motorola, Inc. 1995
PIN ASSIGNMENT
160–PIN CARD EDGE MODULE
TOP VIEW
V
SS
TIO1
TIO7
TIO5
TIO3
(RSVD) NC
VCC5
(RSVD) NC
*(CAA4) CADV
V
SS
COE
CWE5
CWE7
CWE1
VCC5
CWE3
*(CAB3) NC
*(CALE) NC
V
SS
(RSVD) NC
A4
A6
A8
A10
VCC5
A17
V
SS
A9
A14
A15
(RSVD) NC
PD0
PD2
PD4
V
SS
CLK0
V
SS
DQ63
VCC5
DQ61
DQ59
DQ57
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
V
SS
TIO0
TIO2
TIO6
TIO4
NC (RSVD)
VCC3
TWE
CADS (CAA3)*
V
SS
CWE4
CWE6
CWE0
CWE2
VCC3
CCS
(CAB4)*
NC (GWE
)**
NC (BWE
)**
V
SS
A3
A7
A5
A11
A16
VCC3
NC (A18)
{
V
SS
A12
A13
ADSP
NC (ECS1, CS)
NC (ECS2
)
PD1
PD3
V
SS
CLK1
V
SS
DQ62
VCC3
DQ60
DQ58
DQ56
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
V
SS
DQ55
DQ53
DQ51
DQ49
V
SS
DQ47
DQ45
DQ43
VCC5
DQ41
DQ39
DQ37
V
SS
DQ35
DQ33
DQ31
VCC5
DQ29
DQ27
DQ25
V
SS
DQ23
DQ21
DQ19
VCC5
DQ17
DQ15
DQ13
V
SS
DQ11
DQ9
DQ7
VCC5
DQ5
DQ3
DQ1
V
SS
V
SS
DQ54
DQ52
DQ50
DQ48
V
SS
DQ46
DQ44
DQ42
VCC3
DQ40
DQ38
DQ36
V
SS
DQ34
DQ32
DQ30
VCC3
DQ28
DQ26
DQ24
V
SS
DQ22
DQ20
DQ18
VCC3
DQ16
DQ14
DQ12
V
SS
DQ10
DQ8
DQ6
VCC3
DQ4
DQ2
DQ0
V
SS
PIN NAMES
A3 – A18 Cache Address. . . . . . . . . . . . . . . . . . . . .
DQ0 – DQ63 Data Input/Output. . . . . . . . . . . . . . . .
CLK0, CLK1 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . .
CWE0
– CWE7 Cache Write Enable. . . . . . . . . . .
BWE
** Byte Write Enable. . . . . . . . . . . . . . . . . . . . .
GWE
** Global Write Enable. . . . . . . . . . . . . . . . . . .
TIO0 – TIO7 Tag Input/Output. . . . . . . . . . . . . . . . .
TWE
Tag Write Enable. . . . . . . . . . . . . . . . . . . . . . . .
CADS
Cache Address Status. . . . . . . . . . . . . . . . .
ADSP
Address Status Processor. . . . . . . . . . . . . . .
CADV
Cache Burst Advance. . . . . . . . . . . . . . . . . .
COE
Cache Output Enable. . . . . . . . . . . . . . . . . . . .
CCS
Cache Chip Select. . . . . . . . . . . . . . . . . . . . . . .
RSVD Reserved for Future Use. . . . . . . . . . . . . . .
PD0 – PD4 Presence Detect. . . . . . . . . . . . . . . . . .
VCC5 + 5 V Power Supply. . . . . . . . . . . . . . . . . . . . .
VCC3 + 3.3 V Power Supply. . . . . . . . . . . . . . . . . . .
V
SS
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NC No Connect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTES:
* Signals in parentheses indicate pin descriptions for asynchronous Triton
chip set module.
** Signals in parentheses will be implemented in future burstable Triton modules.
{
NC for MCM72JG32, A18 for MCM72JG64.
MCM72JG32•MCM72JG64
2
MOTOROLA FAST SRAM
PRESENCE DETECT TABLE
Cache Size and
Functionality
Module PD4 PD3 PD2 PD1 PD0
256K Async MCM64AF32 V
SS
NC V
SS
V
SS
NC
512K Async — V
SS
V
SS
NC V
SS
NC
256K Burst — V
SS
NC V
SS
NC V
SS
256K Pipe Burst MCM72JG32 V
SS
NC V
SS
NC NC
512K Burst — V
SS
V
SS
NC NC V
SS
512K Pipe Burst MCM72JG64 V
SS
V
SS
NC NC NC
512K 2–Bank
Burst
— V
SS
V
SS
NC V
SS
V
SS
MCM72JG32•MCM72JG64
3
MOTOROLA FAST SRAM
MCM72JG32 MODULE BLOCK DIAGRAM
A18 – NC
CCS
CADV
ADSP
CADS
CLK0
COE
A3 – A17
LW
MCM67J518
ADV
K
G
E
DQ0 – DQ7
DQ8
UW
ADSP
ADSC
DQ9 – DQ16
DQ17
A0 – A14
LW
MCM67J518
ADV
K
G
E
DQ0 – DQ7
DQ8
UW
ADSP
ADSC
DQ9 – DQ16
DQ17
A0 – A14
LW
MCM67J518
ADV
K
G
E
DQ0 – DQ7
DQ8
UW
ADSP
ADSC
DQ9 – DQ16
DQ17
A0 – A14
LW
MCM67J518
ADV
K
G
E
DQ0 – DQ7
DQ8
UW
ADSP
ADSC
DQ9 – DQ16
DQ17
DQ0 – DQ7
DQ8– DQ15
CWE0
CWE1
8
8
A0 – A14
A0 – A12
E
DQ0 – DQ7
A13
W
A14
G
32K x 8
CLK1
TIO0 – TIO7
A5 – A17
TWE
15
13
DQ16 – DQ23
DQ24– DQ31
CWE2
CWE3
8
8
DQ32 – DQ39
DQ40– DQ47
CWE4
CWE5
8
8
DQ48 – DQ55
DQ56– DQ63
CWE6
CWE7
8
8
PD2
PD0 – NC
PD1 – NC
PD4
PD3 – NC
MCM72JG32•MCM72JG64
4
MOTOROLA FAST SRAM
MCM72JG64 MODULE BLOCK DIAGRAM
CCS
CADV
ADSP
CADS
CLK0
COE
A3 – A18
LW
MCM67J618
ADV
K
G
E
DQ0 – DQ7
DQ8
UW
ADSP
ADSC
DQ9 – DQ16
DQ17
A0 – A15
LW
MCM67J618
ADV
K
G
E
DQ0 – DQ7
DQ8
UW
ADSP
ADSC
DQ9 – DQ16
DQ17
A0 – A15
LW
MCM67J618
ADV
K
G
E
DQ0 – DQ7
DQ8
UW
ADSP
ADSC
DQ9 – DQ16
DQ17
A0 – A15
LW
MCM67J618
ADV
K
G
E
DQ0 – DQ7
DQ8
UW
ADSP
ADSC
DQ9 – DQ16
DQ17
DQ0 – DQ7
DQ8– DQ15
CWE0
CWE1
8
8
A0 – A15
A0 – A13
E
DQ0 – DQ7
W
A14
G
CLK1
TIO0 – TIO7
A5 – A18
TWE
16
14
DQ16 – DQ23
DQ23– DQ31
CWE2
CWE3
8
8
DQ32 – DQ39
DQ40– DQ47
CWE4
CWE5
8
8
DQ48 – DQ55
DQ56– DQ63
CWE6
CWE7
8
8
PD2 – NC
PD0 – NC
PD1 – NC
PD4
PD3
32K x 8
MCM72JG32•MCM72JG64
5
MOTOROLA FAST SRAM
PIN DESCRIPTIONS
160–Lead Card Edge Pin Locations Symbol
Type Description
20, 21, 22, 23, 24, 28, 29,
101, 102, 103, 104, 106, 108, 109, 110
A3 – A18 Input Address Inputs: These inputs are registered into data RAMs and must
meet setup and hold times. The tag RAM addresses are not registered.
36, 116 CLK0,
CLK1
Input Clock: This signal registers the address, data in, and all control signals
except COE
.
11, 12, 13, 14, 92, 93, 94, 96 CWE0 –
CWE7
Input Cache Data Byte Write Enable: Active low write signal for data RAMs.
8 TWE Input Tag Write Enable: Active low write signal for tag RAMs.
— BWE Input Byte Write Enable: To be used in future modules.
— GWE Input Global Write Enable: To be used in future modules.
16 CCS Input Chip Select: Active low chip enable for data RAMs.
30 ADSP Input Address Status Processor: Initiates READ, WRITE, or chip deselect
cycle (Exception–chip deselect does not occur when ADSP
is asserted
and CCS
is high.
9 CADS Input Cache Address Status: Initiates READ, WRITE, or chip deselect cycle.
89 CADV Input Cache Burst Advance: Increments address count in accordance with
interleaved count style.
91 COE Input Cache Output Enable: Active low asynchronous input.
Low–enables output buffers (DQ pins)
High–DQx pins are high impedance.
38, 40, 41, 42, 44, 45, 46, 47, 49, 50, 51,
53, 54, 55, 57, 58, 59, 61, 62, 63, 65, 66,
67, 69, 70, 71, 73, 74, 75, 77, 78, 79,
118, 120, 121, 122, 124, 125, 126, 127,
129, 130, 131, 133, 134, 135, 137, 138,
139, 141, 142, 143, 145, 146, 147, 149,
150, 151, 153, 154, 155, 157, 158, 159
DQ0 –
DQ63
I/O Synchronous Data I/O:
Drives data out of data RAMs during READ cycles.
Stores data to data RAMs during WRITE cycles.
2, 3, 4, 5, 82, 83, 84, 85 TIO0 –
TIO7
I/O Tag RAM I/O:
Drives data out during tag compare cycles.
Stores data to tag RAM during tag WRITE cycles.
33, 34, 112, 113, 114 PD0 –
PD4
— Presence Detect: See Presence Detect Table
7, 15, 25, 39, 52, 60, 68, 76 VCC3 Supply Power Supply: 3.3 V ± 5%.
87, 95, 105, 119, 132, 140, 148, 156 VCC5 Supply Power Supply: 5.0 V ± 5%.
1, 10, 19, 27, 35, 37, 43, 48, 56, 64, 72,
80, 81, 90, 99, 107, 115, 117, 123, 128,
136, 144, 152, 160
V
SS
Supply Ground
6, 17, 18, 26, 31, 32, 86, 88, 97, 98, 100,
111
NC — No Connection: There is no connection to the module.
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