Motorola MCM72F7DG9, MCM72F7DG12, MCM72F6DG12, MCM72F6DG10, MCM72F7DG10 Datasheet
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
512KB and 1MB Synchronous
Fast Static RAM Module
Order this document
by MCM72F6/D
MCM72F6
MCM72F7
The MCM72F6 (512KB) is configured as 64K x 72 bits and the MCM72F7
(1MB) is configured as 128K x 72 bits. Both are packaged in a 168–pin dual–
in–line memory module DIMM. Each module uses Motorola’s 3.3 V 64K x 18 bit
flow–through BurstRAMs.
Address (A), data inputs (DQ, DP), and all control signals except output enable
) are clock (K) controlled through positive–edge–triggered noninverting reg-
(G
isters.
Write cycles are internally self–timed and initiated by the rising edge of the
clock (K) input. This feature provides increased timing flexibility for incoming
signals. Synchronous byte write (W
both bytes.
• Single 3.3 V + 10%, – 5% Power Supply
• Plug and Pin Compatibility with 2MB and 4MB
• Multiple Clock Pins for Reduced Loading
• All Inputs and Outputs are L VTTL Compatible
• Byte Write Capability
• Fast SRAM Access Times: 9/10/12 ns
• Decoupling Capacitors for Each Fast Static RAM
• High Quality Multi–Layer FR4 PWB With Separate Power and Ground
Planes
• Amp Connector, Part Number: 390064–4
• 168–Pin DIMM Module
) allows writes to either individual bytes or to
168–LEAD DIMM
CASE 1115J–01
TOP VIEW
1
11
40
41
REV 3
11/24/97
Motorola, Inc. 1997
MOTOROLA FAST SRAM
84
MCM72F6•MCM72F7
1
MCM72F6 BLOCK DIAGRAM
E0
G0
A0 – A15
ADSP
W0
W1
K0
V
DD
V
SS
DQ0 – DQ7
DP0
DQ8 – DQ15
DP1
64K x 18
SE1
G
A0 – A15
ADSC
SBa
SBb
K
SE2
ADV
ADSP
SGW
SW
LBO
SE3
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8
DQ16 – DQ23
DP2
DQ24 – DQ31
DP3
W2
W3
K1
64K x 18
SE1
G
A0 – A15
ADSC
SBa
SBb
K
SE2
ADV
ADSP
SGW
SW
LBO
SE3
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8
DQ32 – DQ39
DP4
DQ40 – DQ47
DP5
W4
W5
K2
64K x 18
SE1
G
A0 – A15
ADSC
SBa
SBb
K
SE2
ADV
ADSP
SGW
SW
LBO
SE3
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8
DQ48 – DQ55
DP6
DQ56 – DQ63
DP7
W6
W7
K3
64K x 18
SE1
G
A0 – A15
ADSC
SBa
SBb
K
SE2
ADV
ADSP
SGW
SW
LBO
SE3
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8
MCM72F6•MCM72F7
2
MOTOROLA FAST SRAM
MCM72F7 BLOCK DIAGRAM
E0
G0
A0 – A15
ADSP
W0
W1
K0
V
DD
V
SS
DQ0 – DQ7
DP0
DQ8 – DQ15
DP1
V
DD
V
SS
E1
G1
64K x 18
SE1
G
A0 – A15
ADSC
SBa
SBb
K
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8
SE2
ADV
ADSP
SGW
SW
LBO
SE3
DQ16 – DQ23
DP2
DQ24 – DQ31
DP3
64K x 18
A0 – A15
ADSC
SBa
SBb
K
DQb8
DQb0 – DQb7
DQa8
DQa0 – DQa7
SE2
ADV
ADSP
SGW
SW
LBO
SE3
SE1
G
W2
W3
K1
64K x 18
SE1
G
A0 – A15
ADSC
SBa
SBb
K
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8
SE2
ADV
ADSP
SGW
SW
LBO
SE3
DQ32 – DQ39
DP4
DQ40 – DQ47
DP5
64K x 18
A0 – A15
ADSC
SBa
SBb
K
DQb8
DQb0 – DQb7
DQa8
DQa0 – DQa7
SE2
ADV
ADSP
SGW
SW
LBO
SE3
SE1
G
W4
W5
K2
64K x 18
SE1
G
A0 – A15
ADSC
SBa
SBb
K
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8
SE2
ADV
ADSP
SGW
SW
LBO
SE3
DQ48 – DQ55
DP6
DQ56 – DQ63
DP7
64K x 18
A0 – A15
ADSC
SBa
SBb
K
DQb8
DQb0 – DQb7
DQa8
DQa0 – DQa7
SE2
ADV
ADSP
SGW
SW
LBO
SE3
SE1
G
W6
W7
K3
64K x 18
SE1
G
A0 – A15
ADSC
SBa
SBb
K
DQa0 – DQa7
DQa8
DQb0 – DQb7
DQb8
SE2
ADV
ADSP
SGW
SW
LBO
SE3
64K x 18
A0 – A15
ADSC
SBa
SBb
K
DQb8
DQb0 – DQb7
DQa8
DQa0 – DQa7
SE2
ADV
ADSP
SGW
SW
LBO
SE3
SE1
G
MOTOROLA FAST SRAM
MCM72F6•MCM72F7
3
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