Motorola MCM72BB64SG66, MCM72BB32SG66, MCM72BB64SG60, MCM72BB32SG60 Datasheet
MCM72BB32•MCM72BB64
1
MOTOROLA FAST SRAM
256KB and 512KB BurstRAM
Secondary Cache Module for
Pentium
The MCM72BB32SG a nd MCM72BB64SG are designed to provide a burstable,
high performance, 256K/512K L2 cache for the Pentium microprocessor. The
modules are configured as 32K x 72 and 64K x 72 bits in a 160 pin card edge
memory module. Each module uses four of Motorola’s MCM67B518 or
MCM67B618 BiCMOS BurstRAMs.
Bursts can be initiated with either address status processor (ADSP
) or address
status controller (ADSC
). Subsequent burst addresses are generated internal to
the BurstRAM by the burst advance (ADV
) input pin.
Write cycles are internally self timed and are initiated by the rising edge of the
clock (K) input. Eight write enables are provided for byte write control.
The cache family is designed to interface with popular Pentium cache
controllers with on board tag.
PD0 – PD2 are reserved for density identification.
• Pentium–style Burst Counter on Board
• 160 Pin Card Edge Module
• Single 5 V ± 5% Power Supply
• All Inputs and Outputs are TTL Compatible
• Three State Outputs
• Byte Parity
• Byte Write Capability
• Fast Module Clock Rates: 66 MHz, 60 MHz
• Decoupling Capacitors for each Fast Static RAM
• High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes
• I/Os are 3.3 V Compatible
• Burndy Connector, Part Number: CELP2X80SC3Z48
BurstRAM is a trademark of Motorola.
Pentium is a trademark of Intel Corp.
160–LEAD
CARD EDGE
CASE 1113–01
TOP VIEW
1
42
43
80
Order this document
by MCM72BB32/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MCM72BB32
MCM72BB64
REV 1
5/95
Motorola, Inc. 1995
PIN ASSIGNMENT
160–LEAD CARD EDGE MODULE
TOP VIEW
V
SS
DQ63
VCC5
DQ61
VCC5
DQ59
DQ57
V
SS
DQP7
DQ55
DQ53
DQ51
V
SS
DQ49
DQ47
DQ45
DQ43
V
SS
DQ41
DQP5
DQ39
DQ37
DQ35
V
SS
DQ33
DQ31
DQ29
DQ27
DQ25
V
SS
DQP3
DQ23
DQ21
VCC5
DQ19
V
SS
DQ17
VCC5
DQ15
DQ13
V
SS
DQ11
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
V
SS
DQ62
VCC3*
DQ60
VCC3*
DQ58
DQ56
V
SS
DQP6
DQ54
DQ52
DQ50
V
SS
DQ48
DQ46
DQ44
DQ42
V
SS
DQ40
DQP4
DQ38
DQ36
DQ34
V
SS
DQ32
DQ30
DQ28
DQ26
DQ24
V
SS
DQP2
DQ22
DQ20
VCC3*
DQ18
V
SS
DQ16
VCC3*
DQ14
DQ12
V
SS
DQ10
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
VCC5
DQ9
DQP1
VCC5
DQ7
DQ5
DQ3
DQ1
V
SS
A3B
A4B
A5B
A6B
A7
V
SS
A9
A11
A13
A15
A17
V
SS
*A19
PD1
K0
*K2
V
SS
W7
W5
W3
W1
V
SS
ADSC1
E1
ADV1
G1
VCC5
ADSP1
V
SS
VCC3*
DQ8
DQP0
VCC3*
DQ6
DQ4
DQ2
DQ0
V
SS
A3A
A4A
A5A
A6A
A8
V
SS
A10
A12
A14
A16
A18**
V
SS
PD0
PD2
K1
K3*
V
SS
W6
W4
W2
W0
V
SS
ADSC0
E0
ADV0
G0
VCC3*
ADSP0
V
SS
PIN NAMES
A3 – A18 Address Inputs. . . . . . . . . . . . . . . . . . . . . .
K0, K1 Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
W0
– W7 Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . .
E0
, E1 Module Enable. . . . . . . . . . . . . . . . . . . . . . . .
G0, G1 Module Output Enable. . . . . . . . . . . . . . . . .
DQ0 – DQ63 Cache Data Input/Output. . . . . . . . . .
DQP0 – DQP7 Data Parity Input/Output. . . . . . . . .
ADSC0
, ADSC1 Controller Address Status. . . . . .
ADSP0, ADSP1 Processor Address Status. . . . . .
ADV0, ADV1 Burst Advance. . . . . . . . . . . . . . . . . . .
PD0 – PD2 Presence Detect. . . . . . . . . . . . . . . . . .
VCC5 + 5 V Power Supply. . . . . . . . . . . . . . . . . . . . .
V
SS
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
* No Connect for MCM72BB32/MCM72BB64
** No Connect for MCM72BB32
MCM72BB32•MCM72BB64
2
MOTOROLA FAST SRAM
PD2 PD1 PD0
Cache
Size
Module
V
SS
V
SS
NC 256KB 72BB32SG
V
SS
V
SS
V
SS
512KB 72BB64SG
MCM72BB32•MCM72BB64
3
MOTOROLA FAST SRAM
64K x 72 BurstRAM MEMORY MODULE BLOCK DIAGRAM
LW
MCM67B618
A4 – A15
ADV
K
G
E
DQ0 – DQ7
A7 – A18
E0
12
DQ8
UW
ADSP
ADSC
DQ9 – DQ16
DQ17
ADV0
ADSP0
ADSC0
K0
G0
DQ0 – DQ7
DQP0
DQ8 – DQ15
DQP1
W0
W1
8
8
LW
MCM67B618
A4 – A15
ADV
K
G
E
DQ0 – DQ7
DQ8
UW
ADSP
ADSC
DQ9 – DQ16
DQ17
DQ16 – DQ23
DQP2
DQ24 – DQ31
DQP3
W2
W3
8
8
A0 – A3A3A – A6A
A0 – A3
LW
MCM67B618
A4 – A15
ADV
K
G
E
DQ0 – DQ7
E1
DQ8
UW
ADSP
ADSC
DQ9 – DQ16
DQ17
ADV1
ADSP1
ADSC1
K1
G1
DQ32 – DQ39
DQP4
DQ40 – DQ47
DQP5
W4
W5
8
8
LW
MCM67B618
A4 – A15
ADV
K
G
E
DQ0 – DQ7
DQ8
UW
ADSP
ADSC
DQ9 – DQ16
DQ17
DQ48 – DQ55
DQP6
DQ56 – DQ63
DQP7
W6
W7
8
8
A0 – A3A3B – A6B
A0 – A3
4
4
MCM72BB32•MCM72BB64
4
MOTOROLA FAST SRAM
32K x 72 BurstRAM MEMORY MODULE BLOCK DIAGRAM
LW
MCM67B518
A4 – A14
ADV
K
G
E
DQ0 – DQ7
A7 – A17
E0
11
DQ8
UW
ADSP
ADSC
DQ9 – DQ16
DQ17
ADV0
ADSP0
ADSC0
K0
G0
DQ0 – DQ7
DQP0
DQ8 – DQ15
DQP1
W0
W1
8
8
LW
MCM67B518
A4 – A14
ADV
K
G
E
DQ0 – DQ7
DQ8
UW
ADSP
ADSC
DQ9 – DQ16
DQ17
DQ16 – DQ23
DQP2
DQ24 – DQ31
DQP3
W2
W3
8
8
A0 – A3A3A – A6A
A0 – A3
LW
MCM67B518
A4 – A14
ADV
K
G
E
DQ0 – DQ7
E1
DQ8
UW
ADSP
ADSC
DQ9 – DQ16
DQ17
ADV1
ADSP1
ADSC1
K1
G1
DQ32 – DQ39
DQP4
DQ40 – DQ47
DQP5
W4
W5
8
8
LW
MCM67B518
A4 – A14
ADV
K
G
E
DQ0 – DQ7
DQ8
UW
ADSP
ADSC
DQ9 – DQ16
DQ17
DQ48 – DQ55
DQP6
DQ56 – DQ63
DQP7
W6
W7
8
8
A0 – A3A3B – A6B
A0 – A3
4
A18 NC
4
MCM72BB32•MCM72BB64
5
MOTOROLA FAST SRAM
MCM67B618 BLOCK DIAGRAM (See Note)
BINARY
COUNTER
DQ0 – DQ8
CLR
Q0
Q1
A0
A1
K
ADSC
ADSP
A0 – A15
E
G
ADDRESS
REGISTER
WRITE
REGISTER
ENABLE
REGISTER
DATA–IN
REGISTERS
OUTPUT
BUFFER
64K
×
18
MEMORY
ARRAY
ADV
BURST LOGIC
INTERNAL
ADDRESS
A0
′
A1
′
16
9
18
16
2
A2 – A15
A1 – A0
DQ9 – DQ17
9
9 9
9
9
UW
LW
NOTE: All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the
next burst. When ADSP
is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is per-
formed using the new external address. Alternatively , an ADSP
–initiated two cycle WRITE can be performed by asserting
ADSP
and a valid address on the first cycle, then negating both ADSP and ADSC and asserting L W and/or UW with valid
data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram).
When ADSC
is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent
on W
) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded.
After the first cycle of the burst, ADV
controls subsequent burst cycles. When ADV is sampled low, the internal address
is advanced prior to the operation. When ADV
is sampled high, the internal address is not advanced, thus inserting a wait
state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See
BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW
, UW).
BURST SEQUENCE TABLE (See Note)
External Address A15 – A2 A1 A0
1st Burst Address A15 – A2 A1 A0
2nd Burst Address A15 – A2 A1 A0
3rd Burst Address A15 – A2 A1 A0
NOTE: The burst wraps around to its initial state upon completion.
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