Motorola MCM69R737AZP6, MCM69R737AZP6R, MCM69R737AZP7, MCM69R737AZP7R, MCM69R737AZP8 Datasheet

MCM69R737A•MCM69R819A

1

MOTOROLA FAST SRAM

Advance Information

4M Late Write LVTTL

The MCM69R737A/819A is a 4 megabit synchronous late write fast static RAM designed to provide high performance in secondary cache and ATM switch, Telecom, and other high speed memory applications. The MCM69R819A organized as 256K words by 18 bits, and the MCM69R737A organized as 128K words by 36 bits wide are fabricated in Motorola’s high performance silicon gate BiCMOS technology.

The differential CK clock inputs control the timing of read/write operations of the RAM. At the rising edge of the CK clock all addresses, write enables, and synchronous selects are registered. An internal buffer and special logic enable the memory to accept write data on the rising edge of the CK clock a cycle after address and control signals. Read data is driven on the rising edge of the CK clock also.

The RAM uses LVTTL 3.3 V inputs and outputs.

The synchronous write and byte enables allow writing to individual bytes or the entire word.

• Byte Write Control

• Single 3.3 V + 10%, – 5% Operation

• L VTTL 3.3 V I/O (V

DDQ

)

• Register to Register Synchronous Operation

• Asynchronous Output Enable

• Boundary Scan (JTAG) IEEE 1149.1 Compatible

• Differential Clock Inputs

• Optional x 18 or x 36 organization

• MCM69R737A/819A–5 = 5 ns

MCM69R737A/819A–6 = 6 ns MCM69R737A/819A–7 = 7 ns MCM69R737A/819A–8 = 8 ns

• Sleep Mode Operation (ZZ Pin)

• 1 19 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array

(PBGA) Package

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Order this document

by MCM69R737A/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MCM69R737A MCM69R819A

ZP PACKAGE

PBGA

CASE 999–01

REV 1 8/13/97

 Motorola, Inc. 1997

MCM69R737A•MCM69R819A 2

MOTOROLA FAST SRAM

ADDRESS

REGISTERS

SA

CK

SW

SBx

CONTROL

LOGIC

DATA IN

REGISTER

MEMORY

ARRAY

G

SW

REGISTERS

DATA OUT REGISTER

DQ

SS

REGISTERS

FUNCTIONAL BLOCK DIAGRAM

PIN ASSIGNMENTS

MCM69R737A

6543217

B C

V

SS

G

A

D E

F

H J

V

SS

V

SS

SBb V

SS

SA

V

SS

V

SS

V

SS

SA SA SA SA

NC SA SA NC

NC NC

DQb

SA SA

NC

ZZ

SW

DQa

V

DDQ

V

DDQ

DQb

V

DDQ

DQb

DQa

V

DD

V

DD

TDO

SA

TDITMS

NC

TCK

DQd DQd VSSSA

CK

V

SS

DQa

DQaSAV

SS

DQdDQd

V

DDQ

DQd V

SS

NC

DQa

DQaSBa

SBdDQdDQd

DQd DQd VSSCK V

SS

DQc

DQa

V

DD

NC

V

DD

NC

V

DD

V

DDQ

DQc VSSNC DQb

DQb DQbNCSBc

DQcDQc

V

DDQ

DQc V

SS

G

DQbSSV

SS

DQc

DQc DQc VSSNC DQb

V

DD

NC

NC NC SA NC

NC

K L M N P

R T U

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

NC

6543217

B C

V

SS

G

A

D E

F

H J

V

SS

V

SS

V

SS

V

SS

SA

V

SS

V

SS

V

SS

SA SA SA SA

NC NC NC

SA SA

NC

ZZ

SW

NC

V

DDQ

V

DDQ

NC

V

DDQ

DQa

V

DD

V

DD

TDO

NC

TDITMS

NC

TCK

NC DQb VSSSA

CK

V

SS

NC

DQaSAV

SS

NCDQb

V

DDQ

DQb V

SS

NC

DQaSBa

V

SS

NCDQb

NC DQb VSSCK V

SS

DQb

NC

V

DD

NC

V

DD

NC

V

DD

V

DDQ

NC VSSNC DQa

DQa

NCNCSBb

DQbNC

V

DDQ

NC V

SS

G

NCSSV

SS

DQbNC

DQb NC VSSNC DQa

V

DD

NC

NC NC SA NC

NC

K L M N P

R T U

V

DDQ

V

DDQ

NC

V

DDQ

V

DDQ

NC

MCM69R819A

DQc

TOP VIEW

MCM69R737A•MCM69R819A

3

MOTOROLA FAST SRAM

MCM69R737A PIN DESCRIPTIONS

PBGA Pin Locations Symbol

Type Description

4K CK Input Address, data in and control input register clock. Active high. 4L CK Input Address, data in and control input register clock. Active low.

(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P (b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H (c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H

(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P

DQx I/O Synchronous Data I/O.

4F G Input Output Enable: Asynchronous pin, active low.

2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,

5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T

SA Input Synchronous Address Inputs: Registered on the rising clock edge.

5L, 5G, 3G, 3L (a), (b), (c), (d)

SBx Input Synchronous Byte Write Enable: Enables writes to byte x in

conjunction with the SW

input. Has no effect on read cycles, active

low.

4E SS Input Synchronous Chip Enable: Registered on the rising clock edge, active

low.

4M SW Input Synchronous Write: Registered on the rising clock edge, active low.

Writes all enabled bytes. 4U TCK Input Test Clock (JTAG). 3U TDI Input Test Data In (JTAG). 5U TDO Output Test Data Out (JTAG). 2U TMS Input T est Mode Select (JTAG). 7T ZZ Input Enables sleep mode, active high.

4C, 2J, 4J, 6J, 4R, 5R V

DD

Supply Core Power Supply.

1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U V

DDQ

Supply Output Power Supply: provides operating power for output buffers.

3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H,

3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 3R

V

SS

Supply Ground.

4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C, 4D, 4G,

4H, 3J, 5J, 1R, 7R, 1T, 2T, 6T, 6U

NC — No Connection: There is no connection to the chip.

Note: 3J and 5J are tied common.

MCM69R737A•MCM69R819A 4

MOTOROLA FAST SRAM

MCM69R819A PIN DESCRIPTIONS

PBGA Pin Locations Symbol

Type Description

4K CK Input Address, data in and control input register clock. Active high. 4L CK Input Address, data in and control input register clock. Active low.

(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P

(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P

DQx I/O Synchronous Data I/O.

4F G Input Output Enable: Asynchronous pin, active low.

2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C,

6C, 4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T

SA Input Synchronous Address Inputs: Registered on the rising clock edge.

5L, 3G (a), (b)

SBx Input Synchronous Byte Write Enable: Enables writes to byte x in

conjunction with the SW

input. Has no effect on read cycles, active

low. 4E SS Input Synchronous Chip Enable: Registered on the rising clock edge, active

low. 4M SW Input Synchronous Write: Registered on the rising clock edge, active low.

Writes all enabled bytes. 4U TCK Input Test Clock (JTAG). 3U TDI Input Test Data In (JTAG). 5U TDO Output Test Data Out (JTAG). 2U TMS Input T est Mode Select (JTAG). 7T ZZ Input Enables sleep mode, active high.

4C, 2J, 4J, 6J, 4R, 5R V

DD

Supply Core Power Supply.

1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U V

DDQ

Supply Output Power Supply: provides operating power for output buffers.

3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,

3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 3R

V

SS

Supply Ground.

4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C,

2D, 4D, 7D, 1E, 6E, 2F, 1G, 4G, 6G,

2H, 4H, 7H, 3J, 5J, 1K, 6K, 2L, 7L, 6M, 2N,

7N, 1P, 6P, 1R, 7R, 1T, 4T, 6U

NC — No Connection: There is no connection to the chip.

Note: 3J and 5J are tied common.

MCM69R737A•MCM69R819A

5

MOTOROLA FAST SRAM

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V

SS

, See Note 1)

Rating

Symbol Value Unit

Core Supply Voltage V

DD

– 0.5 to + 4.6 V

Output Supply Voltage V

DDQ

– 0.5 to VDD + 0.5 V

Voltage On Any Pin V

in

– 0.5 to VDD + 0.5 V

Input Current (per I/O) I

in

± 50 mA

Output Current (per I/O) I

out

± 70 mA

Power Dissipation (See Note 2) P

D

— W

Operating Temperature T

A

0 to + 70 °C

Temperature Under Bias T

bias

–10 to + 85 °C

Storage Temperature T

stg

– 55 to + 125 °C

NOTES:

1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

2. Power dissipation capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.

PBGA PACKAGE THERMAL CHARACTERISTICS

Rating Symbol Max Unit Notes

Junction to Ambient (Still Air) R

θJA

53 °C/W 1, 2

Junction to Ambient (@200 ft/min) Single Layer Board R

θJA

38 °C/W 1, 2

Junction to Ambient (@200 ft/min) Four Layer Board R

θJA

22 °C/W

Junction to Board (Bottom) R

θJB

14 °C/W 3

Junction to Case (Top) R

θJC

5 °C/W 4

NOTES:

1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per SEMI G38–87.

3. Indicates the average thermal resistance between the die and the printed circuit board.

4. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC–883 Method 1012.1).

CLOCK TRUTH TABLE

K ZZ SS SW SBa SBb SBc SBd DQ (n) DQ (n+1) Mode

L – H L L H X X X X X D

out

0–35 Read Cycle All Bytes L – H L L L L H H H High–Z Din 0–8 Write Cycle 1st Byte L – H L L L H L H H High–Z Din 9–17 Write Cycle 2nd Byte L – H L L L H H L H High–Z Din 18–26 Write Cycle 3rd Byte L – H L L L H H H L High–Z Din 27–35 Write Cycle 4th Byte L – H L L L L L L L High–Z Din 0–35 Write Cycle All Bytes L – H L L L H H H H High–Z High–Z Abort Write Cycle L – H L H H X X X X X High–Z Deselect Cycle L – H L H L X X X X High–Z High–Z Deselect Cycle

X H X X X X X X High–Z High–Z Sleep Mode

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit.

This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established.

This device contains circuitry that will ensure the output devices are in High–Z at power up.

MCM69R737A•MCM69R819A 6

MOTOROLA FAST SRAM

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(0°C ≤ TA ≤ 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

(See Notes 1 through 4)

Parameter

Symbol Min

Typical–5Typical–6Typical–7Typical

–8

Max Unit Notes

Core Power Supply Voltage V

DD

3.15 — — — — 3.6 V

Output Driver Supply Voltage V

DDQ

3.15 — — — — 3.6 V

Active Power Supply Current (x18)

(x36)

I

DD1

— —

380 450

360 420

330 390

320 370

480 550

mA 5

Quiescent Active Power Supply Current I

DD2

— —

180 180 180 180 250 mA 6, 10

Active Standby Power Supply Current) I

SB1

— —

170 170 170 170 250 mA 7

Quiescent Standby Power Supply Current I

SB2

— —

150 150 150 150 230 mA 8, 10

Sleep Mode Power Supply Current I

SB3

— 30 30 30 30 50 mA 9, 10

NOTES:

1. All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS bumps.

2. Supply voltage applied to VDD connections.

3. Supply voltage applied to V

DDQ

connections.

4. All power supply currents measured with outputs open or deselected.

5. VDD = VDD (max), t

KHKH

= t

KHKH

(min), SS

registered active, 50% read cycles.

6. VDD = VDD (max), t

KHKH

= dc, SS

registered active.

7. VDD = VDD (max), t

KHKH

= t

KHKH

(min), SS

registered inactive.

8. VDD = VDD (max), t

KHKH

= dc, SS

registered inactive. ZZ low.

9. VDD = VDD (max), t

KHKH

= dc, SS

registered inactive, ZZ high.

10. 200 mV ≥ Vin ≥ V

DDQ

– 200 mV .

DC INPUT CHARACTERISTICS

Parameter Symbol Min Max Unit Notes

DC Input Logic High VIH (dc) 2.0 VDD + 0.3 V DC Input Logic Low VIL (dc) – 0.3 0.8 V 1 Input Leakage Current I

lkg(1)

— ± 5 µA 2

Clock Input Leakage Current I

clkg(1)

— ± 8 µA 2

Clock Input Signal Voltage V

in

– 0.3 VDD + 0.3 V

Clock Input Differential V oltage V

DIF

(dc) 0.2 VDD + 0.6 V 3

Clock Input Common Mode Voltage Range (See Figure 3) VCM (dc) 1 2.1 V 4

NOTES:

1. Inputs may undershoot to – 0.5 V (peak) for up to 20% t

KHKH

(e.g., 2 ns at a clock cycle time of 10 ns).

2. 0 V ≤ Vin ≤ V

DDQ

for all pins.

3. Minimum instantaneous differential input voltage required for differential input clock operation.

4. Maximum rejectable common mode input voltage variation.

DC OUTPUT CHARACTERISTICS

Parameter Symbol Min Max Unit Notes

Output Leakage Current I

lkg(0)

–1.0 1.0 µA

Output Low Voltage V

OL

— 0.4 V 1

Output High Voltage V

OH

2.4 — V 2

NOTES:

1. IOL = 8.0 mA.

2. IOH = – 8.0 mA.