Motorola MCM69P536CTQ7, MCM69P536CTQ5R, MCM69P536CTQ4.5, MCM69P536CTQ4.5R, MCM69P536CTQ4R Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

32K x 36 Bit Pipelined BurstRAM
Synchronous Fast Static RAM

The MCM69P536C is a 1M–bit synchronous fast static RAM designed to pro­vide a burstable, high performance, secondary cache for the 68K Family,
PowerPC, 486, i960, and Pentium microprocessors. It is organized as 32K
words of 36 bits each. This device integrates input registers, an output register,
a 2–bit address counter, and high speed SRAM onto a single monolithic circuit
for reduced parts count in cache data RAM applications. Synchronous design
allows precise cycle control with the use of an external clock (K). BiCMOS cir­cuitry reduces the overall power consumption of the integrated functions for
greater reliability .

Addresses (SA), data inputs (DQx), and all control signals except output
enable (G
positive–edge–triggered noninverting registers.

Bursts can be initiated with either ADSP
addresses can be generated internally by the MCM69P536C (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO
controlled by the burst address advance (ADV

Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx
synchronous write enable SW
bytes or to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa
controls DQa, SBb controls DQb, etc. Individual bytes are written if the selected
byte writes SBx
asserted or if all SBx

For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).

The MCM69P536C operates from a 3.3 V power supply and all inputs and
outputs are L VTTL compatible.

• MCM69P536C–4 = 4 ns Access / 7.5 ns Cycle

• Single 3.3 V + 10%, – 5% Power Supply

• ADSP, ADSC, and ADV Burst Control Pins

• Selectable Burst Sequencing Order (Linear/Interleaved)

• Internally Self–Timed Write Cycle

• Byte Write and Global Write Control

• 5 V Tolerant on all Pins (Inputs and I/Os)

• 100–Pin TQFP Package

) and Linear Burst Order (LBO) are clock (K) controlled through

or ADSC input pins. Subsequent burst

) and

) input pin.

), synchronous global write (SGW), and

are provided to allow writes to either individual

are asserted with SW. All bytes are written if either SGW is

and SW are asserted.

MCM69P536C–4.5 = 4.5 ns Access / 8 ns Cycle
MCM69P536C–5 = 5 ns Access / 10 ns Cycle
MCM69P536C–6 = 6 ns Access / 12 ns Cycle
MCM69P536C–7 = 7 ns Access / 13.3 ns Cycle

Order this document

by MCM69P536C/D

MCM69P536C

TQ PACKAGE

TQFP

CASE 983A–01

The PowerPC name is a trademark of IBM Corp., used under license therefrom.
i960 and Pentium are trademarks of Intel Corp.

REV 3
2/9/98

 Motorola, Inc. 1998

MOTOROLA FAST SRAM

MCM69P536C

1

LBO

ADV

K
ADSC
ADSP

SA
SA1
SA0

SGW

FUNCTIONAL BLOCK DIAGRAM

K2

ADDRESS

REGISTER

15

BURST

COUNTER

CLR

2

13

2

15

32K x 36 ARRAY

SW

SBa

SBb

SBc

SBd

SE1
SE2
SE3

WRITE

REGISTER

a

WRITE

REGISTER

b

WRITE

REGISTER

c

WRITE

REGISTER

d

K2 K

ENABLE

REGISTER

ENABLE

REGISTER

4

DATA–IN

REGISTER

K

36

36

DATA–OUT
REGISTER

G

MCM69P536C
2

DQa – DQd

MOTOROLA FAST SRAM

PIN ASSIGNMENT

DQc
DQc
DQc

V

DD

V

SS

DQc
DQc
DQc

DQc
V

SS

V

DD

DQc
DQc

NC

V

DD
NC

V

SS

DQd
DQd
V

DD

V

SS

DQd
DQd
DQd

DQd
V

SS

V

DD
DQd
DQd
DQd

1
2

3
4

5
6
7
8

9
10

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31 32 33

SASASE1

SE2

SBc

SBd

SBb

94 9397 96 95 89 8892 91 90 86 8587100 99 98 81828384

37 3834 35 36 42 4339 40 41 45 4644

SBa

SE3

DD

VSSV

K

SW

SGW

G

ADSP

ADSC

ADV

SA

SA

DQb

80

DQb

79

DQb

78

V

77
76
75
74
73
72
71
70

69
68
67
66
65
64
63
62
61
60
59
58
57
56
55

54
53
52
51

50494847

DD

V

SS
DQb
DQb

DQb
DQb
V

SS
V

DD
DQb
DQb

V

SS

NC

V

DD

NC

DQa
DQa
V

DD

V

SS

DQa
DQa
DQa
DQa
V

SS

V

DD

DQa
DQa
DQa

SASASA

LBO

SA

SA1

SA0

SS

NCNCNC

DD

V

V

NC

SASASA

SA

SA

NC

NC

MOTOROLA FAST SRAM

MCM69P536C

3

PIN DESCRIPTIONS

Pin Locations Symbol Type Description

85 ADSC Input Synchronous Address Status Controller: Initiates READ, WRITE, or

84 ADSP Input Synchronous Address Status Processor: Initiates READ, WRITE, or

83 ADV Input Synchronous Address Advance: Increments address count in

(a) 51, 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80

(c) 1, 2, 3, 6, 7, 8, 9, 12, 13

(d) 18, 19, 22, 23, 24, 25, 28, 29, 30

86 G Input Asynchronous Output Enable Input:

89 K Input Clock: This signal registers the address, data in, and all control signals

31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this

32, 33, 34, 35, 44, 45, 46,

47, 48, 81, 82, 99, 100

36, 37 SA1,SA0 Input Synchronous Address Inputs: These pins must be wired to the two

93, 94, 95, 96

(a) (b) (c) (d)

98 SE1 Input Synchronous Chip Enable: Active low to enable chip.

97 SE2 Input Synchronous Chip Enable: Active high for depth expansion.
92 SE3 Input Synchronous Chip Enable: Active low for depth expansion.
88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the

87 SW Input Synchronous Write: This signal writes only those bytes that have been

4, 11, 15, 20, 27, 41, 54,

61, 65, 70, 77, 91

5, 10, 17, 21, 26, 40, 55,

60, 67, 71, 76, 90

64 NC Input No Connection: There is no connection to the chip. For compatibility

14, 16, 38, 39, 42, 43, 49, 50, 66 NC — No Connection: There is no connection to the chip.

DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written

SA Input Synchronous Address Inputs: These inputs are registered and must

SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte

V

DD

V

SS

Supply Power Supply: 3.3 V + 10%, – 5%.

Supply Ground.

chip deselect cycle.

chip deselect cycle (exception — chip deselect does not occur when
ADSP

is asserted and SE1 is high).

accordance with counter type selected (linear/interleaved).

(byte a, b, c, d).

Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.

except G

signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).

meet setup and hold times.

LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.

a, b, c, d). SGW

Negated high–blocks ADSP

status of the SBx
being used, tie this pin high.

selected using the byte write SBx
are being used, tie this pin low.

reasons, it is recommended that this pin be tied low for system designs
that do not have a sleep mode associated with the cache/memory
controller. Other vendors’ RAMs may have implemented the Sleep
Mode (ZZ) feature.

and LBO.

overrides SBx.

or deselects chip when ADSC is asserted.

and SW signals. If only byte write signals SBx are

pins. If only byte write signals SBx

MCM69P536C
4

MOTOROLA FAST SRAM