Motorola MCM69F737ZP8.5, MCM69F737ZP8.5R, MCM69F737ZP8R, MCM69F737ZP7.5R, MCM69F737ZP7.5 Datasheet

MCM69F737

1

MOTOROLA FAST SRAM

128K x 36 Bit Flow–Through
BurstRAM Synchronous
Fast Static RAM

The MCM69F737 is a 4M bit synchronous fast static RAM designed to provide
a burstable, high performance, secondary cache for the PowerPC and other
high performance microprocessors. It is organized as 128K words of 36 bits
each. This device integrates input registers, a 2–bit address counter, and high
speed SRAM onto a single monolithic circuit for reduced parts count in cache
data RAM applications. Synchronous design allows precise cycle control with the
use of an external clock (K).

Addresses (SA), data inputs (DQx), and all control signals except output
enable (G

) and linear burst order (LBO) are clock (K) controlled through positive–

edge–triggered noninverting registers.

Bursts can be initiated with either ADSP

or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM69F737 (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO

) and

controlled by the burst address advance (ADV) input pin.

Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx

), synchronous global write (SGW), and synchro­nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa

controls

DQa, SBb

controls DQb, etc. Individual bytes are written if the selected byte
writes SBx are asserted with SW. All bytes are written if either SGW is asserted
or if all SBx

and SW are asserted.

For read cycles, a flow–through SRAM allows output data to simply flow freely

from the memory array.

The MCM69F737 operates from a 3.3 V core power supply and all outputs
operate on a 2.5 V or 3.3 V power supply . All inputs and outputs are JEDEC stan­dard JESD8–5 compatible.

• MCM69F737–7.5: 7.5 ns Access/8.5 ns Cycle (117 MHz)

MCM69F737–8: 8 ns Access/10 ns Cycle (100 MHz)
MCM69F737–8.5: 8.5 ns Access/11ns Cycle (90 MHz)
MCM69F737–11: 11 ns Access/20 ns Cycle (50 MHz)

• 3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply

• ADSP

, ADSC, and ADV Burst Control Pins

• Selectable Burst Sequencing Order (Linear/Interleaved)

• Single–Cycle Deselect Timing

• Internally Self–Timed Write Cycle

• Byte Write and Global Write Control

• PB1 Version 2.0 Compatible

• JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

Order this document

by MCM69F737/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MCM69F737

ZP PACKAGE

PBGA

CASE 999–02

TQ PACKAGE

TQFP

CASE 983A–01

REV 7
1/22/98

 Motorola, Inc. 1998

MCM69F737
2

MOTOROLA FAST SRAM

WRITE

REGISTER

a

WRITE

REGISTER

b

ENABLE

REGISTER

BURST

COUNTER

ADSP

G

CLR

WRITE

REGISTER

c

WRITE

REGISTER

d

SBa

SBb

SBc

SBd

SE3

15

17

SGW

K2

ADDRESS

REGISTER

17

DATA–IN

REGISTER

128K x 36

ARRAY

SE2

LBO

ADV

K

ADSC

SA
SA1
SA0

SW

SE1

K

4

36

2

2

K2

DQa – DQd

36

FUNCTIONAL BLOCK DIAGRAM

MCM69F737

3

MOTOROLA FAST SRAM

71

72

DQc

V

DDQ

DQb

69

70

66

67

68

64

65

61

62

63

3738343536 42433940 41 454644

60
59
58
57
56
55
54
53
52
51

31 3233

74

75

76

77

78

79

80

50494847

DQb

DQb

V

SS

DQb

DQb

DQb

DQb
V

SS

V

DDQ

DQb

DQb

V

DDQ

V

SS

V

SS

V

DDQ

DQc

DQc
DQc
DQc
DQc

DQc
DQc

NC

SASASE1

SBd

K

SBc

ADV

G

SA0

SASASA

SA

NC

NC

NC

LBO

SA1

V

DD

V

DD

NC

DQa

V

SS

DQa

DQa

DQa

DQa

V

SS

V

DDQ

DQa

DQa
V

SS

V

DDQ

DQa

DQa

DQd

V

DD

V

SS

V

SS

V

DDQ

DQd

DQd
DQd
DQd
DQd

73

DQc

94 93979695 89889291 90 8685871009998 81828384

10

9

12

11

15

14

13

17

16

20

19

18

21
22
23
24
25
26
27
28
29
30

7

6

5

4

3

2

1

8

SA

SA

SW

SE2

SE3

VSSV

DD

NC

NC

V

DDQ

V

SS

DQd
DQd
DQd

SA

SA

SASASA

SA

SA

NC

V

SS

ADSP

ADSC

SGW

SBa

SBb

6543217

B
C

V

SS

G

A

D
E

F

H
J

V

SS

V

SS

SBb
V

SS

SA

V

SS

V

SS

V

SS

SA SA SA SA

SA SA SA SA

NC SA SA NC

NC
NC

DQb

SA SA

NC

NC

SW

DQa

DQa

V

DDQ

V

DDQ

DQb

V

DDQ

DQb

DQb

DQa

DQa

NCV

DD

NC

SA

NCNC

NC

NC

DQd DQd VSSSA0

NC

LBO

DQa

DQaSA1V

SS

DQdDQd

V

DDQ

DQd V

SS

NC

DQa

DQaSBa

SBdDQdDQd

DQd DQd V

SS

KV

SS

DQc

DQa

V

DD

NCV

DD

NCV

DD

V

DDQ

DQc VSSSGW

DQb

DQb
DQbADV

SBcDQcDQc

V

DDQ

DQc V

SS

G

DQbSE1V

SS

DQcDQc

DQc DQc VSSNC DQb

V

DD

NC

NC SE2 SA ADSC

ADSP

K
L
M
N
P

R
T

U

V

DDQ

V

DDQ

SE3

V

DDQ

V

DDQ

NC

TOP VIEW 119 BUMP PBGA

Not to Scale

TOP VIEW 100 PIN TQFP

PIN ASSIGNMENTS

MCM69F737
4

MOTOROLA FAST SRAM

PBGA PIN DESCRIPTIONS

Pin Locations Symbol

Type Description

4B ADSC Input Synchronous Address Status Controller: Active low, interrupts any

ongoing burst and latches a new external address. Used to initiate a
READ, WRITE, or chip deselect.

4A ADSP Input Synchronous Address Status Processor: Active low, interrupts any

ongoing burst and latches a new external address. Used to initiate a
new READ, WRITE, or chip deselect (exception — chip deselect does
not occur when ADSP

is asserted and SE1 is high).

4G ADV Input Synchronous Address Advance: Increments address count in

accordance with counter type selected (linear/interleaved).

(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P

(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H

(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H

(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P

DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written

(byte a, b, c, d).

4F G Input Asynchronous Output Enable Input:

Low — enables output buffers (DQx pins).
High — DQx pins are high impedance.

4K K Input Clock: This signal registers the address, data in, and all control signals

except G

and LBO.

3R LBO Input Linear Burst Order Input: This pin must remain in steady state (this

signal not registered or latched). It must be tied high or low.
Low — linear burst counter (68K/PowerPC).
High — interleaved burst counter (486/i960/Pentium).

2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,

5C, 6C, 2R, 6R, 3T, 4T, 5T

SA Input Synchronous Address Inputs: These inputs are registered and must

meet setup and hold times.

4N, 4P SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two

LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.

5L, 5G, 3G, 3L
(a) (b) (c) (d)

SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte

a, b, c, d). SGW

overrides SBx.

4E SE1 Input Synchronous Chip Enable: Active low to enable chip.

Negated high — blocks ADSP

or deselects chip when ADSC is

asserted.
2B SE2 Input Synchronous Chip Enable: Active high for depth expansion.
6B SE3 Input Synchronous Chip Enable: Active low for depth expansion.
4H SGW Input Synchronous Global Write: This signal writes all bytes regardless of the

status of the SBx

and SW signals. If only byte write signals SBx are

being used, tie this pin high.
4M SW Input Synchronous Write: This signal writes only those bytes that have been

selected using the byte write SBx

pins. If only byte write signals SBx

are being used, tie this pin low.

4C, 2J, 4J, 6J, 4R V

DD

Supply Core Power Supply.

1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U V

DDQ

Supply I/O Power Supply.

3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H,

3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P

V

SS

Supply Ground.

1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 5R,

7R, 1T, 2T, 6T, 7T, 2U, 3U, 4U, 5U, 6U

NC — No Connection: There is no connection to the chip.

MCM69F737

5

MOTOROLA FAST SRAM

TQFP PIN DESCRIPTIONS

Pin Locations Symbol

Type Description

85 ADSC Input Synchronous Address Status Controller: Active low, interrupts any

ongoing burst and latches a new external address. Used to initiate a

READ, WRITE, or chip deselect.
84 ADSP Input Synchronous Address Status Processor: Active low, interrupts any

ongoing burst and latches a new external address. Used to initiate a

new READ, WRITE, or chip deselect (exception — chip deselect does

not occur when ADSP

is asserted and SE1 is high).

83 ADV Input Synchronous Address Advance: Increments address count in

accordance with counter type selected (linear/interleaved).

(a) 51, 52, 53, 56, 57, 58, 59, 62, 63
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30

DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written

(byte a, b, c, d).

86 G Input Asynchronous Output Enable Input:

Low — enables output buffers (DQx pins).

High — DQx pins are high impedance.
89 K Input Clock: This signal registers the address, data in, and all control signals

except G

and LBO.

31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this

signal not registered or latched). It must be tied high or low.

Low — linear burst counter (68K/PowerPC).

High — interleaved burst counter (486/i960/Pentium).

32, 33, 34, 35, 44, 45, 46,

47, 48, 49, 50, 81, 82, 99, 100

SA Input Synchronous Address Inputs: These inputs are registered and must

meet setup and hold times.

36, 37 SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two

LSBs of the address bus for proper burst operation. These inputs are

registered and must meet setup and hold times.

93, 94, 95, 96

(a) (b) (c) (d)

SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte

a, b, c, d). SGW

overrides SBx.

98 SE1 Input Synchronous Chip Enable: Active low to enable chip.

Negated high — blocks ADSP

or deselects chip when ADSC is

asserted.
97 SE2 Input Synchronous Chip Enable: Active high for depth expansion.
92 SE3 Input Synchronous Chip Enable: Active low for depth expansion.
88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the

status of the SBx

and SW signals. If only byte write signals SBx are

being used, tie this pin high.
87 SW Input Synchronous Write: This signal writes only those bytes that have been

selected using the byte write SBx

pins. If only byte write signals SBx

are being used, tie this pin low.

15, 41, 65, 91 V

DD

Supply Core Power Supply.

4, 11, 20, 27, 54, 61, 70, 77 V

DDQ

Supply I/O Power Supply.

5, 10, 17, 21, 26, 40,

55, 60, 67, 71, 76, 90

V

SS

Supply Ground.

14, 16, 38, 39, 42, 43, 64, 66 NC — No Connection: There is no connection to the chip.

MCM69F737
6

MOTOROLA FAST SRAM

TRUTH TABLE (See Notes 1 Through 5)

Next Cycle

Address

Used

SE1 SE2 SE3 ADSP ADSC ADV G

3

DQx Write 2,

4

Deselect None 1 X X X 0 X X High–Z X
Deselect None 0 X 1 0 X X X High–Z X
Deselect None 0 0 X 0 X X X High–Z X
Deselect None X X 1 1 0 X X High–Z X
Deselect None X 0 X 1 0 X X High–Z X
Begin Read External 0 1 0 0 X X 0 High–Z X

5

Begin Read External 0 1 0 1 0 X 0 High–Z READ

5

Continue Read Next X X X 1 1 0 1 High–Z READ
Continue Read Next X X X 1 1 0 0 DQ READ
Continue Read Next 1 X X X 1 0 1 High–Z READ
Continue Read Next 1 X X X 1 0 0 DQ READ
Suspend Read Current X X X 1 1 1 1 High–Z READ
Suspend Read Current X X X 1 1 1 0 DQ READ
Suspend Read Current 1 X X X 1 1 1 High–Z READ
Suspend Read Current 1 X X X 1 1 0 DQ READ
Begin Write External 0 1 0 1 0 X X High–Z WRITE
Continue Write Next X X X 1 1 0 X High–Z WRITE
Continue Write Next 1 X X X 1 0 X High–Z WRITE
Suspend Write Current X X X 1 1 1 X High–Z WRITE
Suspend Write Current 1 X X X 1 1 X High–Z WRITE

NOTES:

1. X = Don’t Care. 1 = logic high. 0 = logic low.

2. Write is defined as either 1) any SBx

and SW low or 2) SGW is low.

3. G

is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (t

GLQX

) following G going low.

4. On write cycles that follow read cycles, G

must be negated prior to the start of the write cycle to ensure proper write data setup times. G must

also remain negated at the completion of the write cycle to ensure proper write data hold times.

5. This read assumes the RAM was previously deselected.

LINEAR BURST ADDRESS TABLE (LBO = V

SS

)

1st Address (External) 2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)

X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X10 X . . . X11 X . . . X00
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X00 X . . . X01 X . . . X10

INTERLEAVED BURST ADDRESS TABLE (LBO = V

DD

)

1st Address (External)

2nd Address (Internal) 3rd Address (Internal) 4th Address (Internal)

X . . . X00 X . . . X01 X . . . X10 X . . . X11
X . . . X01 X . . . X00 X . . . X11 X . . . X10
X . . . X10 X . . . X11 X . . . X00 X . . . X01
X . . . X11 X . . . X10 X . . . X01 X . . . X00

WRITE TRUTH TABLE

Cycle Type SGW SW SBa SBb SBc SBd

Read H H X X X X
Read H L H H H H
Write Byte a H L L H H H
Write Byte b H L H L H H
Write Byte c H L H H L H
Write Byte d H L H H H L
Write All Bytes H L L L L L
Write All Bytes L X X X X X