Motorola MCM67M618BFN10, MCM67M618BFN9, MCM67M618BFN12 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

64K x 18 Bit BurstRAM
Synchronous Fast Static RAM

With Burst Counter and Self–Timed Write

The MCM67M618B is a 1,179,648 bit synchronous static random access
memory designed to provide a burstable, high–performance, secondary cache
for the MC68040 and PowerPC microprocessors. It is organized as 65,536
words of 18 bits, fabricated using Motorola’s high–performance silicon–gate
BiCMOS technology . The device integrates input registers, a 2–bit counter, high
speed SRAM, and high drive capability outputs onto a single monolithic circuit
for reduced parts count implementation of cache data RAM applications. Syn­chronous design allows precise cycle control with the use of an external clock
(K). BiCMOS circuitry reduces the overall power consumption of the integrated
functions for greater reliability .

Addresses (A0 – A15), data inputs (DQ0 – DQ17), and all control sig­nals, except output enable (G
tive–edge–triggered noninverting registers.

Bursts can be initiated with either transfer start processor (TSP
transfer start cache controller (TSC
addresses are generated internally by the MCM67M618B (burst
sequence imitates that of the MC68040) and controlled by the burst
address advance (BAA
detailed information on burst controls.

Write cycles are internally self–timed and are initiated by the rising
edge of the clock (K) input. This feature eliminates complex off–chip
write pulse generation and provides increased flexibility for incoming
signals.

Dual write enables (LW
writeable bytes. LW controls DQ0 – DQ8 (the lower bits), while UW
controls DQ9 – DQ17 (the upper bits).

This device is ideally suited for systems that require wide data bus
widths and cache memory .

• Single 5 V ± 5% Power Supply

• Fast Access Times: 9/10/12 ns Max

• Byte Writeable via Dual Write Strobes

• Internal Input Registers (Address, Data, Control)

• Internally Self–Timed Write Cycle

• TSP

, TSC, and BAA Burst Control Pins

• Asynchronous Output Enable Controlled Three–State Outputs

• Common Data Inputs and Data Outputs

• High Board Density 52–PLCC Package

• 3.3 V I/O Compatible

), are clock (K) controlled through posi-

) or

) input pins. Subsequent burst

) input pin. The following pages provide more

and UW) are provided to allow individually

DQ10

V

CC

V

SS

DQ11
DQ12
DQ13

DQ14

V

SS

V

CC

DQ15
DQ16
DQ17

Order this document

by MCM67M618B/D

MCM67M618B

FN PACKAGE

PLASTIC

CASE 778–02

PIN ASSIGNMENT

A6A7E

7654321525150494847

8DQ9
9

10
11
12
13
14
15
16
17
18
19
20

21 22 23 24 25 26 27 28 29 30 31 32 33

A5

UW

A4A3A2

LW

A1

TSC

A0

TSP

SS

V

PIN NAMES

A0 – A15 Address Inputs. . . . . . . . . . . . . . . .

K Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BAA
LW
UW
TSP

, TSC Transfer Start. . . . . . . . . . . . . . . .

E
G

DQ0 – DQ17 Data Input/Output. . . . . . . . . .

V

CC

V

SS

All power supply and ground pins must be con­nected for proper operation of the device.

G

K

A8A9A10

BAA

46
45

44
43
42
41
40
39
38
37
36
35
34

CC

A15

A14

V

Burst Address Advance. . . . . . . . . . . .

Lower Byte Write Enable. . . . . . . . . . . .

Upper Byte Write Enable. . . . . . . . . . . .

+ 5 V Power Supply. . . . . . . . . . . . . . . .

A13

Output Enable. . . . . . . . . . . . . . . . . . . . . .

Chip Enable. . . . . . . . . . . . . . . . . . . . . . . . .

A12

A11

Ground. . . . . . . . . . . . . . . . . . . . . . . . . .

DQ8
DQ7

DQ6
V

CC

V

SS

DQ5
DQ4
DQ3
DQ2
V

SS

V

CC

DQ1
DQ0

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 1
7/15/97

 Motorola, Inc. 1997

MOTOROLA FAST SRAM

MCM67M618B

1

BAA

TSC

TSP

BLOCK DIAGRAM (See Note)

BURST LOGIC

INTERNAL
ADDRESS

A1

A0

′

16

′

64K x 18

MEMORY

ARRAY

K

BINARY

COUNTER

LOAD

D1

Q1

Q0

D0

A1

EXTERNAL

A15 – A0

UW

LW

DQ0 – DQ8

DQ9 – DQ17

NOTE: All registers are positive–edge triggered. The TSC or TSP signals control the duration of the burst and the start of the next

ADDRESS

E

G

9
9

ADDRESS

REGISTERS

16

WRITE

REGISTER

ENABLE

REGISTER

A0

A15 – A2

18

DATA–IN

REGISTERS

99

9

9

OUTPUT
BUFFER

burst. When TSP is sampled low, any ongoing burst is interrupted and a read (independent of W and TSC) is performed
using the new external address. Alternatively , a TSP

–initiated two cycle WRITE can be performed by asserting TSP and
a valid address on the first cycle, then negating both TSP and TSC and asserting LW and/or UW with valid data on the
second cycle (see Single Write Cycle in WRITE CYCLES timing diagram).
When TSC

is sampled low (and TSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on
W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After
the first cycle of the burst, BAA

controls subsequent burst cycles. When BAA is sampled low, the internal address is
advanced prior to the operation. When BAA is sampled high, the internal address is not advanced, thus inserting a wait
state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state.
See BURST SEQUENCE TABLE. Write refers to either or both byte write enables (L W

, UW).

MCM67M618B
2

BURST SEQUENCE GRAPH (See Note)

0,0

′

, A0′ =

A1

NOTE: The external two values for A1 and A0

provide the starting point for the burst
sequence graph. The burst logic ad­vances A1 and A0 as shown above.

1,1

0,1

1,0

MOTOROLA FAST SRAM

SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)

E

H L X X X L–H N/A Deselected
H X L X X L–H N/A Deselected
L L X X X L–H External Address Read Cycle, Begin Burst
L H L X L L–H External Address Write Cycle, Begin Burst
L H L X H L–H External Address Read Cycle, Begin Burst
X H H L L L–H Next Address Write Cycle, Continue Burst
X H H L H L–H Next Address Read Cycle, Continue Burst
X H H H L L–H Current Address Write Cycle, Suspend Burst
X H H H H L–H Current Address Read Cycle, Suspend Burst

NOTES:

1. X means Don’t Care.

2. All inputs except G

3. Wait states are inserted by suspending burst.

TSP TSC BAA LW or UW K Address Operation

must meet setup and hold times for the low–to–high transition of clock (K).

ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)

Operation

Read L Data Out
Read H High–Z
Write X High–Z — Data In

Deselected X High–Z

NOTES:

1. X means Don’t Care.

2. For a write operation following a read operation, G
required setup time and held high through the input data hold time.

G I/O Status

must be high before the input data

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V

Rating

Power Supply Voltage V
Voltage Relative to VSS for Any Pin

Except V
Output Current (per I/O) I
Power Dissipation P
Temperature Under Bias T
Ambient Temperature T
Storage Temperature T

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

CC

exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

Symbol Value Unit

CC

Vin, V

out

D

bias

A

stg

– 0.5 to VCC + 0.5 V

out

= 0 V)

SS

– 0.5 to + 7.0 V

± 30 mA

1.6 W

– 10 to + 85 °C

0 to +70 °C

– 55 to + 125 °C

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised that
normal precautions be taken to avoid application
of any voltage higher than maximum rated volt­ages to this high–impedance circuit.

This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.

This device contains circuitry that will
ensure the output devices are in High–Z at
power up.

MOTOROLA FAST SRAM

MCM67M618B

3

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter

Supply Voltage (Operating Voltage Range) V
Input High Voltage V
Input Low Voltage V

*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA.

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA.

(Voltages Referenced to VSS = 0 V)

Symbol Min Max Unit

CC

IH
IL

4.75 5.25 V

2.2 VCC + 0.3** V

– 0.5* 0.8 V

DC CHARACTERISTICS AND SUPPLY CURRENTS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC) I
Output Leakage Current (G = VIH) I
AC Supply Current (Device Selected, All Outputs Open, MCM67M618B–9

Freq = Max) MCM67M618B–10

MCM67M618B–12

CMOS Standby Supply Current (Device Deselected, Freq = 0, VCC = Max,
All Inputs Static at CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V)

Clock Running (Device Deselected, Freq = Max, VCC = Max,
All Inputs Toggling at CMOS Levels Vin ≤ VSS + 0.2 V or ≥ VCC – 0.2 V)

Output Low Voltage (IOL = + 8.0 mA) V
Output High Voltage (IOH = – 4.0 mA) V

NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible 68040 and PowerPC

bus cycles.

lkg(I)

lkg(O)
I

CCA

I

SB2

I

SB4

OL
OH

— ± 1.0 µA
— ± 1.0 µA
— TBD mA

— TBD mA

— TBD mA

— 0.4 V

2.4 3.3 V

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

Parameter

Input Capacitance C
Input/Output Capacitance C

= 25°C, Periodically Sampled Rather Than 100% Tested)

A

Symbol Min Typ Max Unit

in

I/O

— 4 5 pF
— 6 8 pF

MCM67M618B
4

MOTOROLA FAST SRAM