Motorola MCM6205DJ15R2, MCM6205DJ15, MCM6205DJ25, MCM6205DJ20, MCM6205DJ20R2 Datasheet
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MCM6205D
1
MOTOROLA FAST SRAM
32K x 9 Bit Fast Static RAM
The MCM6205D is fabricated using Motorola’s high–performance silicon–gate
CMOS technology. Static design eliminates the need for external clocks or timing
strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is available in a plastic small–outline J–leaded package.
• Single 5 V ± 10% Power Supply
• Fully Static — No Clock or Timing Strobes Necessary
• Fast Access Times: 15, 20, and 25 ns
• Equal Address and Chip Enable Access Times
• Output Enable (G
) Feature for Increased System Flexibility and to
Eliminate Bus Contention Problems
• Low Power Operation: 130 – 140 mA Maximum AC
• Fully TTL Compatible — Three State Output
BLOCK DIAGRAM
A0 A2 A5 A8 A12 A13 A14
A1
A3
A4
A6
A7
A9
A10
A11
MEMORY MATRIX
256 ROWS x
128 x 9 COLUMNS
ROW
DECODER
INPUT
DATA
CONTROL
COLUMN I/O
COLUMN DECODER
DQ0
DQ8
E2
E1
W
G
V
CC
V
SS
Order this document
by MCM6205D/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
PIN ASSIGNMENT
MCM6205D
J PACKAGE
300 MIL SOJ
CASE 857–02
SS
NC
A8
A7
A6
A5
A4
A3
A2
A1
V
V
A14
E2
A13
CC
A9
A10
A0
NC
A11
A12
DQ7
DQ8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DQ0
DQ1
DQ2
DQ3
DQ6
DQ4
DQ5
W
G
E1
PIN NAMES
A0 – A14 Address Input. . . . . . . . . . . . .
DQ0 – DQ8 Data Input/Data Output. . .
W Write Enable. . . . . . . . . . . . . . . . . . . .
G
Output Enable. . . . . . . . . . . . . . . . . . .
E1
, E2 Chip Enable. . . . . . . . . . . . . . . . .
NC No Connection. . . . . . . . . . . . . . . . .
V
CC
Power Supply (+ 5 V). . . . . . . . . . .
V
SS
Ground. . . . . . . . . . . . . . . . . . . . . . .
REV 1
5/95
Motorola, Inc. 1994
MCM6205D
2
MOTOROLA FAST SRAM
TRUTH TABLE (X = Don’t Care)
E1
E2 G W Mode VCC Current Output Cycle
H X X X Not Selected I
SB1
, I
SB2
High–Z —
X L X X Not Selected I
SB1
, I
SB2
High–Z —
L H H H Output Disabled I
CCA
High–Z —
L H L H Read I
CCA
D
out
Read Cycle
L H X L Write I
CCA
High–Z Write Cycle
ABSOLUTE MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage V
CC
– 0.5 to + 7.0 V
Voltage Relative to VSS For Any Pin
Except V
CC
Vin, V
out
– 0.5 to VCC + 0.5 V
Output Current I
out
± 20 mA
Power Dissipation P
D
1.0 W
Temperature Under Bias T
bias
– 10 to + 85 °C
Operating Temperature T
A
0 to + 70 °C
Storage Temperature — Plastic T
stg
– 55 to + 125 °C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
Supply Voltage (Operating Voltage Range) V
CC
4.5 5.0 5.5 V
Input High Voltage V
IH
2.2 —
VCC + 0.3**
V
Input Low Voltage V
IL
– 0.5*
— 0.8 V
*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns)
**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns)
DC CHARACTERISTICS
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC) I
lkg(I)
— ± 1 µA
Output Leakage Current (E1 = VIH or G = VIH or E2 = VIL, V
out
= 0 to VCC) I
lkg(O)
— ± 1 µA
Output High Voltage (IOH = – 4.0 mA) V
OH
2.4 — V
Output Low Voltage (IOL = 8.0 mA) V
OL
— 0.4 V
POWER SUPPLY CURRENTS
Parameter Symbol – 15 – 20 – 25 Unit
AC Active Supply Current (I
out
= 0 mA, VCC = Max, f = f
max
) I
CCA
140 135 130 mA
AC Standby Current (E1 = VIH, or E2 = VIL, VCC = Max, f = f
max
) I
SB1
40 40 35 mA
CMOS Standby Current (VCC = Max, f = 0 MHz, E1 ≥ VCC – 0.2 V or
E2 ≤ VSS + 0.2 V, Vin ≤ VSS + 0.2 V, or ≥ VCC – 0.2 V)
I
SB2
20 20 20 mA
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high–impedance
circuit.
This CMOS memory circuit has been designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear
feet per minute is maintained.
MCM6205D
3
MOTOROLA FAST SRAM
CAPACITANCE (f = 1 MHz, dV = 3 V, T
A
= 25°C, Periodically sampled rather than 100% tested)
Characteristic
Symbol Max Unit
Address Input Capacitance C
in
6 pF
Control Pin Input Capacitance (E1, E2, G, W) C
in
8 pF
I/O Capacitance C
I/O
8 pF
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .
Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time 5 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .
Output Load Figure 1A Unless Otherwise Noted. . . . . . . . . . . . . . . .
READ CYCLE (See Notes 1 and 2)
MCM6205D–15 MCM6205D–20 MCM6205D–25
Parameter Symbol Min Max Min Max Min Max Unit Notes
Read Cycle Time t
AVAV
15 — 20 — 25 — ns 3
Address Access Time t
AVQV
— 15 — 20 — 25 ns
Enable Access Time t
ELQV
— 15 — 20 — 25 ns 4
Output Enable Access Time t
GLQV
— 8 — 10 — 12 ns
Output Hold from Address Change t
AXQX
4 — 4 — 4 — ns
Enable Low to Output Active t
ELQX
4 — 4 — 4 — ns 5, 6, 7
Enable High to Output High–Z t
EHQZ
0 8 0 9 0 10 ns 5, 6, 7
Output Enable Low to Output Active t
GLQX
0 — 0 — 0 — ns 5, 6, 7
Output Enable High to Output High–Z t
GHQZ
0 7 0 8 0 10 ns 5, 6, 7
Power Up Time t
ELICCH
0 — 0 — 0 — ns
Power Down Time t
EHICCL
— 15 — 20 — 25 ns
NOTES:
1. W
is high for read cycle.
2. E1
and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. All timings are referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with E
going low.
5. At any given voltage and temperature, t
EHQZ
(max) is less than t
ELQX
(min), and t
GHQZ
(max) is less than t
GLQX
(min), both for a
given device and from device to device.
6. Transition is measured ±500 mV from steady–state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected (E1
= VIL, E2 = VIH, G = VIL).
AC TEST LOADS
OUTPUT
Z0 = 50
Ω
50
Ω
VL = 1.5 V
Figure 1A Figure 1B
The table of timing values shows either a
minimum or a maximum limit for each parameter. Input requirements are specified from
the external system point of view. Thus, address setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
require it). On the other hand, responses from
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never provides data later than that time.
TIMING LIMITS
5 pF
+ 5 V
OUTPUT
255
Ω
480
Ω
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