Motorola MC74HCT240AN, MC74HCT240ADT, MC74HCT240ASD, MC74HCT240ADW Datasheet

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SEMICONDUCTOR TECHNICAL DATA

1

REV 6

 Motorola, Inc. 1995

10/95

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High–Performance Silicon–Gate CMOS

The MC74HCT240A is identical in pinout to the LS240. This device may be used as a l evel converter for interfacing TTL or NMOS outputs t o High–Speed CMOS inputs. The HCT240A is an octal inverting buffer line driver line receiver designed to be u sed with 3–state memory address drivers, clock drivers, and other bus–oriented systems. The device has inverting outputs and two active–low output enables.

The HCT240A is the inverting version of the HCT244. See also HCT241.

• Output Drive Capability: 15 LSTTL Loads

• TTL NMOS–Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 4.5 to 5.5 V

• Low Input Current: 1 µA

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 110 FETs or 27.5 Equivalent Gates

LOGIC DIAGRAM

DATA INPUTS

A1

A2

A3

A4

B1

B2

B3

B4

17

15

13

11

8

6

4

2 18

16

14

12

9

7

5

3

YB4

YB3

YB2

YB1

YA4

YA3

YA2

YA1

INVERTING OUTPUTS

PIN 20 = V

CC

PIN 10 = GND

OUTPUT

ENABLES

ENABLE A ENABLE B

1 19



PIN ASSIGNMENT

A3

A2

YB4

A1

ENABLE A

GND

YB1

A4

YB2

YB3 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

YA2

B4

YA1

ENABLE B

V

CC

B1

YA4

B2

YA3

B3

FUNCTION TABLE

Inputs Outputs

Enable A, Enable B A, B YA, YB

L L H L H L

H X Z

Z = High Impedance X = Don’t Care

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

ORDERING INFORMATION

MC74HCTXXXAN MC74HCTXXXADW MC74HCTXXXASD MC74HCTXXXADT

Plastic SOIC SSOP TSSOP

DT SUFFIX

TSSOP PACKAGE

CASE 948E–02

1

20

SD SUFFIX

SSOP PACKAGE

CASE 940C–03

1

20

1

20

1

20

MC74HCT240A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

in

DC Input Voltage (Referenced to GND)

– 1.5 to VCC + 1.5

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 35

mA

I

CC

DC Supply Current, VCC and GND Pins

± 75

mA

P

D

Power Dissipation in Still Air Plastic DIP†

SOIC Package†

TSSOP or SSOP Package†

750 500 450

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP, SOIC, TSSOP or SSOP Package)

260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP or SSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

4.5

5.5

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise and Fall Time (Figure 1)

0

500

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC V

– 55 to

25_C

v

85_C

v

125_C

Unit

V

IH

Minimum High–Level Input Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

4.5

5.5

2 2

V

IL

Maximum Low–Level Input Voltage

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

4.5

5.5

0.8

V

Vin = VIH or V

IL

|I

out

| v 20 µA

4.5

5.5

4.4

5.4

4.4

5.4

4 4

5.4

Vin = VIH or V

IL

|I

out

| v 6 mA

4.5

3.98

3.84

3.7

Vin = VIH or V

IL

|I

out

| v 20 µA

4.5

5.5

0.1

Vin = VIH or V

IL

|I

out

| v 6 mA

4.5

0.26

0.33

0.4

I

in

Maximum Input Leakage Current

Vin = VCC or GND

5.5

± 0.1

± 1.0

µA

I

OZ

Maximum Three State Leakage Current

Output in High–Impedance State Vin = VIL or V

IH

V

out

= VCC or GND

5.5

± 0.5

± 5.0

± 10

µA

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

V

OH

V

OL

Minimum High–Level Output Voltage

Maximum Low–Level Output Voltage

V

MC74HCT240A

High–Speed CMOS Logic Data DL129 — Rev 6

3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC V

– 55 to

25_C

v

85_C

v

125_C

Unit

I

CC

Maximum Quiescent Supply Current (per Package)

Vin = VCC or GND I

out

= 0 µA

5.5

4

40

160

µA

∆I

CC

≥ –55_C

25_C to 125_C

Current

Vin = VCC or GND, Other Inputs l

out

= 0 µA

2.9

2.4

NOTES:

1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the Motorola High– Speed CMOS Data Book (DL129/D).

2. Total Supply Current = ICC + Σ∆ICC.

AC ELECTRICAL CHARACTERISTICS (V

CC

= 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

– 55 to

25_C

v

85_C

v

125_C

Unit

t

PLH

,

t

PHL

Maximum Propagation Delay, A to YA or B to YB

(Figures 1 and 3)

20

25

30

ns

t

PLZ

,

t

PHZ

Maximum Propagation Delay, Output Enable to YA or YB

(Figures 2 and 4)

28

35

42

ns

t

PZL

,

t

PZH

Maximum Propagation Delay, Output Enable to YA or YB

(Figures 2 and 4)

25

31

38

ns

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

12

15

18

ns

C

in

Maximum Input Capacitance

10

pF

C

out

Maximum Three–State Output Capacitance (Output in High–Impedance State)

15

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

55

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

Additional Quiescent Supply

Vin = 2.4 V, Any One Input

5.5

mA

C

PD

Power Dissipation Capacitance (Per Enabled Output)*

pF