MOTOROLA MC74HC4020AFR2, MC74HC4020AFL2, MC74HC4020AF, MC74HC4020ADT, MC74HC4020AD Datasheet

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 2

1 Publication Order Number:

MC74HC4020A/D

MC74HC4020A

14-Stage Binary Ripple
Counter

High–Performance Silicon–Gate CMOS

The MC74C4020A is identical in pinout to the standard CMOS
MC14020B. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.

This device consists of 14 master–slave flip–flops with 12 stages
brought out to pins. The output of each flip–flop feeds the next and the
frequency at each output is half of that of the preceding one. Reset is
asynchronous and active–high.

State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with the Clock of the
HC4020A for some designs.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance With JEDEC Standard No. 7A Requirements

• Chip Complexity: 398 FETs or 99.5 Equivalent Gates

LOGIC DIAGRAM

Q1

9

Q4

7

Q5

5

Q6

4

Q7

6

Q8

13

Q9

12

Q10

14

Q11

15

Q12

1

Q13

2

Q14

3

Clock

10

Reset

11

Pin 16 = V

CC

Pin 8 = GND

1516 14 13 12 11 10

21 34567

V

CC

9

8

Q11 Q10 Q8 Q9 Reset Clock Q1

Q12 Q13 Q14 Q6 Q5 Q7 Q4

GND

Pinout: 16–Lead Plastic Package

(Top View)

SO–16

D SUFFIX

CASE 751B

http://onsemi.com

TSSOP–16
DT SUFFIX
CASE 948F

1

16

PDIP–16
N SUFFIX
CASE 648

1

16

1

16

MARKING

DIAGRAMS

1

16

MC74HC4020AN

AWLYYWW

1

16

HC4020A

AWLYWW

A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week

HC40

20A

ALYW

1

16

Device Package Shipping

ORDERING INFORMATION

MC74HC4020AN PDIP–16 2000 / Box
MC74HC4020AD SOIC–16

48 / Rail
MC74HC4020ADR2 SOIC–16 2500 / Reel
MC74HC4020ADT TSSOP–16 96 / Rail
MC74HC4020ADTR2 TSSOP–16

2500 / Reel

FUNCTION TABLE

Clock Reset Output State

X

L
L
H

No Charge

Advance to Next State

All Outputs Are Low

MC74HC4020A

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2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

V

in

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

ÎÎ

Î

P

D

ОООООООООООО

Î

Power Dissipation in Still Air Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎ

Î

750
500
450

Î

Î

mW

T

stg

Storage Temperature Range

– 65 to + 150

_

C

ÎÎ

Î

T

L

ОООООООООООО

Î

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package

ÎÎÎ

Î

260

Î

Î

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

ÎÎ

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

ÎÎ

V

CC

V

T

A

Operating Temperature Range, All Package Types

– 55

ÎÎ

+ 125

_

C

ÎÎ

Î

ÎÎ

Î

tr, t

f

ООООООООООООО

Î

ООООООООООООО

Î

Input Rise/Fall Time VCC = 2.0 V

(Figure 1) VCC = 3.0 V

VCC = 4.5 V
VCC = 6.0 V

Î

Î

Î

Î

0
0
0
0

ÎÎ

ÎÎ

ÎÎ

1000

600
500
400

Î

Î

Î

Î

ns

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol Parameter Condition

V

CC

V

–55 to 25°C ≤85°C ≤125°C

Unit

V

IH

Minimum High–Level Input
Voltage

V

out

= 0.1V or VCC –0.1V

|I

out

| ≤ 20µA

2.0

3.0

4.5

6.0

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

V

V

IL

Maximum Low–Level Input
Voltage

V

out

= 0.1V or VCC – 0.1V

|I

out

| ≤ 20µA

2.0

3.0

4.5

6.0

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

V

V

OH

Minimum High–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| ≤ 20µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

Vin =VIH or V

IL

|I

out

| ≤ 2.4mA

|I

out

| ≤ 4.0mA

|I

out

| ≤ 5.2mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.20

3.70

5.20

V

OL

Maximum Low–Level Output
Voltage

Vin = VIH or V

IL

|I

out

| ≤ 20µA

2.0

4.5

6.0

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

0.1

V

Vin = VIH or V

IL|Iout

| ≤ 2.4mA

|I

out

| ≤ 4.0mA

|I

out

| ≤ 5.2mA

3.0

4.5

6.0

0.26

0.26

0.26

0.33

0.33

0.33

0.40

0.40

0.40

This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir­cuit. For proper operation, Vin and
V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

MC74HC4020A

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3

DC CHARACTERISTICS (Voltages Referenced to GND)

Symbol Unit

Guaranteed Limit

V

CC
V

ConditionParameter

Symbol Unit≤125°C≤85°C–55 to 25°C

V

CC
V

ConditionParameter

I

in

Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA

I

CC

Maximum Quiescent Supply
Current (per Package)

Vin = VCC or GND
I

out

= 0µA

6.0 4 40 160 µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

AC CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

V

Guaranteed Limit

Symbol Parameter

V

CC

V

–55 to 25°C ≤85°C ≤125°C

Unit

f

max

Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)

2.0

3.0

4.5

6.0

10
15
30
50

9.0
14
28
50

8.0
12
25
40

MHz

t

PLH

,

t

PHL

Maximum Propagation Delay, Clock to Q1*
(Figures 1 and 4)

2.0

3.0

4.5

6.0

96
63
31
25

106

71
36
30

115

88
40
35

ns

t

PHL

Maximum Propagation Delay, Reset to Any Q
(Figures 2 and 4)

2.0

3.0

4.5

6.0

45
30
30
26

52
36
35
32

65
40
40
35

ns

t

PLH

,

t

PHL

Maximum Propagation Delay, Qn to Qn+1
(Figures 3 and 4)

2.0

3.0

4.5

6.0

69
40
17
14

80
45
21
15

90
50
28
22

ns

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output
(Figures 1 and 4)

2.0

3.0

4.5

6.0

75
27
15
13

95
32
19
15

110

36
22
19

ns

C

in

Maximum Input Capacitance 10 10 10 pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High–Speed CMOS Data Book (DL129/D).

* For TA = 25°C and CL = 50 pF , typical propagation delay from Clock to other Q outputs may be calculated with the following equations:

VCC = 2.0 V: tP = [93.7 + 59.3 (n–1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n–1)] ns
VCC = 3.0 V: tP = [61.5 + 34.4 (n–1)] ns VCC = 6.0 V: tP = [24.4 + 12 (n–1)] ns

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Package)*

38

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).