Motorola MC74HC368AD, MC74HC368ADT, MC74HC368AN Datasheet

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SEMICONDUCTOR TECHNICAL DATA

REV 0

 Motorola, Inc. 1997

1/97

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High–Performance Silicon–Gate CMOS

The MC74HC368A is identical in pinout to the LS368. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device is arranged into 2–bit and 4–bit sections, each having its own active–low Output Enable. When either of the enables is high, the affected buffer outputs are placed into high–impedance states. The HC368A has inverting outputs.

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 80 FETs or 20 Equivalent Gates

LOGIC DIAGRAM

OUTPUT ENABLE 1

OUTPUT ENABLE 2

PIN 16 = V

PIN 8 = GND

Y0A0

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

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PIN ASSIGNMENT

FUNCTION TABLE

Inputs Output

Enable 1, Enable 2 A Y

LLH LHL HXZ

X = don’t care Z = high–impedance

125

OUTPUT ENABLE 2

OUTPUT

ENABLE 1

GND

D SUFFIX

SOIC PACKAGE

16–LEAD

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

16–LEAD

CASE 648–08

ORDERING INFORMATION

MC74HCXXXAN MC74HCXXXAD MC74HCXXXADT

Plastic SOIC TSSOP

DT SUFFIX

TSSOP PACKAGE

16–LEAD

CASE 948F–01

MC74HC368A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

DC Input Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

DC Input Current, per Pin

± 20

out

DC Output Current, per Pin

± 25

DC Supply Current, VCC and GND Pins

± 50

ОООООООООООО

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎ

750 500 450

stg

ОООООООООООО

Storage Temperature

ÎÎÎÎ

– 65 to + 150

ОООООООООООО

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package

ÎÎÎÎ

260

*Maximum Ratings are those values beyond which damage to the device may occur .

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

DC Supply Voltage (Referenced to GND)

2.0

6.0

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

Operating Temperature, All Package Types

– 55

+ 125

ÎÎ

tr, t

ОООООООООООО

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

0 0 0

1000

500 400

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

ÎÎ

Symbol

ООООООО

Parameter

ООООООО

Test Conditions

ÎÎ

– 55 to

25_C

ÎÎ

85_C

ÎÎ

125_C

Unit

ÎÎ

ООООООО

Minimum High–Level Input Voltage

ООООООО

out

= 0.1 V

out

| v 20 µA

ÎÎ

2.0

4.5

6.0

ÎÎ

1.5

3.15

4.2

ÎÎ

1.5

3.15

4.2

ÎÎ

1.5

3.15

4.2

ÎÎ

ООООООО

Maximum Low–Level Input Voltage

ООООООО

out

= VCC – 0.1 V

out

| v 20 µA

ÎÎ

2.0

4.5

6.0

ÎÎ

0.3

0.9

1.2

ÎÎ

0.3

0.9

1.2

ÎÎ

0.3

0.9

1.2

ÎÎ

ООООООО

Minimum High–Level Output Voltage

ООООООО

Vin = V

out

| v 20 µA

ÎÎ

2.0

4.5

6.0

ÎÎ

1.9

4.4

5.9

ÎÎ

1.9

4.4

5.9

ÎÎ

1.9

4.4

5.9

Vin = V

out

| v 6.0 mA

out

| v 7.8 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.70

5.20

ÎÎ

ООООООО

Maximum Low–Level Output Voltage

ООООООО

Vin = V

out

| v 20 µA

ÎÎ

2.0

4.5

6.0

ÎÎ

0.1

ÎÎ

0.1

ÎÎ

0.1

Vin = V

out

| v 6.0 mA

out

| v 7.8 mA

4.5

6.0

0.26

0.33

0.40

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

µA

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

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