Motorola MC74HC367N Datasheet


SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
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High–Performance Silicon–Gate CMOS
The MC54/74HC367 is identical in pinout to the LS367. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device is arranged into 2–bit and 4–bit sections, each having its own active–low Output Enable. When either of the enables is high, the affected buffer outputs are placed into high–impedance states. The HC367 has noninverting outputs.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 92 FETs or 23 Equivalent Gates
LOGIC DIAGRAM
3
5
7
9
11
13
2
4
6
10
12
14
OUTPUT ENABLE 1
OUTPUT ENABLE 2
PIN 16 = V
CC
PIN 8 = GND
Y5
Y4
Y3
Y2
Y1
Y0A0
A1
A2
A3
A4
A5
1
15

PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
A4
Y5
A5
OUTPUT ENABLE 2
V
CC
Y3
A3
Y4
A1
Y0
A0
OUTPUT
ENABLE 1
GND
Y2
A2
Y1
FUNCTION TABLE
Inputs Output
Enable 1, Enable 2 A Y
L L L L H H H X Z
X = don’t care Z = high impedance
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
1
16
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16
ORDERING INFORMATION
MC54HCXXXJ MC74HCXXXN
Ceramic Plastic
MC54/74HC367
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
V
in
DC Input Voltage (Referenced to GND)
– 1.5 to VCC + 1.5
V
V
out
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
I
in
DC Input Current, per Pin
± 20
mA
I
out
DC Output Current, per Pin
± 35
mA
I
CC
DC Supply Current, VCC and GND Pins
± 75
mA
P
D
Power Dissipation in Still Air,Plastic or Ceramic DIP†
750
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP)
(Ceramic DIP)
260 300
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, V
out
DC Input Voltage, Output Voltage (Referenced to GND)
0
V
CC
V
T
A
Operating Temperature, All Package Types
– 55
+ 125
_
C
tr, t
f
Input Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
0 0 0
1000
500 400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
V
CC V
– 55 to
25_C
v
85_Cv 125_C
Unit
V
IH
Minimum High–Level Input Voltage
V
out
= VCC – 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
IL
Maximum Low–Level Input Voltage
V
out
= 0.1 V
|I
out
| v 20 µA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
V
OH
Minimum High–Level Output Voltage
Vin = V
IH
|I
out
| v 20 µA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = V
IH
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
V
OL
Maximum Low–Level Output Voltage
Vin = V
IL
|I
out
| v 20 µA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = V
IL
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
I
in
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
I
OZ
Maximum Three–State Leakage Current
Output in High–Impedance State Vin = VIL or V
IH
V
out
= VCC or GND
6.0
± 0.5
± 5.0
± 10
µA
I
CC
Maximum Quiescent Supply Current (per Package)
Vin = VCC or GND I
out
= 0 µA
6.0
8
80
160
µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance cir­cuit. For proper operation, Vin and V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
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