Motorola MC74HC241AN Datasheet

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SEMICONDUCTOR TECHNICAL DATA

1

REV 6

 Motorola, Inc. 1995

10/95

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High–Performance Silicon–Gate CMOS

The MC54/74HC241A is identical in pinout to the LS241. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This octal noninverting buffer/line driver/line receiver is designed to be used w ith 3–state m emory address drivers, clock d rivers, a nd other sub–oriented systems. The device has noninverted outputs and two output enables. Enable A is active–low and Enable B is active–high.

The HC241A is similar in function to the HC244A and HC240A.

• Output Drive Capability: 15 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 2 to 6 V

• Low Input Current: 1 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 134 FETs or 33.5 Equivalent Gates

LOGIC DIAGRAM

DATA

INPUTS

A1

A2

A3

A4

B1

B2

B3

B4

17

15

13

11

8

6

4

2 18

16

14

12

9

7

5

3

YB4

YB3

YB2

YB1

YA4

YA3

YA2

YA1

NONINVERTING OUTPUTS

PIN 20 = V

CC

PIN 10 = GND

OUTPUT

ENABLES

ENABLE A ENABLE B

1 19



PIN ASSIGNMENT

A3

A2

YB4

A1

ENABLE A

GND

YB1

A4

YB2

YB3 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

YA2

B4

YA1

ENABLE B

V

CC

B1

YA4

B2

YA3

B3

FUNCTION TABLE

Inputs Output Inputs Output

Enable Enable

A A YA B B YB

L L L H L L L H H H H H

H X Z L X Z

Z = high impedance

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

ORDERING INFORMATION

MC54HCXXXAJ MC74HCXXXAN MC74HCXXXADW

Ceramic Plastic SOIC

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

1

20

1

20

1

20

MC54/74HC241A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

in

DC Input Voltage (Referenced to GND)

– 1.5 to VCC + 1.5

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 35

mA

I

CC

DC Supply Current, VCC and GND Pins

± 75

mA

P

D

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

750 500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

T

L

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

(Ceramic DIP)

260 300

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

Ceramic DIP: – 10 mW/_C from 100_ to 125_C SOIC Package: – 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

+ 125

_

C

tr, t

f

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

0 0 0

1000

500 400

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

Symbol

Parameter

Test Conditions

V

CC V

– 55 to

25_C

v

85_Cv 125_C

Unit

V

IH

Minimum High–Level Input Voltage

V

out

= VCC – 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

V

IL

Maximum Low–Level Input Voltage

V

out

= 0.1 V

|I

out

| v 20 µA

2.0

4.5

6.0

0.5

1.35

1.8

0.5

1.35

1.8

0.5

1.35

1.8

V

OH

Minimum High–Level Output Voltage

Vin = V

IH

|I

out

| v 20 µA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

V

Vin = V

IH

|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.70

5.20

V

OL

Maximum Low–Level Output Voltage

Vin = V

IL

|I

out

| v 20 µA

2.0

4.5

6.0

0.1

V

Vin = V

IL

|I

out

| v 6.0 mA

|I

out

| v 7.8 mA

4.5

6.0

0.26

0.33

0.40

I

in

Maximum Input Leakage Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

µA

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

MC54/74HC241A

High–Speed CMOS Logic Data DL129 — Rev 6

3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Unit

Guaranteed Limit

V

CC

V

Test Conditions

Parameter

Symbol

Unit

v

125_C

v

85_C

– 55 to

25_C

V

CC

V

Test Conditions

Parameter

Symbol

I

OZ

Maximum Three–State Leakage Current

Output in High–Impedance State Vin = VIL or V

IH

V

out

= VCC or GND

6.0

± 0.5

± 5.0

± 10

µA

I

CC

Maximum Quiescent Supply Current (per Package)

Vin = VCC or GND I

out

= 0 µA

6.0

4

40

160

µA

NOTE: Information on typical parametric values along with high frequency or heavy load considerations, can be found in Chapter 2 of the Motorola

High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6 ns)

Guaranteed Limit

Symbol

Parameter

V

CC V

– 55 to

25_C

v

85_C

v

125_C

Unit

t

PLH

,

t

PHL

Maximum Propagation Delay, A to YA or B to YB

(Figures 1 and 3)

2.0

4.5

6.0

90 18 15

115

23 20

135

27 23

ns

t

PLZ

,

t

PHZ

Maximum Propagation Delay, Output Enable to YA or YB

(Figures 2 and 4)

2.0

4.5

6.0

110

22 19

140

28 24

165

33 28

ns

t

PZL

,

t

PZH

Maximum Propagation Delay, Output Enable to YA or YB

(Figures 2 and 4)

2.0

4.5

6.0

110

22 19

140

28 24

165

33 28

ns

t

TLH

,

t

THL

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

2.0

4.5

6.0

60 12 10

75 15 13

90 18 15

ns

C

in

Maximum Input Capacitance

—

10

pF

C

out

Maximum Three–State Output Capacitance (Output in High–Impedance State)

—

15

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–

Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Transceiver Channel)*

34

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

Motorola MC74HC241AN Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual