MOTOROLA MC74HC139AN, MC74HC139AF, MC74HC139AFEL, MC74HC139AFL1, MC74HC139AFL2 Datasheet

 Semiconductor Components Industries, LLC, 2000

March, 2000 – Rev. 7

1 Publication Order Number:

MC74HC139A/D

MC74HC139A

Dual 1-of-4 Decoder/ Demultiplexer

High–Performance Silicon–Gate CMOS

The MC74HC139A is identical in pinout to the LS139. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.

This device consists of two independent 1–of–4 decoders, each of which decodes a two–bit Address to one–of–four active–low outputs. Active–low Selects are provided to facilitate the demultiplexing and cascading functions. The demultiplexing function is accomplished by using the Address inputs to select the desired device output, and utilizing the Select as a data input.

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL

• Operating Voltage Range: 2.0 to 6.0 V

• Low Input Current: 1.0 µA

• High Noise Immunity Characteristic of CMOS Devices

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 100 FETs or 25 Equivalent Gates

LOGIC DIAGRAM

A0

a

A1

a

SELECT

a

A0

b

A1

b

1

SELECT

b

Y0

a

Y1

a

Y2

a

Y3

a

Y0

b

Y1

b

Y2

b

Y3

b

ACTIVE–LOW

OUTPUTS

ADDRESS

INPUTS

PIN 16 = V

CC

PIN 8 = GND

ACTIVE–LOW

OUTPUTS

3

2

ADDRESS

INPUTS

13

14

15

4 5 6 7

12 11 10

9

FUNCTION TABLE

Inputs Outputs

Select A1 A0 Y0 Y1 Y2 Y3

HXXHHHH LLLLHHH LLHHLHH LHLHHLH LHHHHHL

X = don’t care

SO–16

D SUFFIX

CASE 751B

http://onsemi.com

1

16

PDIP–16 N SUFFIX CASE 648

1

16

MARKING

DIAGRAMS

1

16

MC74HC139AN

AWLYYWW

1

16

HC139A

AWLYWW

A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week

Device Package Shipping

ORDERING INFORMATION

MC74HC139AN PDIP–16 2000 / Box MC74HC139AD SOIC–16

48 / Rail

MC74HC139ADR2 SOIC–16 2500 / Reel

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

SELECT

a

A1

a

A0

a

GND

A1

b

A0

b

SELECT

b

V

CC

Y0

a

Y1

a

Y2

a

Y3

a

Y0

b

Y1

b

Y2

b

Y3

b

MC74HC139A

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2

MAXIMUM RATINGS*

Symbol

Parameter

Value

Unit

V

CC

DC Supply Voltage (Referenced to GND)

– 0.5 to + 7.0

V

in

DC Input Voltage (Referenced to GND)

– 1.5 to VCC + 1.5

V

out

DC Output Voltage (Referenced to GND)

– 0.5 to VCC + 0.5

V

I

in

DC Input Current, per Pin

± 20

mA

I

out

DC Output Current, per Pin

± 25

mA

I

CC

DC Supply Current, VCC and GND Pins

± 50

mA

P

D

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

750 500

mW

T

stg

Storage Temperature

– 65 to + 150

_

C

ÎÎ

Î

T

L

ОООООООООООО

Î

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic DIP or SOIC Package)

ÎÎÎ

Î

260

Î

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

ÎÎ

Max

Unit

V

CC

DC Supply Voltage (Referenced to GND)

2.0

ÎÎ

6.0

V

Vin, V

out

DC Input Voltage, Output Voltage (Referenced to GND)

0

ÎÎ

V

CC

V

T

A

Operating Temperature, All Package Types

– 55

ÎÎ

+ 125

_

C

ÎÎ

Î

tr, t

f

ООООООООООООО

Î

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

Î

0 0 0

ÎÎ

1000

500 400

Î

ns

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit

ÎÎ

Î

Symbol

ООООООО

Î

Parameter

ООООООО

Î

Test Conditions

ÎÎ

Î

V

CC V

ÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Unit

ÎÎ

Î

V

IH

ООООООО

Î

Minimum High–Level Input Voltage

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

1.5

3.15

4.2

ÎÎÎ

Î

1.5

3.15

4.2

ÎÎ

Î

1.5

3.15

4.2

Î

V

ÎÎ

Î

V

IL

ООООООО

Î

Maximum Low–Level Input Voltage

ООООООО

Î

V

out

= 0.1 V or VCC – 0.1 V

|I

out

| v 20 µA

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

0.5

1.35

1.8

ÎÎÎ

Î

0.5

1.35

1.8

ÎÎ

Î

0.5

1.35

1.8

Î

V

ÎÎ

Î

ÎÎ

Î

V

OH

ООООООО

Î

ООООООО

Î

Minimum High–Level Output Voltage

ООООООО

Î

ООООООО

Î

Vin = VIH or V

IL

|I

out

| v 20 µA

ÎÎ

Î

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

ÎÎ

Î

1.9

4.4

5.9

ÎÎÎ

Î

1.9

4.4

5.9

ÎÎ

Î

ÎÎ

Î

1.9

4.4

5.9

Î

V

Vin = VIH or VIL|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

4.5

6.0

3.98

5.48

ÎÎÎ

3.84

5.34

3.70

5.20

ÎÎ

Î

V

OL

ООООООО

Î

Maximum Low–Level Output Voltage

ООООООО

Î

Vin = VIH or V

IL

|I

out

| v 20 µA

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

0.1

ÎÎÎ

Î

0.1

ÎÎ

Î

0.1

Î

V

ÎÎÎОООООООÎООООООО

Î

Vin = VIH or VIL|I

out

| v 4.0 mA

|I

out

| v 5.2 mA

ÎÎ

Î

4.5

6.0

ÎÎ

Î

0.26

ÎÎÎ

Î

0.33

ÎÎ

Î

0.40

Î

ÎÎ

Î

I

in

ООООООО

Î

Maximum Input Leakage Current

ООООООО

Î

Vin = VCC or GND

ÎÎ

Î

6.0

ÎÎ

Î

± 0.1

ÎÎÎ

Î

± 1.0

ÎÎ

Î

± 1.0

Î

µA

I

CC

Maximum Quiescent Supply Current (per Package)

Vin = VCC or GND I

out

= 0 µA

6.0

4

ÎÎÎ

40

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and V

out

should be constrained to the

range GND v (Vin or V

out

) v VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

MC74HC139A

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3

AC ELECTRICAL CHARACTERISTICS (C

L

= 50 pF, Input tr = tf = 6.0 ns)

Guaranteed Limit

ÎÎÎ

Î

Symbol

ОООООООООООООО

Î

Parameter

ÎÎ

Î

V

CC V

ÎÎ

Î

– 55 to

25_C

ÎÎÎ

Î

v

85_C

ÎÎ

Î

v

125_C

Î

Unit

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООО

Î

Maximum Propagation Delay, Select to Output Y

(Figures 1 and 3)

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

115

23 20

ÎÎÎ

Î

145

29 25

ÎÎ

Î

175

35 30

Î

ns

ÎÎÎ

Î

t

PLH

,

t

PHL

ОООООООООООООО

Î

Maximum Propagation Delay, Input A to Output Y

(Figures 2 and 3)

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

115

23 20

ÎÎÎ

Î

145

29 25

ÎÎ

Î

175

35 30

Î

ns

ÎÎÎ

Î

t

TLH

,

t

THL

ОООООООООООООО

Î

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

ÎÎ

Î

2.0

4.5

6.0

ÎÎ

Î

75 15 13

ÎÎÎ

Î

95 19 16

ÎÎ

Î

110

22 19

Î

ns

C

in

Maximum Input Capacitance

—

10

ÎÎÎ

10

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

C

PD

Power Dissipation Capacitance (Per Decoder)*

55

pF

*Used to determine the no–load dynamic power consumption: PD = CPD V

CC

2

f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).

SWITCHING W AVEFORMS

t

THL

t

TLH

Figure 1.

V

CC

GND

t

r

t

PHL

t

PLH

OUTPUT Y

SELECT

90%

50%

10%

90%

50%

10%

Figure 2.

50%

t

PHL

t

PLH

V

CC

GND

OUTPUT Y

50%

INPUT A

*Includes all probe and jig capacitance

Figure 3. Test Circuit

CL*

TEST POINT

DEVICE UNDER

TEST

OUTPUT

t

f

VALID VALID

MOTOROLA MC74HC139AN, MC74HC139AF, MC74HC139AFEL, MC74HC139AFL1, MC74HC139AFL2 Datasheet

Specifications and Main Features

Frequently Asked Questions

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