SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
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High–Performance Silicon–Gate CMOS
The MC54/74HC132A is identical in pinout to the LS132. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC132A can be used to enhance noise immunity or to square up
slowly changing waveforms.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 72 FETs or 18 Equivalent Gates
LOGIC DIAGRAM
A1
B1
Y1
3
2
1
PIN 14 = V
CC
PIN 7 = GND
Y = AB
A2
B2
Y2
6
5
4
A3
B3
Y3
8
10
9
A4
B4
Y4
11
13
12
FUNCTION TABLE
PIN ASSIGNMENT
Inputs Output
A B Y
L L H
L H H
H L H
H H L
11
12
13
14
8
9
105
4
3
2
1
7
6
B3
Y4
A4
B4
V
CC
Y3
A3
A2
Y1
B1
A1
GND
Y2
B2
D SUFFIX
SOIC PACKAGE
CASE 751A–03
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
Ceramic
Plastic
SOIC
1
14
1
14
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
1
14
ORDERING INFORMATION
MC54/74HC132A
MOTOROLA High–Speed CMOS Logic Data
DL129 — Rev 6
2
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air,Plastic or Ceramic DIP†
SOIC Package†
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
ns
*When Vin X 0.5 VCC, ICC >> quiescent current.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Maximum Positive–Going
Input Threshold Voltage
(Figure 3)
V
out
= 0.1 V
|I
out
| v 20 µA
Minimum Positive–Going
Input Threshold Voltage
(Figure 3)
V
out
= 0.1 V
|I
out
| v 20 µA
Maximum Negative–Going
Input Threshold Voltage
(Figure 3)
V
out
= VCC – 0.1 V
|I
out
| v 20 µA
Minimum Negative–Going
Input Threshold Voltage
(Figure 3)
V
out
= VCC – 0.1 V
|I
out
| v 20 µA
Maximum Hysteresis Voltage
(Figure 3)
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
Minimum Hysteresis Voltage
(Figure 3)
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
V
NOTE: 1. VHmin > (VT+ min) – (VT– max); VHmax = (VT+ max) + (VT– min).
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.