Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 7
1 Publication Order Number:
MC74HC132A/D
MC74HC132A
Quad 2-Input NAND Gate
with Schmitt-Trigger Inputs
High–Performance Silicon–Gate CMOS
The MC74HC132A is identical in pinout to the LS132. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The HC132A can be used to enhance noise immunity or to square up
slowly changing waveforms.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 72 FETs or 18 Equivalent Gates
LOGIC DIAGRAM
A1
B1
Y1
3
2
1
PIN 14 = V
CC
PIN 7 = GND
Y = AB
A2
B2
Y2
6
5
4
A3
B3
Y3
8
10
9
A4
B4
Y4
11
13
12
FUNCTION TABLE
Inputs Output
ABY
LLH
LHH
HLH
HHL
Device Package Shipping
ORDERING INFORMATION
MC74HC132AN PDIP–14 2000 / Box
MC74HC132AD SOIC–14
http://onsemi.com
55 / Rail
MC74HC132ADR2 SOIC–14 2500 / Reel
MARKING
DIAGRAMS
A = Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
1
14
PDIP–14
N SUFFIX
CASE 646
MC74HC132AN
AWLYYWW
SOIC–14
D SUFFIX
CASE 751A
1
14
HC132A
AWLYWW
PIN ASSIGNMENT
11
12
13
14
8
9
105
4
3
2
1
7
6
B3
Y4
A4
B4
V
CC
Y3
A3
A2
Y1
B1
A1
GND
Y2
B2
MC74HC132A
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2
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, VCC and GND Pins
Power Dissipation in Still Air, Plastic DIP†
SOIC Package†
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
ns
*When Vin X 0.5 VCC, ICC >> quiescent current.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Maximum Positive–Going
Input Threshold Voltage
(Figure 3)
V
out
= 0.1 V
|I
out
| v 20 µA
Minimum Positive–Going
Input Threshold Voltage
(Figure 3)
V
out
= 0.1 V
|I
out
| v 20 µA
Maximum Negative–Going
Input Threshold Voltage
(Figure 3)
V
out
= VCC – 0.1 V
|I
out
| v 20 µA
Minimum Negative–Going
Input Threshold Voltage
(Figure 3)
V
out
= VCC – 0.1 V
|I
out
| v 20 µA
Maximum Hysteresis Voltage
(Figure 3)
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
Minimum Hysteresis Voltage
(Figure 3)
V
out
= 0.1 V or VCC – 0.1 V
|I
out
| v 20 µA
V
NOTE: 1. VHmin > (VT+ min) – (VT– max); VHmax = (VT+ max) + (VT– min).
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HC132A
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3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Minimum High–Level Output
Voltage
Vinv
VT– min or VT+ max
|I
out
| v 20 µA
Vinv
–VT– min or VT+ max
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
Maximum Low–Level Output
Voltage
Vin ≥VT+ max
|I
out
| v 20 µA
Vin≥VT+ max |I
out
| v 4.0 mA
|I
out
| v 5.2 mA
Maximum Input Leakage
Current
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
I
out
= 0 µA
µA
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input tr = tf = 6.0 ns)
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
Maximum Input Capacitance
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Gate)*
24
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
Figure 1. Switching Waveforms
r
V
CC
GND
90%
50%
10%
90%
50%
10%
INPUT
A OR B
Y
t
PHL
t
PLH
t
THL
t
TLH
*Includes all probe and jig capacitance
Figure 2. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT