Motorola MC74F579DW, MC74F579J, MC74F579N Datasheet
4-229
FAST AND LS TTL DATA
8-BIT BIDIRECTIONAL
BINARY COUNTER (3-STATE)
The MC74F579 is a fully synchronous 8-stage up/down counter with multiplexed 3-state I/O ports for bus-oriented applications. It features a preset
capability for programmable operation, carry look-ahead for easy cascading
and a U/D
input to control the direction of counting. All state changes, except
for the case of asynchronous reset, are initiated by the rising edge of the clock.
TC
output is not recommended for use as a clock or asynchronous reset due
to the possibility of decoding spikes.
• Multiplexed 3-State I/O Ports For Bus-oriented Applications
• Built-In Cascading Carry Capability
• Count Frequency 115 MHz Typ
• Supply Current 100 mA Typ
• Fully Synchronous Operation
• U/D Pin to Control Direction of Counting
• Separate Pins for Master Reset and Synchronous Reset
• Center Power Pins to Reduce Effects of Package Inductance
• See F269 for 24-Pin Separate I/O Port Version
• See F779 for 16-Pin Version
• ESD Protection > 4000 Volts
PIN ASSIGNMENT
18 17 16 15 14 13
1 2 3 4 5 6
7
20 19
8
MR
CP
SR
CEP CET V
CC
U/DTC PE
I/O0I/O1I/O2I/O3GND I/O4I/O
5
9 10
I/O6I/O
7
12 11
CS
OE
MR SR
CEP
CET
TC
PE CS
OE
U/D
CP
I/O0I/O1I/O
2
I/O3I/O
4
I/O5I/O6I/O
7
18
17
11
1
2 3 4
5 6
7 8 9
15
20 1913 12 14
LOGIC SYMBOL
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 4.5 5.0 5.5 V
T
A
Operating Ambient Temperature Range 0 25 70 °C
TC –1.0
IOHOutput Current — High
I/O
n
–3.0
mA
TC 20
IOLOutput Current — Low
I/O
n
24
mA
MC74F579
8-BIT BIDIRECTIONAL
BINARY COUNTER (3-STATE)
FAST SCHOTTKY TTL
ORDERING INFORMATION
MC74FXXXJ Ceramic
MC74FXXXN Plastic
MC74FXXXDW SOIC
20
1
J SUFFIX
CERAMIC
CASE 732-03
20
1
N SUFFIX
PLASTIC
CASE 738-03
20
1
DW SUFFIX
SOIC
CASE 751D-03
4-230
FAST AND LS TTL DATA
MC74F579
FUNCTION TABLE
MR SR CS PE CEP CET U/D OE CP Function
X X H X X X X X X I/O0 to I/O7 in Hi-Z (PE disabled)
X X L H X X X H X I/O0 to I/O7 in Hi-Z
X X L H X X X L X Flip-Flop outputs appear on I/O lines
L X X X X X X X X Asynchronous reset for all flip-flops
H L X X X X X X ↑ Synchronous reset for all flip-flops
H H L L X X X X ↑ Parallel load all flip-flops
H H (not LL) H X X X ↑ Hold
H H (not LL) X H X X ↑ Hold (TC held high)
H H (not LL) L L H X ↑ Count up
H H (not LL) L L L X ↑ Count down
H = High voltage level L = Low voltage level
X = Don’t care ↑ = Low-to-High clock transition
(not LL) = CS and PE should never both be low voltage at the same time
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
74F
Test Conditions
Symbol
Parameter
Min Typ (2) Max
Unit
Test Conditions
(Note 1)
2.5
IOH = –1.0 mA
VCC = 4.5 V
TC
2.7 3.4
V
VIL = MAX
VIH = MIN
VCC = 4.75 V
VOHOutput HIGH Voltage
2.4 3.3
IOH = –3.0 mA
VCC = 4.5 V
I/O
n
2.7 3.3
V
VIL = MAX
VIH = MIN
VCC = 4.75 V
TC
IOL = 20 mA
VCC = 4.5 V
VOLOutput LOW Voltage
I/O
n
0.35
0.5
V
IOL = 24 mA
VIL = MAX
VIH = MIN
V
IK
Input Clamp Diode Voltage –0.73 –1.2 V VCC = 4.5 V, IIN = –18 mA
I/O
n
1.0 mA
VIN = 5.5 V
others 100 µA
VCC = 5.5 V
VIN = 7.0 V
IIHInput HIGH Current
I/O
n
70
others 20
µA
VCC = 5.5 V, VIN = 2.7 V
I
IL
Input LOW Current
Except
I/O
n
–0.6 mA VCC = 5.5 V, VIN = 0.5 V
I
OZH
OFF-State Current
High-Level Voltage Applied
70
V
OUT
= 2.7 V
I
OZL
OFF-State Current
Low-Level Voltage Applied
I/O
n
–600
µA
VCC = 5.5 V
V
OUT
= 0.5 V
I
OS
Output Short Circuit Current (Note 3) –60 –80 –150 mA VCC = MAX, V
OUT
= 0 V
I
CCH
95 135
I
CC
Total Supply Current (total)
I
CCL
105 145
mA VCC = MAX
CC
I
CCZ
105 150
CC
= MAX
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under guaranteed operating conditions for the applicable device type.
2. All typical values are at VCC = 5.0 V, TA = 25°C.
3. Not more than one output should be shorted at a time. For IOS testing, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a HIGH output may raise the chip
temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last.
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