Motorola MC74ACT563N, MC74ACT563DW, MC74AC563N, MC74AC563DW Datasheet
5-1
FACT DATA
The MC74AC563/74ACT563 is a high-speed octal latch with buffered common
Latch Enable (LE) and buffered common Output Enable (OE
) inputs.
The MC74AC563/74ACT563 device is functionally identical to the MC74AC573/
74ACT573, but with inverted outputs.
• Inputs and Outputs on Opposite Sides of Package
Allowing Easy Interface with Microprocessors
• Useful as Input or Output Port for Microprocessors
• Functionally Identical to MC74AC573/74ACT573 but with
Inverted Outputs
• Outputs Source/Sink 24 mA
• ′ACT563 Has TTL Compatible Inputs
1920 18 17 16 15 14
21 3 4 5 6 7
V
CC
13
8
12
9
11
10
O0O1O2O3O4O5O6O7LE
OE
D0D1D2D3D4D5D6D7GND
PIN NAMES
D0–D7Data Inputs
LE Latch Enable Input
OE
3-State Output Enable Input
O0–O73-State Latch Outputs
OCTAL D-TYPE
LATCH WITH
3-STATE OUTPUTS
N SUFFIX
CASE 738-03
PLASTIC
DW SUFFIX
CASE 751D-04
PLASTIC
LOGIC SYMBOL
O0O1O2O3O4O5O6O
7
D0D1D2D3D4D5D6D
7
LE
OE
MC74AC563 MC74ACT563
5-2
FACT DATA
FUNCTIONAL DESCRIPTION
The MC74AC563/74ACT563 contains eight D-type
latches with 3-state complementary outputs. When the Latch
Enable (LE) input is HIGH, data on the Dn inputs enters the
latches. In this condition the latches are transparent, i.e., a
latch output will change state each time its D input changes.
When LE is LOW the latches store the information that was
present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-state buffers are
controlled by the Output Enable (OE
) input. When OE is LOW,
the buffers are in the bi-state mode. When OE
is HIGH the
buffers are in the high impedance mode but that does not
interfere with entering new data into the latches.
FUNCTION TABLE
Inputs Internal Outputs
OE LE D Q O
Function
H X X X Z High Z
H H L H Z High Z
H H H L Z High Z
H L X NC Z Latched
L H L H H Transparent
L H H L L Transparent
L L X NC NC Latched
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
D
C
Q
D
1
D
2
D
3
D
4
D
5
D
6
D
7
LE
OE
O
1
O
2
O
3
O
4
O
5
O
6
O
7
O
8
D
0
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
LOGIC DIAGRAM
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
MC74AC563 MC74ACT563
5-3
FACT DATA
MAXIMUM RATINGS*
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
V
in
DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V
V
out
DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Sink/Source Current, per Pin ±50 mA
I
CC
DC VCC or GND Current per Output Pin ±50 mA
T
stg
Storage Temperature –65 to +150 °C
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended
Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
′AC 2.0 5.0 6.0
VCCSupply Voltage
′ACT 4.5 5.0 5.5
V
Vin, V
out
DC Input Voltage, Output Voltage (Ref. to GND) 0 V
CC
V
VCC @ 3.0 V 150
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
VCC @ 4.5 V 40 ns/V
r
, t
f
′AC Devices except Schmitt Inputs
VCC @ 5.5 V 25
VCC @ 4.5 V 10
tr, t
f
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
VCC @ 5.5 V 8.0
ns/V
T
J
Junction Temperature (PDIP) 140 °C
T
A
Operating Ambient Temperature Range –40 25 85 °C
I
OH
Output Current — High –24 mA
I
OL
Output Current — Low 24 mA
1. Vin from 30% to 70% VCC; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. Vin from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
tr, t
f
Input Rise and Fall Time (Note 2)
Loading...